Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 527 1 T9 7 T10 1 T11 9
all_values[1] 552 1 T1 2 T9 5 T10 1
all_values[2] 455 1 T8 1 T9 9 T11 6
all_values[3] 442 1 T9 9 T10 1 T11 5
all_values[4] 477 1 T9 8 T10 1 T11 4
all_values[5] 492 1 T9 2 T10 1 T11 4
all_values[6] 501 1 T9 9 T10 1 T11 3
all_values[7] 542 1 T1 1 T9 8 T10 1
all_values[8] 480 1 T1 1 T8 1 T9 4
all_values[9] 521 1 T8 1 T9 3 T11 9
all_values[10] 446 1 T8 1 T9 2 T11 5
all_values[11] 497 1 T8 1 T9 4 T11 4
all_values[12] 516 1 T8 1 T9 3 T11 3
all_values[13] 510 1 T9 2 T11 6 T20 7
all_values[14] 480 1 T9 4 T10 3 T11 4
all_values[15] 508 1 T8 1 T9 7 T11 3
all_values[16] 499 1 T8 1 T9 5 T10 1
all_values[17] 466 1 T9 3 T11 2 T20 4
all_values[18] 475 1 T1 1 T8 1 T9 6
all_values[19] 496 1 T9 4 T11 10 T20 4
all_values[20] 508 1 T9 6 T11 10 T20 3
all_values[21] 540 1 T8 3 T9 5 T11 4
all_values[22] 447 1 T9 3 T11 4 T20 8
all_values[23] 526 1 T1 1 T9 4 T10 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%