Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1661	1			T8	5		T9	16		T10	1
all_values[1]	1699	1			T8	6		T9	18		T10	3
all_values[2]	1705	1			T8	4		T9	24		T11	12
all_values[3]	1754	1			T8	2		T9	18		T10	1
all_values[4]	1680	1			T8	3		T9	16		T11	14
all_values[5]	1674	1			T8	2		T9	19		T10	1
all_values[6]	1743	1			T8	5		T9	21		T10	2
all_values[7]	1584	1			T8	6		T9	16		T10	2
all_values[8]	1641	1			T8	8		T9	15		T10	1
all_values[9]	1688	1			T8	2		T9	19		T10	1
all_values[10]	1680	1			T8	3		T9	16		T11	28
all_values[11]	1737	1			T8	6		T9	16		T10	1
all_values[12]	1665	1			T8	4		T9	13		T10	1
all_values[13]	1725	1			T8	5		T9	14		T11	16
all_values[14]	1759	1			T8	5		T9	18		T10	1
all_values[15]	1658	1			T8	3		T9	9		T10	2
all_values[16]	1690	1			T9	13		T10	1		T11	25
all_values[17]	1644	1			T8	3		T9	21		T10	1
all_values[18]	1658	1			T8	3		T9	20		T10	2
all_values[19]	1678	1			T8	3		T9	14		T11	15
all_values[20]	1609	1			T8	4		T9	14		T11	17
all_values[21]	1737	1			T8	4		T9	15		T10	2
all_values[22]	1723	1			T8	6		T9	22		T10	2
all_values[23]	1676	1			T8	14		T9	21		T10	1
all_values[24]	1674	1			T8	2		T9	16		T11	15
all_values[25]	1701	1			T8	2		T9	15		T11	10
all_values[26]	1679	1			T8	7		T9	16		T10	1
all_values[27]	1745	1			T8	6		T9	19		T10	1
all_values[28]	1638	1			T8	4		T9	16		T10	1
all_values[29]	1637	1			T8	7		T9	21		T10	2
all_values[30]	1674	1			T8	7		T9	9		T11	26
all_values[31]	1717	1			T8	4		T9	17		T11	27
all_values[32]	1658	1			T8	5		T9	17		T10	1
all_values[33]	1653	1			T8	3		T9	16		T10	2
all_values[34]	1678	1			T8	4		T9	13		T10	1
all_values[35]	1676	1			T8	7		T9	27		T10	1
all_values[36]	1670	1			T8	3		T9	25		T11	10
all_values[37]	1669	1			T9	16		T10	2		T11	22
all_values[38]	1715	1			T8	5		T9	14		T11	22
all_values[39]	1696	1			T8	2		T9	15		T11	30
all_values[40]	1668	1			T8	5		T9	15		T10	1
all_values[41]	1724	1			T8	4		T9	13		T10	1
all_values[42]	1601	1			T8	7		T9	14		T10	1
all_values[43]	1672	1			T8	3		T9	10		T10	1
all_values[44]	1668	1			T8	4		T9	14		T11	17
all_values[45]	1632	1			T8	6		T9	18		T10	1
all_values[46]	1605	1			T8	5		T9	18		T10	1
all_values[47]	1647	1			T8	3		T9	18		T10	1
all_values[48]	1730	1			T8	4		T9	21		T10	1
all_values[49]	1695	1			T8	6		T9	13		T10	2
all_values[50]	1640	1			T8	6		T9	20		T10	2
all_values[51]	1686	1			T8	5		T9	16		T10	1
all_values[52]	1625	1			T8	1		T9	19		T10	1
all_values[53]	1662	1			T8	3		T9	16		T10	1
all_values[54]	1681	1			T8	4		T9	14		T10	1
all_values[55]	1611	1			T8	4		T9	14		T10	1
all_values[56]	1671	1			T8	3		T9	17		T10	2
all_values[57]	1708	1			T8	2		T9	21		T10	2
all_values[58]	1683	1			T8	6		T9	13		T11	33
all_values[59]	1742	1			T8	4		T9	17		T11	22
all_values[60]	1680	1			T8	7		T9	17		T10	1
all_values[61]	1770	1			T8	1		T9	19		T10	2
all_values[62]	1700	1			T8	6		T9	16		T11	21
all_values[63]	1725	1			T8	2		T9	13		T10	2