Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
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Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 64 0 64 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1737 1 T7 3 T35 1 T153 2
all_values[1] 1691 1 T2 1 T7 4 T35 2
all_values[2] 1781 1 T2 1 T7 4 T35 2
all_values[3] 1693 1 T7 2 T35 1 T153 4
all_values[4] 1714 1 T7 4 T35 1 T153 1
all_values[5] 1798 1 T7 4 T35 2 T153 3
all_values[6] 1662 1 T2 1 T7 2 T35 4
all_values[7] 1719 1 T2 1 T7 2 T35 1
all_values[8] 1735 1 T2 1 T7 2 T35 4
all_values[9] 1752 1 T7 5 T153 2 T25 2
all_values[10] 1657 1 T7 2 T153 3 T25 2
all_values[11] 1674 1 T7 3 T153 1 T25 1
all_values[12] 1762 1 T2 1 T7 3 T35 1
all_values[13] 1660 1 T7 5 T153 2 T25 5
all_values[14] 1689 1 T2 1 T7 1 T35 1
all_values[15] 1714 1 T2 1 T7 5 T35 2
all_values[16] 1778 1 T7 2 T35 2 T25 3
all_values[17] 1658 1 T2 1 T7 5 T35 1
all_values[18] 1751 1 T2 1 T7 2 T35 3
all_values[19] 1837 1 T35 1 T153 1 T25 1
all_values[20] 1754 1 T7 1 T153 3 T25 3
all_values[21] 1706 1 T7 5 T35 1 T153 4
all_values[22] 1795 1 T2 1 T7 3 T35 1
all_values[23] 1773 1 T7 3 T35 1 T25 2
all_values[24] 1764 1 T7 2 T35 1 T153 1
all_values[25] 1714 1 T7 5 T35 2 T153 1
all_values[26] 1708 1 T7 1 T35 1 T153 3
all_values[27] 1735 1 T7 1 T153 4 T25 1
all_values[28] 1736 1 T7 4 T35 1 T25 5
all_values[29] 1716 1 T7 1 T35 3 T153 4
all_values[30] 1701 1 T153 1 T25 2 T40 10
all_values[31] 1758 1 T2 1 T35 1 T25 3
all_values[32] 1692 1 T2 1 T35 1 T153 1
all_values[33] 1733 1 T7 2 T35 2 T153 6
all_values[34] 1715 1 T7 1 T35 2 T153 5
all_values[35] 1709 1 T7 2 T35 1 T153 3
all_values[36] 1738 1 T35 1 T153 2 T25 7
all_values[37] 1743 1 T7 3 T35 1 T153 1
all_values[38] 1714 1 T7 2 T35 1 T153 2
all_values[39] 1697 1 T7 3 T153 1 T25 5
all_values[40] 1736 1 T2 1 T35 4 T153 4
all_values[41] 1734 1 T2 1 T7 1 T35 1
all_values[42] 1816 1 T2 2 T35 2 T153 3
all_values[43] 1724 1 T7 4 T35 2 T153 3
all_values[44] 1731 1 T7 1 T35 5 T153 2
all_values[45] 1702 1 T2 1 T7 3 T25 6
all_values[46] 1719 1 T2 1 T7 2 T35 4
all_values[47] 1716 1 T7 4 T35 2 T25 1
all_values[48] 1679 1 T7 3 T35 1 T153 1
all_values[49] 1742 1 T2 1 T7 7 T35 1
all_values[50] 1748 1 T7 2 T153 1 T25 2
all_values[51] 1701 1 T35 3 T153 1 T25 1
all_values[52] 1754 1 T2 1 T7 1 T35 1
all_values[53] 1648 1 T7 2 T35 1 T153 1
all_values[54] 1784 1 T7 4 T35 1 T153 2
all_values[55] 1772 1 T2 1 T7 5 T35 4
all_values[56] 1735 1 T7 2 T35 5 T153 1
all_values[57] 1779 1 T2 2 T7 4 T153 3
all_values[58] 1738 1 T2 1 T7 2 T153 4
all_values[59] 1757 1 T2 1 T7 1 T35 1
all_values[60] 1723 1 T2 1 T7 5 T153 1
all_values[61] 1688 1 T7 2 T35 1 T153 1
all_values[62] 1784 1 T7 5 T35 2 T153 2
all_values[63] 1715 1 T7 1 T35 3 T153 3

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