Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 495 1 T2 1 T7 6 T15 1
all_values[1] 507 1 T2 1 T7 8 T15 2
all_values[2] 494 1 T7 3 T18 1 T83 1
all_values[3] 474 1 T2 3 T7 4 T12 3
all_values[4] 466 1 T7 6 T15 2 T24 2
all_values[5] 480 1 T7 5 T12 1 T15 2
all_values[6] 495 1 T2 1 T7 4 T24 1
all_values[7] 443 1 T7 4 T18 1 T40 1
all_values[8] 483 1 T2 2 T7 5 T24 1
all_values[9] 534 1 T2 3 T7 4 T12 1
all_values[10] 412 1 T7 7 T17 1 T18 2
all_values[11] 439 1 T7 1 T12 1 T15 1
all_values[12] 469 1 T2 2 T7 2 T15 1
all_values[13] 496 1 T7 7 T12 2 T15 1
all_values[14] 430 1 T2 3 T7 3 T12 1
all_values[15] 474 1 T2 1 T7 5 T15 1
all_values[16] 484 1 T7 4 T17 1 T18 1
all_values[17] 459 1 T7 7 T24 1 T175 4
all_values[18] 485 1 T2 1 T7 8 T15 1
all_values[19] 427 1 T7 4 T40 1 T157 2
all_values[20] 428 1 T7 5 T18 1 T175 3
all_values[21] 507 1 T7 4 T15 1 T17 3
all_values[22] 478 1 T2 1 T7 4 T15 1
all_values[23] 489 1 T2 2 T7 8 T15 3

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