Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1737	1			T2	8		T7	18		T37	2
all_values[1]	1598	1			T2	10		T7	16		T40	1
all_values[2]	1665	1			T2	8		T7	15		T40	3
all_values[3]	1681	1			T2	2		T7	20		T40	1
all_values[4]	1744	1			T2	3		T7	19		T37	2
all_values[5]	1744	1			T2	7		T7	25		T40	2
all_values[6]	1699	1			T2	7		T7	24		T40	3
all_values[7]	1754	1			T2	6		T7	22		T37	2
all_values[8]	1714	1			T2	7		T7	21		T40	5
all_values[9]	1706	1			T2	3		T7	16		T40	2
all_values[10]	1709	1			T2	6		T7	15		T40	1
all_values[11]	1757	1			T2	5		T7	16		T37	1
all_values[12]	1748	1			T2	6		T7	11		T172	2
all_values[13]	1731	1			T2	6		T7	26		T37	2
all_values[14]	1730	1			T2	3		T7	17		T157	11
all_values[15]	1590	1			T2	5		T7	12		T157	8
all_values[16]	1664	1			T2	3		T7	17		T40	1
all_values[17]	1691	1			T2	4		T7	14		T40	2
all_values[18]	1719	1			T2	7		T7	18		T40	1
all_values[19]	1791	1			T2	3		T7	22		T40	1
all_values[20]	1744	1			T2	5		T7	13		T37	4
all_values[21]	1669	1			T2	5		T7	15		T37	1
all_values[22]	1850	1			T2	5		T7	21		T40	1
all_values[23]	1691	1			T2	2		T7	16		T40	1
all_values[24]	1720	1			T2	8		T7	18		T40	2
all_values[25]	1736	1			T2	5		T7	21		T40	1
all_values[26]	1738	1			T2	3		T7	21		T40	1
all_values[27]	1669	1			T2	4		T7	14		T40	1
all_values[28]	1729	1			T2	8		T7	21		T40	1
all_values[29]	1722	1			T2	4		T7	16		T40	1
all_values[30]	1719	1			T2	10		T7	14		T37	1
all_values[31]	1681	1			T2	4		T7	14		T40	2
all_values[32]	1723	1			T2	11		T7	10		T40	1
all_values[33]	1749	1			T2	4		T7	17		T40	1
all_values[34]	1740	1			T2	4		T7	16		T37	2
all_values[35]	1781	1			T2	8		T7	24		T40	3
all_values[36]	1728	1			T2	10		T7	21		T40	2
all_values[37]	1741	1			T2	3		T7	14		T40	2
all_values[38]	1741	1			T2	7		T7	15		T40	3
all_values[39]	1654	1			T2	3		T7	19		T40	4
all_values[40]	1684	1			T2	3		T7	23		T40	1
all_values[41]	1708	1			T2	3		T7	15		T40	2
all_values[42]	1723	1			T2	1		T7	15		T172	5
all_values[43]	1689	1			T2	8		T7	14		T40	2
all_values[44]	1747	1			T2	1		T7	16		T40	1
all_values[45]	1750	1			T2	5		T7	18		T172	3
all_values[46]	1631	1			T2	5		T7	17		T40	3
all_values[47]	1723	1			T2	9		T7	16		T40	1
all_values[48]	1687	1			T2	3		T7	20		T40	1
all_values[49]	1697	1			T2	9		T7	23		T40	4
all_values[50]	1637	1			T2	2		T7	16		T40	1
all_values[51]	1803	1			T2	7		T7	12		T40	1
all_values[52]	1722	1			T2	2		T7	16		T40	2
all_values[53]	1743	1			T2	4		T7	17		T40	1
all_values[54]	1679	1			T2	8		T7	15		T40	2
all_values[55]	1685	1			T2	7		T7	24		T40	2
all_values[56]	1702	1			T2	3		T7	25		T40	1
all_values[57]	1764	1			T2	8		T7	16		T40	5
all_values[58]	1744	1			T2	6		T7	16		T40	1
all_values[59]	1711	1			T2	7		T7	10		T40	2
all_values[60]	1779	1			T2	6		T7	18		T40	3
all_values[61]	1802	1			T2	4		T7	19		T37	1
all_values[62]	1759	1			T2	8		T7	25		T37	1
all_values[63]	1769	1			T2	5		T7	18		T40	2