Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 469 1 T1 1 T9 2 T29 4
all_values[1] 514 1 T9 1 T26 1 T29 2
all_values[2] 507 1 T1 1 T8 1 T9 1
all_values[3] 501 1 T8 2 T9 1 T29 1
all_values[4] 521 1 T1 2 T8 4 T29 4
all_values[5] 484 1 T1 1 T8 5 T9 1
all_values[6] 518 1 T8 3 T9 1 T29 4
all_values[7] 505 1 T1 1 T8 2 T29 7
all_values[8] 543 1 T1 1 T8 6 T26 1
all_values[9] 478 1 T8 3 T29 2 T18 1
all_values[10] 481 1 T1 1 T8 3 T29 8
all_values[11] 520 1 T8 6 T29 7 T18 1
all_values[12] 467 1 T8 2 T29 3 T20 2
all_values[13] 497 1 T8 5 T9 1 T29 5
all_values[14] 511 1 T1 3 T8 1 T9 1
all_values[15] 511 1 T8 5 T29 2 T18 1
all_values[16] 494 1 T1 3 T8 4 T29 3
all_values[17] 503 1 T1 1 T8 5 T29 4
all_values[18] 451 1 T8 1 T18 1 T20 1
all_values[19] 535 1 T1 1 T8 3 T9 1
all_values[20] 503 1 T1 1 T8 4 T29 6
all_values[21] 512 1 T8 1 T9 1 T29 10
all_values[22] 487 1 T1 1 T29 5 T4 1
all_values[23] 495 1 T8 4 T9 2 T29 4

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