Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1719	1			T3	3		T8	24		T29	22
all_values[1]	1629	1			T3	2		T8	15		T29	18
all_values[2]	1650	1			T3	1		T8	20		T29	18
all_values[3]	1654	1			T3	4		T8	17		T29	26
all_values[4]	1626	1			T3	1		T8	14		T29	16
all_values[5]	1684	1			T3	1		T8	14		T29	15
all_values[6]	1684	1			T3	2		T8	20		T29	12
all_values[7]	1616	1			T8	19		T29	16		T20	1
all_values[8]	1644	1			T3	1		T8	25		T29	24
all_values[9]	1667	1			T3	3		T8	20		T29	25
all_values[10]	1654	1			T3	1		T8	18		T29	19
all_values[11]	1713	1			T8	21		T29	22		T17	2
all_values[12]	1657	1			T3	3		T8	15		T29	19
all_values[13]	1687	1			T3	1		T8	18		T29	21
all_values[14]	1632	1			T3	1		T8	21		T29	10
all_values[15]	1669	1			T3	1		T8	19		T29	22
all_values[16]	1703	1			T3	1		T8	23		T29	22
all_values[17]	1659	1			T3	1		T8	19		T29	12
all_values[18]	1706	1			T3	5		T8	14		T29	20
all_values[19]	1668	1			T3	6		T8	15		T29	19
all_values[20]	1647	1			T3	2		T8	15		T29	20
all_values[21]	1646	1			T3	2		T8	24		T29	20
all_values[22]	1675	1			T3	1		T8	24		T29	21
all_values[23]	1646	1			T3	1		T8	21		T29	21
all_values[24]	1630	1			T3	2		T8	18		T29	28
all_values[25]	1689	1			T3	2		T8	13		T29	28
all_values[26]	1688	1			T3	8		T8	15		T29	24
all_values[27]	1646	1			T3	6		T8	11		T29	22
all_values[28]	1742	1			T3	3		T8	17		T29	27
all_values[29]	1690	1			T3	3		T8	30		T29	21
all_values[30]	1664	1			T3	2		T8	17		T29	11
all_values[31]	1729	1			T3	2		T8	29		T29	20
all_values[32]	1690	1			T8	13		T29	18		T17	4
all_values[33]	1663	1			T3	2		T8	14		T29	23
all_values[34]	1691	1			T3	3		T8	14		T29	19
all_values[35]	1653	1			T3	8		T8	17		T29	18
all_values[36]	1744	1			T3	4		T8	17		T29	21
all_values[37]	1655	1			T3	2		T8	24		T29	20
all_values[38]	1662	1			T3	3		T8	21		T29	21
all_values[39]	1727	1			T3	4		T8	16		T29	26
all_values[40]	1692	1			T3	3		T8	16		T29	24
all_values[41]	1723	1			T3	4		T8	18		T29	19
all_values[42]	1664	1			T3	4		T8	13		T29	19
all_values[43]	1714	1			T3	2		T8	17		T29	32
all_values[44]	1679	1			T3	3		T8	18		T29	23
all_values[45]	1687	1			T3	7		T8	14		T29	23
all_values[46]	1654	1			T3	1		T8	16		T29	24
all_values[47]	1566	1			T3	6		T8	22		T29	14
all_values[48]	1652	1			T3	2		T8	23		T29	16
all_values[49]	1697	1			T3	2		T8	22		T29	18
all_values[50]	1685	1			T3	7		T8	14		T29	19
all_values[51]	1673	1			T3	2		T8	16		T29	19
all_values[52]	1617	1			T3	4		T8	17		T29	18
all_values[53]	1685	1			T3	2		T8	24		T29	23
all_values[54]	1634	1			T3	5		T8	20		T29	17
all_values[55]	1716	1			T3	2		T8	12		T29	14
all_values[56]	1705	1			T3	2		T8	18		T29	22
all_values[57]	1676	1			T3	2		T8	17		T29	16
all_values[58]	1668	1			T3	5		T8	15		T29	16
all_values[59]	1626	1			T3	4		T8	12		T29	16
all_values[60]	1615	1			T3	2		T8	13		T29	22
all_values[61]	1700	1			T3	4		T8	13		T29	20
all_values[62]	1674	1			T8	16		T29	20		T17	2
all_values[63]	1649	1			T8	17		T29	19		T17	3