Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1877	1			T33	20		T19	2		T20	29
all_values[1]	1901	1			T33	19		T19	5		T20	34
all_values[2]	1918	1			T33	15		T20	25		T21	7
all_values[3]	1895	1			T33	14		T19	3		T20	26
all_values[4]	1867	1			T33	16		T20	22		T21	5
all_values[5]	1850	1			T33	19		T19	3		T20	28
all_values[6]	1907	1			T33	19		T19	1		T20	31
all_values[7]	1876	1			T33	19		T19	2		T20	37
all_values[8]	1888	1			T33	10		T19	4		T20	34
all_values[9]	1887	1			T33	18		T19	1		T20	25
all_values[10]	1940	1			T33	16		T19	3		T20	32
all_values[11]	1867	1			T33	19		T19	3		T20	26
all_values[12]	1861	1			T33	12		T19	4		T20	19
all_values[13]	1843	1			T33	14		T19	3		T20	38
all_values[14]	1876	1			T33	17		T19	4		T20	23
all_values[15]	1917	1			T33	11		T19	4		T20	29
all_values[16]	1840	1			T33	13		T19	3		T20	42
all_values[17]	1930	1			T33	10		T19	1		T20	22
all_values[18]	1903	1			T33	11		T19	2		T20	37
all_values[19]	1861	1			T33	13		T19	2		T20	24
all_values[20]	1840	1			T33	15		T19	2		T20	26
all_values[21]	1848	1			T33	10		T19	2		T20	34
all_values[22]	1859	1			T33	21		T19	5		T20	30
all_values[23]	1852	1			T33	20		T19	3		T20	28
all_values[24]	1892	1			T33	15		T19	1		T20	24
all_values[25]	1832	1			T33	14		T20	31		T21	5
all_values[26]	1860	1			T33	19		T19	3		T20	34
all_values[27]	1904	1			T33	12		T19	6		T20	28
all_values[28]	1900	1			T33	13		T19	4		T20	37
all_values[29]	1882	1			T33	18		T19	1		T20	19
all_values[30]	1881	1			T33	17		T19	2		T20	22
all_values[31]	1852	1			T33	16		T19	1		T20	27
all_values[32]	1838	1			T33	16		T19	3		T20	29
all_values[33]	1914	1			T33	15		T19	3		T20	35
all_values[34]	1889	1			T33	12		T19	6		T20	33
all_values[35]	1890	1			T33	18		T19	2		T20	34
all_values[36]	1932	1			T33	16		T19	4		T20	23
all_values[37]	1859	1			T33	13		T19	1		T20	22
all_values[38]	1911	1			T33	10		T19	3		T20	36
all_values[39]	1873	1			T33	10		T19	2		T20	22
all_values[40]	1874	1			T33	14		T19	4		T20	34
all_values[41]	1769	1			T33	15		T19	1		T20	25
all_values[42]	1799	1			T33	9		T19	5		T20	28
all_values[43]	1866	1			T33	19		T19	4		T20	29
all_values[44]	1934	1			T33	21		T19	4		T20	29
all_values[45]	1871	1			T33	15		T19	3		T20	30
all_values[46]	1942	1			T33	17		T19	4		T20	31
all_values[47]	1815	1			T33	12		T19	6		T20	24
all_values[48]	1827	1			T33	14		T20	22		T21	10
all_values[49]	1898	1			T33	18		T19	5		T20	28
all_values[50]	1917	1			T33	14		T19	2		T20	27
all_values[51]	1843	1			T33	16		T19	5		T20	28
all_values[52]	1829	1			T33	13		T19	3		T20	30
all_values[53]	1815	1			T33	15		T19	3		T20	22
all_values[54]	1869	1			T33	14		T19	1		T20	26
all_values[55]	1884	1			T33	18		T19	3		T20	31
all_values[56]	1871	1			T33	20		T19	1		T20	24
all_values[57]	1891	1			T33	16		T20	35		T21	10
all_values[58]	1820	1			T33	12		T19	5		T20	27
all_values[59]	1869	1			T33	9		T19	1		T20	28
all_values[60]	1928	1			T33	13		T19	2		T20	24
all_values[61]	1841	1			T33	16		T19	1		T20	29
all_values[62]	1868	1			T33	19		T19	4		T20	35
all_values[63]	1834	1			T33	12		T19	4		T20	42