Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1610	1			T7	17		T6	12		T12	4
all_values[1]	1770	1			T7	25		T6	20		T12	2
all_values[2]	1683	1			T7	17		T6	15		T8	1
all_values[3]	1697	1			T7	22		T6	9		T8	2
all_values[4]	1720	1			T7	19		T6	20		T8	2
all_values[5]	1630	1			T7	18		T6	22		T12	1
all_values[6]	1673	1			T7	21		T6	21		T8	1
all_values[7]	1722	1			T7	17		T6	10		T12	1
all_values[8]	1684	1			T7	20		T6	12		T12	1
all_values[9]	1731	1			T7	20		T6	13		T12	1
all_values[10]	1707	1			T7	25		T6	18		T12	2
all_values[11]	1750	1			T7	22		T6	13		T12	2
all_values[12]	1680	1			T7	16		T6	21		T8	1
all_values[13]	1725	1			T7	20		T6	19		T8	1
all_values[14]	1637	1			T7	22		T6	13		T15	1
all_values[15]	1655	1			T7	20		T6	13		T12	2
all_values[16]	1687	1			T7	17		T6	13		T12	5
all_values[17]	1645	1			T7	21		T6	22		T15	2
all_values[18]	1759	1			T7	17		T6	13		T8	1
all_values[19]	1683	1			T7	16		T6	17		T12	2
all_values[20]	1653	1			T7	24		T6	14		T8	1
all_values[21]	1683	1			T7	16		T6	17		T8	1
all_values[22]	1708	1			T7	21		T6	15		T8	1
all_values[23]	1725	1			T7	26		T6	15		T8	2
all_values[24]	1664	1			T7	16		T6	12		T15	1
all_values[25]	1615	1			T7	16		T6	16		T8	1
all_values[26]	1699	1			T7	20		T6	22		T8	3
all_values[27]	1725	1			T7	18		T6	9		T8	1
all_values[28]	1674	1			T7	16		T6	20		T12	1
all_values[29]	1677	1			T7	24		T6	13		T8	1
all_values[30]	1723	1			T7	24		T6	19		T15	1
all_values[31]	1689	1			T7	15		T6	18		T12	1
all_values[32]	1664	1			T7	19		T6	16		T8	4
all_values[33]	1740	1			T7	17		T6	17		T12	2
all_values[34]	1670	1			T7	17		T6	20		T12	4
all_values[35]	1699	1			T7	13		T6	17		T16	5
all_values[36]	1590	1			T7	16		T6	12		T8	1
all_values[37]	1594	1			T7	14		T6	14		T8	2
all_values[38]	1713	1			T7	16		T6	14		T12	1
all_values[39]	1736	1			T7	17		T6	13		T12	2
all_values[40]	1652	1			T7	23		T6	13		T8	1
all_values[41]	1709	1			T7	20		T6	18		T8	1
all_values[42]	1597	1			T7	18		T6	13		T12	4
all_values[43]	1738	1			T7	18		T6	14		T8	1
all_values[44]	1748	1			T7	16		T6	9		T12	2
all_values[45]	1678	1			T7	20		T6	16		T12	2
all_values[46]	1661	1			T7	15		T6	21		T12	4
all_values[47]	1748	1			T7	23		T6	17		T12	3
all_values[48]	1709	1			T7	22		T6	15		T8	2
all_values[49]	1686	1			T7	15		T6	13		T8	2
all_values[50]	1679	1			T7	20		T6	23		T8	2
all_values[51]	1692	1			T7	19		T6	18		T8	2
all_values[52]	1649	1			T7	19		T6	17		T12	1
all_values[53]	1714	1			T7	15		T6	16		T8	2
all_values[54]	1661	1			T7	18		T6	20		T8	1
all_values[55]	1669	1			T7	23		T6	9		T8	1
all_values[56]	1668	1			T7	17		T6	15		T12	2
all_values[57]	1753	1			T7	20		T6	17		T8	1
all_values[58]	1673	1			T7	20		T6	22		T12	4
all_values[59]	1628	1			T7	23		T6	18		T8	4
all_values[60]	1686	1			T7	17		T6	23		T8	2
all_values[61]	1634	1			T7	16		T6	13		T8	3
all_values[62]	1686	1			T7	19		T6	18		T12	1
all_values[63]	1640	1			T7	15		T6	11		T16	1