Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1666	1			T3	2		T7	1		T8	1
all_values[1]	1596	1			T3	2		T7	3		T18	1
all_values[2]	1728	1			T3	4		T7	3		T8	1
all_values[3]	1651	1			T3	2		T7	2		T18	2
all_values[4]	1692	1			T7	2		T8	1		T18	2
all_values[5]	1630	1			T3	5		T7	1		T8	1
all_values[6]	1728	1			T3	2		T7	5		T18	3
all_values[7]	1677	1			T3	2		T7	3		T8	1
all_values[8]	1639	1			T3	4		T18	2		T4	6
all_values[9]	1623	1			T3	2		T7	1		T8	1
all_values[10]	1653	1			T3	2		T7	1		T18	2
all_values[11]	1616	1			T3	1		T7	2		T18	3
all_values[12]	1654	1			T3	2		T18	1		T38	11
all_values[13]	1659	1			T3	2		T7	3		T18	2
all_values[14]	1733	1			T3	4		T7	2		T18	3
all_values[15]	1640	1			T3	4		T8	1		T18	2
all_values[16]	1629	1			T3	2		T7	3		T8	1
all_values[17]	1667	1			T3	2		T7	2		T8	1
all_values[18]	1676	1			T7	3		T8	3		T18	3
all_values[19]	1671	1			T3	3		T7	2		T8	1
all_values[20]	1635	1			T3	4		T7	2		T18	3
all_values[21]	1697	1			T3	1		T7	1		T18	2
all_values[22]	1641	1			T3	2		T7	2		T18	2
all_values[23]	1664	1			T3	2		T7	3		T18	2
all_values[24]	1660	1			T7	2		T18	2		T4	6
all_values[25]	1689	1			T3	3		T7	1		T18	3
all_values[26]	1719	1			T3	2		T4	8		T38	18
all_values[27]	1732	1			T3	1		T7	2		T8	1
all_values[28]	1692	1			T3	3		T7	2		T8	1
all_values[29]	1665	1			T3	3		T7	4		T8	1
all_values[30]	1647	1			T3	1		T7	5		T8	1
all_values[31]	1595	1			T3	5		T7	3		T18	1
all_values[32]	1674	1			T3	3		T7	7		T18	3
all_values[33]	1650	1			T3	3		T7	3		T18	1
all_values[34]	1723	1			T3	2		T7	3		T18	1
all_values[35]	1656	1			T7	3		T18	2		T4	6
all_values[36]	1661	1			T3	1		T7	1		T18	2
all_values[37]	1742	1			T3	6		T7	3		T18	1
all_values[38]	1624	1			T3	1		T7	4		T18	1
all_values[39]	1625	1			T3	3		T7	2		T18	1
all_values[40]	1707	1			T3	2		T7	3		T8	1
all_values[41]	1607	1			T7	3		T18	2		T4	5
all_values[42]	1599	1			T7	4		T4	10		T38	8
all_values[43]	1632	1			T3	1		T7	3		T18	2
all_values[44]	1684	1			T3	4		T7	1		T8	2
all_values[45]	1614	1			T3	2		T7	2		T8	1
all_values[46]	1658	1			T3	3		T7	4		T18	1
all_values[47]	1654	1			T3	1		T7	4		T8	1
all_values[48]	1721	1			T3	1		T7	4		T8	1
all_values[49]	1615	1			T3	1		T7	3		T4	11
all_values[50]	1675	1			T3	3		T7	2		T18	3
all_values[51]	1601	1			T3	4		T7	3		T8	1
all_values[52]	1646	1			T3	1		T7	2		T8	1
all_values[53]	1658	1			T3	1		T7	6		T8	2
all_values[54]	1631	1			T7	1		T18	2		T4	9
all_values[55]	1682	1			T3	3		T7	3		T8	1
all_values[56]	1692	1			T3	4		T7	4		T8	1
all_values[57]	1612	1			T3	2		T7	3		T8	2
all_values[58]	1679	1			T3	3		T7	3		T18	1
all_values[59]	1633	1			T7	4		T18	1		T4	9
all_values[60]	1691	1			T3	3		T7	3		T18	2
all_values[61]	1634	1			T3	3		T7	4		T8	1
all_values[62]	1676	1			T3	1		T7	3		T18	2
all_values[63]	1682	1			T3	1		T7	4		T18	4