Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 503 1 T8 15 T11 1 T18 1
all_values[1] 467 1 T8 9 T9 2 T11 2
all_values[2] 472 1 T8 11 T9 2 T19 3
all_values[3] 469 1 T8 13 T18 1 T20 6
all_values[4] 471 1 T8 6 T20 8 T131 2
all_values[5] 443 1 T8 11 T9 2 T19 1
all_values[6] 446 1 T8 12 T18 1 T20 10
all_values[7] 473 1 T4 1 T8 8 T9 1
all_values[8] 428 1 T8 10 T9 1 T19 1
all_values[9] 449 1 T8 8 T9 2 T18 1
all_values[10] 477 1 T8 7 T9 2 T18 1
all_values[11] 466 1 T8 10 T9 3 T19 1
all_values[12] 469 1 T8 16 T18 1 T19 3
all_values[13] 445 1 T8 6 T11 2 T18 4
all_values[14] 505 1 T8 12 T9 3 T18 1
all_values[15] 484 1 T8 13 T11 2 T18 3
all_values[16] 449 1 T8 14 T9 4 T19 1
all_values[17] 481 1 T4 1 T8 8 T9 1
all_values[18] 466 1 T8 8 T9 1 T18 1
all_values[19] 481 1 T8 9 T11 1 T18 1
all_values[20] 463 1 T8 7 T9 2 T11 1
all_values[21] 490 1 T8 12 T9 1 T11 1
all_values[22] 476 1 T8 10 T9 1 T11 1
all_values[23] 455 1 T8 7 T11 1 T18 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%