Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1778	1			T2	2		T8	32		T9	4
all_values[1]	1728	1			T2	2		T8	43		T9	4
all_values[2]	1718	1			T2	4		T8	28		T9	1
all_values[3]	1660	1			T2	1		T8	36		T9	3
all_values[4]	1687	1			T2	5		T8	36		T9	3
all_values[5]	1660	1			T2	1		T8	45		T9	4
all_values[6]	1670	1			T2	4		T8	44		T18	2
all_values[7]	1704	1			T8	42		T9	3		T18	1
all_values[8]	1741	1			T8	58		T9	1		T16	2
all_values[9]	1687	1			T2	1		T8	42		T9	3
all_values[10]	1665	1			T2	2		T8	37		T9	2
all_values[11]	1745	1			T8	33		T9	2		T18	3
all_values[12]	1674	1			T2	1		T8	41		T9	2
all_values[13]	1725	1			T2	1		T8	42		T9	5
all_values[14]	1738	1			T2	2		T8	41		T9	5
all_values[15]	1728	1			T2	1		T8	47		T9	2
all_values[16]	1679	1			T2	1		T8	27		T9	2
all_values[17]	1657	1			T2	2		T8	36		T9	6
all_values[18]	1698	1			T2	1		T8	49		T9	2
all_values[19]	1711	1			T2	3		T8	28		T18	4
all_values[20]	1701	1			T2	1		T8	39		T9	2
all_values[21]	1666	1			T2	2		T8	39		T9	2
all_values[22]	1707	1			T2	2		T8	41		T9	2
all_values[23]	1624	1			T8	50		T9	4		T18	1
all_values[24]	1703	1			T2	1		T8	39		T9	2
all_values[25]	1661	1			T2	4		T8	35		T9	2
all_values[26]	1644	1			T2	3		T8	40		T9	4
all_values[27]	1642	1			T2	1		T8	44		T16	1
all_values[28]	1713	1			T8	32		T9	2		T16	2
all_values[29]	1687	1			T2	1		T8	38		T9	2
all_values[30]	1691	1			T2	1		T8	48		T9	3
all_values[31]	1715	1			T2	1		T8	41		T9	3
all_values[32]	1648	1			T2	1		T8	37		T9	3
all_values[33]	1755	1			T2	1		T8	46		T9	2
all_values[34]	1658	1			T2	4		T8	32		T9	4
all_values[35]	1735	1			T2	1		T8	40		T9	3
all_values[36]	1713	1			T2	1		T8	48		T9	4
all_values[37]	1702	1			T2	2		T8	34		T9	5
all_values[38]	1775	1			T2	1		T8	54		T9	2
all_values[39]	1700	1			T2	1		T8	36		T9	3
all_values[40]	1613	1			T2	2		T8	35		T9	2
all_values[41]	1686	1			T2	3		T8	34		T16	1
all_values[42]	1660	1			T2	4		T8	50		T9	2
all_values[43]	1694	1			T8	36		T9	1		T16	1
all_values[44]	1748	1			T2	1		T8	39		T9	2
all_values[45]	1706	1			T8	51		T9	4		T16	1
all_values[46]	1697	1			T2	2		T8	53		T9	3
all_values[47]	1655	1			T8	39		T9	2		T18	2
all_values[48]	1779	1			T2	1		T8	51		T9	3
all_values[49]	1720	1			T2	2		T8	40		T9	2
all_values[50]	1721	1			T2	3		T8	46		T9	5
all_values[51]	1687	1			T2	4		T8	33		T9	8
all_values[52]	1736	1			T2	1		T8	48		T9	3
all_values[53]	1733	1			T8	36		T9	2		T16	2
all_values[54]	1687	1			T2	1		T8	42		T9	2
all_values[55]	1668	1			T2	4		T8	34		T9	3
all_values[56]	1762	1			T2	2		T8	41		T16	1
all_values[57]	1750	1			T2	1		T8	46		T9	3
all_values[58]	1665	1			T2	1		T8	38		T9	1
all_values[59]	1633	1			T2	1		T8	47		T9	3
all_values[60]	1659	1			T8	47		T9	4		T18	2
all_values[61]	1747	1			T2	2		T8	35		T9	8
all_values[62]	1666	1			T2	3		T8	32		T9	4
all_values[63]	1654	1			T2	1		T8	40		T9	4