Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.92 98.80 95.88 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T763 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.761202267 Jun 24 04:55:44 PM PDT 24 Jun 24 04:55:58 PM PDT 24 205076591 ps
T764 /workspace/coverage/xbar_build_mode/48.xbar_same_source.3674199633 Jun 24 04:56:11 PM PDT 24 Jun 24 04:56:34 PM PDT 24 4438719357 ps
T765 /workspace/coverage/xbar_build_mode/20.xbar_random.2788171409 Jun 24 04:54:34 PM PDT 24 Jun 24 04:55:02 PM PDT 24 196561799 ps
T766 /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2322028776 Jun 24 04:54:18 PM PDT 24 Jun 24 04:54:48 PM PDT 24 226448309 ps
T767 /workspace/coverage/xbar_build_mode/19.xbar_smoke.2288654248 Jun 24 04:54:34 PM PDT 24 Jun 24 04:54:41 PM PDT 24 137146750 ps
T768 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.354193097 Jun 24 04:54:29 PM PDT 24 Jun 24 04:54:47 PM PDT 24 861224047 ps
T769 /workspace/coverage/xbar_build_mode/36.xbar_random.3732440782 Jun 24 04:55:33 PM PDT 24 Jun 24 04:56:17 PM PDT 24 3204760411 ps
T770 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.542797785 Jun 24 04:56:01 PM PDT 24 Jun 24 04:59:58 PM PDT 24 30714138224 ps
T233 /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2056060369 Jun 24 04:55:45 PM PDT 24 Jun 24 04:58:07 PM PDT 24 48862202948 ps
T184 /workspace/coverage/xbar_build_mode/44.xbar_random.2192454624 Jun 24 04:55:58 PM PDT 24 Jun 24 04:56:27 PM PDT 24 3568509486 ps
T771 /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.217272891 Jun 24 04:55:57 PM PDT 24 Jun 24 04:56:14 PM PDT 24 262085295 ps
T772 /workspace/coverage/xbar_build_mode/28.xbar_smoke.4288783784 Jun 24 04:55:03 PM PDT 24 Jun 24 04:55:10 PM PDT 24 148455802 ps
T773 /workspace/coverage/xbar_build_mode/49.xbar_smoke.2590040876 Jun 24 04:56:11 PM PDT 24 Jun 24 04:56:17 PM PDT 24 155003158 ps
T774 /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1942129069 Jun 24 04:54:36 PM PDT 24 Jun 24 04:58:28 PM PDT 24 37868932457 ps
T775 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.89268589 Jun 24 04:55:36 PM PDT 24 Jun 24 04:57:12 PM PDT 24 265556967 ps
T776 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.289973565 Jun 24 04:55:58 PM PDT 24 Jun 24 04:57:45 PM PDT 24 252764729 ps
T777 /workspace/coverage/xbar_build_mode/15.xbar_smoke.68152816 Jun 24 04:54:25 PM PDT 24 Jun 24 04:54:31 PM PDT 24 69289982 ps
T146 /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.903852687 Jun 24 04:54:28 PM PDT 24 Jun 24 04:54:41 PM PDT 24 412559411 ps
T778 /workspace/coverage/xbar_build_mode/45.xbar_error_random.3292989059 Jun 24 04:55:57 PM PDT 24 Jun 24 04:56:28 PM PDT 24 1333373202 ps
T779 /workspace/coverage/xbar_build_mode/0.xbar_random.4183239201 Jun 24 04:53:47 PM PDT 24 Jun 24 04:54:05 PM PDT 24 337964260 ps
T780 /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1965281119 Jun 24 04:56:18 PM PDT 24 Jun 24 04:58:07 PM PDT 24 25416588699 ps
T781 /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3867803414 Jun 24 04:54:28 PM PDT 24 Jun 24 04:55:09 PM PDT 24 7725466380 ps
T782 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3303071666 Jun 24 04:55:12 PM PDT 24 Jun 24 04:55:19 PM PDT 24 127431038 ps
T783 /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2124523458 Jun 24 04:55:51 PM PDT 24 Jun 24 04:56:00 PM PDT 24 420920955 ps
T784 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2853470206 Jun 24 04:56:07 PM PDT 24 Jun 24 04:56:38 PM PDT 24 5785402282 ps
T785 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.85294808 Jun 24 04:55:45 PM PDT 24 Jun 24 04:56:17 PM PDT 24 6720827175 ps
T786 /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1889754661 Jun 24 04:54:11 PM PDT 24 Jun 24 04:55:40 PM PDT 24 9965526974 ps
T787 /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.25500590 Jun 24 04:54:48 PM PDT 24 Jun 24 04:55:17 PM PDT 24 226110025 ps
T788 /workspace/coverage/xbar_build_mode/25.xbar_error_random.1856498633 Jun 24 04:54:56 PM PDT 24 Jun 24 04:55:16 PM PDT 24 804422790 ps
T789 /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.719405112 Jun 24 04:55:14 PM PDT 24 Jun 24 04:55:38 PM PDT 24 274083211 ps
T790 /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.193641408 Jun 24 04:54:36 PM PDT 24 Jun 24 04:55:03 PM PDT 24 12201101213 ps
T791 /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3976040109 Jun 24 04:54:51 PM PDT 24 Jun 24 04:58:09 PM PDT 24 7271188057 ps
T792 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1997100912 Jun 24 04:55:55 PM PDT 24 Jun 24 04:56:18 PM PDT 24 2406471701 ps
T793 /workspace/coverage/xbar_build_mode/1.xbar_random.367403603 Jun 24 04:53:53 PM PDT 24 Jun 24 04:54:02 PM PDT 24 157186546 ps
T794 /workspace/coverage/xbar_build_mode/21.xbar_random.58212086 Jun 24 04:54:49 PM PDT 24 Jun 24 04:55:17 PM PDT 24 122320412 ps
T795 /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3779310 Jun 24 04:54:53 PM PDT 24 Jun 24 04:55:31 PM PDT 24 5916931161 ps
T796 /workspace/coverage/xbar_build_mode/16.xbar_error_random.27866524 Jun 24 04:54:25 PM PDT 24 Jun 24 04:54:40 PM PDT 24 1084583423 ps
T797 /workspace/coverage/xbar_build_mode/35.xbar_stress_all.94447595 Jun 24 04:55:34 PM PDT 24 Jun 24 04:57:28 PM PDT 24 6141835615 ps
T798 /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4263714792 Jun 24 04:56:08 PM PDT 24 Jun 24 04:56:13 PM PDT 24 67659075 ps
T799 /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1748060339 Jun 24 04:54:51 PM PDT 24 Jun 24 04:58:42 PM PDT 24 49103940940 ps
T800 /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3921015412 Jun 24 04:55:50 PM PDT 24 Jun 24 04:56:31 PM PDT 24 9280614184 ps
T801 /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2436983544 Jun 24 04:53:51 PM PDT 24 Jun 24 04:54:09 PM PDT 24 184290028 ps
T802 /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2636887695 Jun 24 04:55:10 PM PDT 24 Jun 24 04:59:46 PM PDT 24 100791421870 ps
T803 /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.4237679967 Jun 24 04:55:32 PM PDT 24 Jun 24 04:59:22 PM PDT 24 38759961255 ps
T804 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.273465418 Jun 24 04:53:59 PM PDT 24 Jun 24 04:55:12 PM PDT 24 834613169 ps
T805 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1735788475 Jun 24 04:53:48 PM PDT 24 Jun 24 04:58:44 PM PDT 24 58998090439 ps
T147 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3197638926 Jun 24 04:55:50 PM PDT 24 Jun 24 04:56:39 PM PDT 24 7187442726 ps
T806 /workspace/coverage/xbar_build_mode/22.xbar_error_random.3571921169 Jun 24 04:54:44 PM PDT 24 Jun 24 04:54:57 PM PDT 24 73423356 ps
T135 /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1469024850 Jun 24 04:56:14 PM PDT 24 Jun 24 05:01:42 PM PDT 24 50893819742 ps
T807 /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2125081045 Jun 24 04:54:09 PM PDT 24 Jun 24 04:55:16 PM PDT 24 11394671507 ps
T808 /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1650018559 Jun 24 04:56:17 PM PDT 24 Jun 24 04:56:35 PM PDT 24 107535797 ps
T809 /workspace/coverage/xbar_build_mode/38.xbar_stress_all.612726093 Jun 24 04:55:36 PM PDT 24 Jun 24 04:59:55 PM PDT 24 36281419663 ps
T810 /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2765583171 Jun 24 04:55:34 PM PDT 24 Jun 24 04:56:14 PM PDT 24 8652124780 ps
T175 /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4119635979 Jun 24 04:53:46 PM PDT 24 Jun 24 04:56:53 PM PDT 24 37084306597 ps
T811 /workspace/coverage/xbar_build_mode/24.xbar_error_random.3445699612 Jun 24 04:54:53 PM PDT 24 Jun 24 04:55:03 PM PDT 24 229161113 ps
T812 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.362043729 Jun 24 04:54:38 PM PDT 24 Jun 24 05:01:01 PM PDT 24 4832735854 ps
T813 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3938784367 Jun 24 04:54:31 PM PDT 24 Jun 24 04:56:17 PM PDT 24 10683597542 ps
T814 /workspace/coverage/xbar_build_mode/28.xbar_random.2776264252 Jun 24 04:55:04 PM PDT 24 Jun 24 04:55:10 PM PDT 24 89130839 ps
T815 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1125846313 Jun 24 04:56:15 PM PDT 24 Jun 24 05:02:07 PM PDT 24 2439039382 ps
T816 /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1683995243 Jun 24 04:56:00 PM PDT 24 Jun 24 04:57:36 PM PDT 24 776023862 ps
T817 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2888352817 Jun 24 04:56:09 PM PDT 24 Jun 24 05:02:18 PM PDT 24 5729865971 ps
T818 /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.807006228 Jun 24 04:54:07 PM PDT 24 Jun 24 04:55:58 PM PDT 24 14697216849 ps
T819 /workspace/coverage/xbar_build_mode/29.xbar_stress_all.547829534 Jun 24 04:55:13 PM PDT 24 Jun 24 04:59:00 PM PDT 24 7888469518 ps
T820 /workspace/coverage/xbar_build_mode/19.xbar_random.485433889 Jun 24 04:54:44 PM PDT 24 Jun 24 04:55:12 PM PDT 24 655872351 ps
T821 /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1507956267 Jun 24 04:54:43 PM PDT 24 Jun 24 04:55:07 PM PDT 24 92109503 ps
T228 /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1597541097 Jun 24 04:54:34 PM PDT 24 Jun 24 04:57:25 PM PDT 24 46616595969 ps
T822 /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.272738348 Jun 24 04:54:37 PM PDT 24 Jun 24 04:54:42 PM PDT 24 42956729 ps
T823 /workspace/coverage/xbar_build_mode/19.xbar_same_source.513601528 Jun 24 04:54:46 PM PDT 24 Jun 24 04:55:22 PM PDT 24 1259337873 ps
T824 /workspace/coverage/xbar_build_mode/13.xbar_error_random.370475219 Jun 24 04:54:31 PM PDT 24 Jun 24 04:54:37 PM PDT 24 15816126 ps
T825 /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1656262766 Jun 24 04:55:19 PM PDT 24 Jun 24 04:55:49 PM PDT 24 3218357758 ps
T826 /workspace/coverage/xbar_build_mode/32.xbar_random.2431178807 Jun 24 04:55:15 PM PDT 24 Jun 24 04:55:24 PM PDT 24 340532755 ps
T827 /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3631945518 Jun 24 04:54:13 PM PDT 24 Jun 24 04:54:20 PM PDT 24 25654755 ps
T828 /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2096825819 Jun 24 04:54:43 PM PDT 24 Jun 24 04:55:10 PM PDT 24 140754918 ps
T829 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2101575795 Jun 24 04:56:08 PM PDT 24 Jun 24 04:56:18 PM PDT 24 59279771 ps
T830 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2776753003 Jun 24 04:55:01 PM PDT 24 Jun 24 04:56:06 PM PDT 24 1476319069 ps
T831 /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3379624259 Jun 24 04:54:08 PM PDT 24 Jun 24 04:54:15 PM PDT 24 29454335 ps
T832 /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2589618322 Jun 24 04:55:38 PM PDT 24 Jun 24 04:55:56 PM PDT 24 288325807 ps
T833 /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.435071626 Jun 24 04:55:55 PM PDT 24 Jun 24 04:56:19 PM PDT 24 225785967 ps
T834 /workspace/coverage/xbar_build_mode/26.xbar_error_random.3043167118 Jun 24 04:55:13 PM PDT 24 Jun 24 04:55:27 PM PDT 24 1019348217 ps
T224 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3486367250 Jun 24 04:54:35 PM PDT 24 Jun 24 05:01:18 PM PDT 24 52942821219 ps
T835 /workspace/coverage/xbar_build_mode/46.xbar_smoke.2701580593 Jun 24 04:56:00 PM PDT 24 Jun 24 04:56:07 PM PDT 24 363187275 ps
T836 /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2932379469 Jun 24 04:55:00 PM PDT 24 Jun 24 04:55:34 PM PDT 24 993835766 ps
T837 /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2607236379 Jun 24 04:53:53 PM PDT 24 Jun 24 04:54:00 PM PDT 24 38821512 ps
T838 /workspace/coverage/xbar_build_mode/9.xbar_smoke.19334419 Jun 24 04:54:14 PM PDT 24 Jun 24 04:54:22 PM PDT 24 145721115 ps
T839 /workspace/coverage/xbar_build_mode/48.xbar_random.139260447 Jun 24 04:56:11 PM PDT 24 Jun 24 04:56:22 PM PDT 24 76991929 ps
T840 /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2043215140 Jun 24 04:54:27 PM PDT 24 Jun 24 04:55:01 PM PDT 24 3890615942 ps
T841 /workspace/coverage/xbar_build_mode/16.xbar_smoke.2883344536 Jun 24 04:54:42 PM PDT 24 Jun 24 04:54:52 PM PDT 24 147063100 ps
T842 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.349083434 Jun 24 04:54:39 PM PDT 24 Jun 24 04:58:20 PM PDT 24 591879808 ps
T843 /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1153914156 Jun 24 04:54:19 PM PDT 24 Jun 24 04:57:32 PM PDT 24 35824268436 ps
T844 /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3275272289 Jun 24 04:54:44 PM PDT 24 Jun 24 04:55:26 PM PDT 24 4219087687 ps
T845 /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.655779691 Jun 24 04:54:11 PM PDT 24 Jun 24 04:54:45 PM PDT 24 936299119 ps
T846 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1308328251 Jun 24 04:54:46 PM PDT 24 Jun 24 04:58:59 PM PDT 24 43986375293 ps
T847 /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1798597368 Jun 24 04:54:25 PM PDT 24 Jun 24 04:55:11 PM PDT 24 6610952094 ps
T848 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2609603618 Jun 24 04:55:43 PM PDT 24 Jun 24 04:55:51 PM PDT 24 64160077 ps
T210 /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2152609667 Jun 24 04:54:59 PM PDT 24 Jun 24 04:55:29 PM PDT 24 190854011 ps
T849 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.407938070 Jun 24 04:54:34 PM PDT 24 Jun 24 04:58:58 PM PDT 24 8934968398 ps
T850 /workspace/coverage/xbar_build_mode/27.xbar_same_source.4104484133 Jun 24 04:55:02 PM PDT 24 Jun 24 04:55:40 PM PDT 24 8668102059 ps
T851 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1937508870 Jun 24 04:55:15 PM PDT 24 Jun 24 04:55:48 PM PDT 24 451846123 ps
T852 /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.570380682 Jun 24 04:55:04 PM PDT 24 Jun 24 04:55:42 PM PDT 24 657871160 ps
T853 /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.672131948 Jun 24 04:54:33 PM PDT 24 Jun 24 04:57:37 PM PDT 24 35539923127 ps
T854 /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1465569206 Jun 24 04:55:31 PM PDT 24 Jun 24 04:55:36 PM PDT 24 27978106 ps
T855 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.862353891 Jun 24 04:54:59 PM PDT 24 Jun 24 04:56:06 PM PDT 24 1746102413 ps
T856 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3224530777 Jun 24 04:56:08 PM PDT 24 Jun 24 04:56:59 PM PDT 24 2347468006 ps
T857 /workspace/coverage/xbar_build_mode/5.xbar_error_random.4183337944 Jun 24 04:54:06 PM PDT 24 Jun 24 04:54:31 PM PDT 24 379527416 ps
T858 /workspace/coverage/xbar_build_mode/24.xbar_random.2948937889 Jun 24 04:54:51 PM PDT 24 Jun 24 04:55:07 PM PDT 24 60894948 ps
T859 /workspace/coverage/xbar_build_mode/44.xbar_same_source.3886906233 Jun 24 04:55:58 PM PDT 24 Jun 24 04:56:33 PM PDT 24 2523475865 ps
T860 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2234988987 Jun 24 04:54:12 PM PDT 24 Jun 24 04:56:49 PM PDT 24 5300984434 ps
T861 /workspace/coverage/xbar_build_mode/49.xbar_same_source.2488378275 Jun 24 04:56:13 PM PDT 24 Jun 24 04:56:48 PM PDT 24 3671949089 ps
T862 /workspace/coverage/xbar_build_mode/40.xbar_error_random.827037468 Jun 24 04:55:46 PM PDT 24 Jun 24 04:56:05 PM PDT 24 492303870 ps
T863 /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4288095862 Jun 24 04:54:38 PM PDT 24 Jun 24 04:56:45 PM PDT 24 40133702646 ps
T864 /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2205049104 Jun 24 04:55:15 PM PDT 24 Jun 24 04:55:56 PM PDT 24 9354239557 ps
T865 /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1940307761 Jun 24 04:55:03 PM PDT 24 Jun 24 04:56:45 PM PDT 24 21687846672 ps
T866 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4091159540 Jun 24 04:55:23 PM PDT 24 Jun 24 04:58:05 PM PDT 24 3295245643 ps
T867 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.350261712 Jun 24 04:55:05 PM PDT 24 Jun 24 04:55:21 PM PDT 24 142652032 ps
T868 /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1558264691 Jun 24 04:55:46 PM PDT 24 Jun 24 04:56:05 PM PDT 24 131924831 ps
T155 /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3046587796 Jun 24 04:54:47 PM PDT 24 Jun 24 05:04:45 PM PDT 24 182361953381 ps
T869 /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.562209825 Jun 24 04:56:09 PM PDT 24 Jun 24 04:56:36 PM PDT 24 5355308157 ps
T870 /workspace/coverage/xbar_build_mode/48.xbar_smoke.663070149 Jun 24 04:56:08 PM PDT 24 Jun 24 04:56:11 PM PDT 24 24700922 ps
T871 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1454548307 Jun 24 04:55:59 PM PDT 24 Jun 24 04:57:31 PM PDT 24 2524222390 ps
T872 /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3746475752 Jun 24 04:54:45 PM PDT 24 Jun 24 04:54:55 PM PDT 24 81512121 ps
T28 /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2402982937 Jun 24 04:55:59 PM PDT 24 Jun 24 04:56:54 PM PDT 24 2026520146 ps
T873 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.653425612 Jun 24 04:56:05 PM PDT 24 Jun 24 04:56:41 PM PDT 24 1290872529 ps
T874 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2681861156 Jun 24 04:55:41 PM PDT 24 Jun 24 05:06:19 PM PDT 24 103182048197 ps
T875 /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.696278331 Jun 24 04:55:32 PM PDT 24 Jun 24 04:58:36 PM PDT 24 40599304200 ps
T876 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2489897968 Jun 24 04:54:02 PM PDT 24 Jun 24 04:55:44 PM PDT 24 4119856145 ps
T877 /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3353794727 Jun 24 04:54:59 PM PDT 24 Jun 24 04:55:11 PM PDT 24 304103241 ps
T878 /workspace/coverage/xbar_build_mode/34.xbar_error_random.4135632189 Jun 24 04:55:24 PM PDT 24 Jun 24 04:56:08 PM PDT 24 1753740266 ps
T879 /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1092075469 Jun 24 04:54:55 PM PDT 24 Jun 24 04:55:03 PM PDT 24 31046377 ps
T880 /workspace/coverage/xbar_build_mode/29.xbar_error_random.3782605811 Jun 24 04:55:09 PM PDT 24 Jun 24 04:55:20 PM PDT 24 744390390 ps
T881 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3669336820 Jun 24 04:55:36 PM PDT 24 Jun 24 05:03:50 PM PDT 24 3875931389 ps
T882 /workspace/coverage/xbar_build_mode/31.xbar_smoke.268963685 Jun 24 04:55:13 PM PDT 24 Jun 24 04:55:19 PM PDT 24 211261416 ps
T883 /workspace/coverage/xbar_build_mode/24.xbar_stress_all.156705942 Jun 24 04:54:41 PM PDT 24 Jun 24 04:57:36 PM PDT 24 8678795137 ps
T884 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3676817408 Jun 24 04:55:31 PM PDT 24 Jun 24 05:05:17 PM PDT 24 14100019177 ps
T885 /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2251073175 Jun 24 04:55:36 PM PDT 24 Jun 24 04:55:45 PM PDT 24 406900625 ps
T886 /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2144877692 Jun 24 04:55:23 PM PDT 24 Jun 24 04:55:38 PM PDT 24 199100666 ps
T887 /workspace/coverage/xbar_build_mode/20.xbar_error_random.566490636 Jun 24 04:54:42 PM PDT 24 Jun 24 04:55:09 PM PDT 24 306818059 ps
T888 /workspace/coverage/xbar_build_mode/37.xbar_error_random.3489679909 Jun 24 04:55:36 PM PDT 24 Jun 24 04:56:14 PM PDT 24 1054335244 ps
T889 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.909322381 Jun 24 04:55:44 PM PDT 24 Jun 24 04:58:40 PM PDT 24 456266906 ps
T199 /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1950990621 Jun 24 04:55:01 PM PDT 24 Jun 24 04:58:46 PM PDT 24 36035369072 ps
T890 /workspace/coverage/xbar_build_mode/32.xbar_error_random.1529509437 Jun 24 04:55:20 PM PDT 24 Jun 24 04:55:29 PM PDT 24 186571357 ps
T891 /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.184577365 Jun 24 04:54:44 PM PDT 24 Jun 24 04:54:54 PM PDT 24 44142804 ps
T892 /workspace/coverage/xbar_build_mode/48.xbar_error_random.2413681292 Jun 24 04:56:11 PM PDT 24 Jun 24 04:56:16 PM PDT 24 23304282 ps
T893 /workspace/coverage/xbar_build_mode/6.xbar_smoke.3908082055 Jun 24 04:54:15 PM PDT 24 Jun 24 04:54:23 PM PDT 24 662372378 ps
T894 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3158389045 Jun 24 04:56:06 PM PDT 24 Jun 24 04:56:16 PM PDT 24 281197486 ps
T895 /workspace/coverage/xbar_build_mode/46.xbar_random.3344340189 Jun 24 04:56:00 PM PDT 24 Jun 24 04:56:09 PM PDT 24 66061398 ps
T896 /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3945306018 Jun 24 04:54:19 PM PDT 24 Jun 24 04:54:48 PM PDT 24 5022143578 ps
T897 /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.207716207 Jun 24 04:55:31 PM PDT 24 Jun 24 04:55:36 PM PDT 24 28150730 ps
T898 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1894806513 Jun 24 04:54:35 PM PDT 24 Jun 24 04:58:56 PM PDT 24 3564018944 ps
T899 /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3514287494 Jun 24 04:55:01 PM PDT 24 Jun 24 04:55:31 PM PDT 24 705799035 ps
T900 /workspace/coverage/xbar_build_mode/18.xbar_error_random.1330627151 Jun 24 04:54:35 PM PDT 24 Jun 24 04:55:17 PM PDT 24 3446591435 ps

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.826088369
Short name T2
Test name
Test status
Simulation time 360689261 ps
CPU time 74.1 seconds
Started Jun 24 04:54:48 PM PDT 24
Finished Jun 24 04:56:10 PM PDT 24
Peak memory 208348 kb
Host smart-218baf97-1501-4fd8-9765-82b2a5830baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=826088369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res
et_error.826088369
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.783675736
Short name T86
Test name
Test status
Simulation time 122351242966 ps
CPU time 609.4 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 05:05:14 PM PDT 24
Peak memory 211548 kb
Host smart-39868876-fb7f-4aa5-b373-83d7e35e2ffa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=783675736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo
w_rsp.783675736
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2211470189
Short name T110
Test name
Test status
Simulation time 84141527497 ps
CPU time 654.69 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 05:05:24 PM PDT 24
Peak memory 211648 kb
Host smart-94b62cca-a8ae-4a93-9d37-8100a4503e8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2211470189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2211470189
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2423805291
Short name T63
Test name
Test status
Simulation time 70332558594 ps
CPU time 288.91 seconds
Started Jun 24 04:54:23 PM PDT 24
Finished Jun 24 04:59:15 PM PDT 24
Peak memory 211532 kb
Host smart-b1241245-0fe0-4a5b-af6f-efdc9c93a0eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2423805291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.2423805291
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.277860106
Short name T5
Test name
Test status
Simulation time 99951140 ps
CPU time 13.73 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:55:02 PM PDT 24
Peak memory 204528 kb
Host smart-82e146ce-3705-47a9-96b1-1de12ce85d62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277860106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.277860106
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1637633755
Short name T92
Test name
Test status
Simulation time 528307452905 ps
CPU time 707.43 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 05:06:56 PM PDT 24
Peak memory 211648 kb
Host smart-39bb9900-cf7f-441e-9909-53553f65ef87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1637633755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.1637633755
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2089646421
Short name T6
Test name
Test status
Simulation time 4996765606 ps
CPU time 155.48 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:57:22 PM PDT 24
Peak memory 208516 kb
Host smart-323c57c6-2964-4ac4-bab5-932b42c417ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2089646421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2089646421
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1282889094
Short name T8
Test name
Test status
Simulation time 27045867924 ps
CPU time 44.59 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:56:46 PM PDT 24
Peak memory 203464 kb
Host smart-c8c67562-00c6-4fe0-8886-006858329c9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282889094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1282889094
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.4048192338
Short name T89
Test name
Test status
Simulation time 45179563058 ps
CPU time 278.55 seconds
Started Jun 24 04:54:52 PM PDT 24
Finished Jun 24 04:59:37 PM PDT 24
Peak memory 207408 kb
Host smart-ecf4cd98-2d98-49ad-af15-25e0de613150
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048192338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4048192338
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.94008619
Short name T14
Test name
Test status
Simulation time 839372090 ps
CPU time 225.37 seconds
Started Jun 24 04:55:12 PM PDT 24
Finished Jun 24 04:58:58 PM PDT 24
Peak memory 208616 kb
Host smart-f8d40a35-121b-436f-bff6-8f0a410b5f7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94008619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_
reset.94008619
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2746954536
Short name T26
Test name
Test status
Simulation time 3416187297 ps
CPU time 415.57 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 05:03:06 PM PDT 24
Peak memory 209640 kb
Host smart-eb1a398a-8a2c-4d05-bbb3-f771d5678e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2746954536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.2746954536
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.550277745
Short name T23
Test name
Test status
Simulation time 9962852075 ps
CPU time 486.83 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 05:03:02 PM PDT 24
Peak memory 220568 kb
Host smart-45cd7df2-d460-44a4-97b2-fa594aed6716
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=550277745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res
et_error.550277745
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2662356634
Short name T197
Test name
Test status
Simulation time 274524114209 ps
CPU time 581.74 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 05:04:24 PM PDT 24
Peak memory 211644 kb
Host smart-82d42028-94f5-4d37-ac5c-a50506a430cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2662356634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.2662356634
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.616778929
Short name T182
Test name
Test status
Simulation time 585366399 ps
CPU time 163.49 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:56:57 PM PDT 24
Peak memory 211328 kb
Host smart-60f0021e-04e9-48d3-9cac-8d52d4c9b4f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=616778929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese
t_error.616778929
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3449064852
Short name T33
Test name
Test status
Simulation time 1794804993 ps
CPU time 185.74 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:58:45 PM PDT 24
Peak memory 210400 kb
Host smart-6ea61101-80f5-4d62-b1f9-f3779dcef872
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3449064852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.3449064852
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.371577943
Short name T68
Test name
Test status
Simulation time 15669849728 ps
CPU time 128.45 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:57:11 PM PDT 24
Peak memory 207008 kb
Host smart-09afd392-c68d-4db9-b62d-92244f1bb6f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=371577943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.371577943
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4206365635
Short name T17
Test name
Test status
Simulation time 412731658 ps
CPU time 147.67 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:58:29 PM PDT 24
Peak memory 208252 kb
Host smart-87aed9b6-8678-4ffb-b0cb-efabebefd213
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206365635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.4206365635
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2677599934
Short name T133
Test name
Test status
Simulation time 40449005214 ps
CPU time 286.81 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:58:54 PM PDT 24
Peak memory 211540 kb
Host smart-b00a4890-1b21-45bf-a0e9-5145a324ba52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2677599934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2677599934
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1627673771
Short name T105
Test name
Test status
Simulation time 719402286 ps
CPU time 14.52 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:54:10 PM PDT 24
Peak memory 211512 kb
Host smart-edd716e2-6629-4c09-b299-0ebf4a7a11eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1627673771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1627673771
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3526867948
Short name T478
Test name
Test status
Simulation time 63780980 ps
CPU time 3.04 seconds
Started Jun 24 04:53:50 PM PDT 24
Finished Jun 24 04:53:57 PM PDT 24
Peak memory 203332 kb
Host smart-d06058d7-1224-4a81-9d3d-bfc58dcc6f68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3526867948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3526867948
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2607236379
Short name T837
Test name
Test status
Simulation time 38821512 ps
CPU time 2 seconds
Started Jun 24 04:53:53 PM PDT 24
Finished Jun 24 04:54:00 PM PDT 24
Peak memory 203412 kb
Host smart-e9035ef6-b513-4610-9abe-6b87cf38857b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2607236379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2607236379
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.4261466182
Short name T629
Test name
Test status
Simulation time 1215510407 ps
CPU time 26.14 seconds
Started Jun 24 04:54:00 PM PDT 24
Finished Jun 24 04:54:32 PM PDT 24
Peak memory 203432 kb
Host smart-75c0483d-23fd-4737-be10-c0097dc9c4af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4261466182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4261466182
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.4183239201
Short name T779
Test name
Test status
Simulation time 337964260 ps
CPU time 14.13 seconds
Started Jun 24 04:53:47 PM PDT 24
Finished Jun 24 04:54:05 PM PDT 24
Peak memory 211568 kb
Host smart-e6588f38-2624-4ea0-83a3-d4f59e047041
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4183239201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4183239201
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4119635979
Short name T175
Test name
Test status
Simulation time 37084306597 ps
CPU time 183.85 seconds
Started Jun 24 04:53:46 PM PDT 24
Finished Jun 24 04:56:53 PM PDT 24
Peak memory 211656 kb
Host smart-9a1734f0-5415-4c6a-a69c-d8f2fdc2143b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119635979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4119635979
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2683807396
Short name T232
Test name
Test status
Simulation time 32144077571 ps
CPU time 191.18 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:57:06 PM PDT 24
Peak memory 204944 kb
Host smart-f33c4a48-d4c6-469c-9018-056cdd16111b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2683807396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2683807396
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2033582758
Short name T179
Test name
Test status
Simulation time 66180538 ps
CPU time 7.04 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:54:13 PM PDT 24
Peak memory 211564 kb
Host smart-f846ac4f-e252-4ed7-82e4-a58febade38e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033582758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2033582758
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.4016251838
Short name T390
Test name
Test status
Simulation time 799782400 ps
CPU time 18.14 seconds
Started Jun 24 04:53:52 PM PDT 24
Finished Jun 24 04:54:16 PM PDT 24
Peak memory 204128 kb
Host smart-4d91af43-4dd2-4b1f-b82f-ca7ec6754409
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4016251838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4016251838
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.934123938
Short name T753
Test name
Test status
Simulation time 107053442 ps
CPU time 3.17 seconds
Started Jun 24 04:53:45 PM PDT 24
Finished Jun 24 04:53:51 PM PDT 24
Peak memory 203292 kb
Host smart-398f4532-d2f0-4333-9ebf-d9403abb98f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=934123938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.934123938
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3230828574
Short name T410
Test name
Test status
Simulation time 13880850662 ps
CPU time 35.43 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:54:30 PM PDT 24
Peak memory 203400 kb
Host smart-7cc667ca-05aa-4148-b714-a70a189dfe80
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230828574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3230828574
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3552128947
Short name T486
Test name
Test status
Simulation time 4033063568 ps
CPU time 36 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:54:32 PM PDT 24
Peak memory 203420 kb
Host smart-9df037d1-5fcf-452b-8730-f8a4f8fcbef8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3552128947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3552128947
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3668532095
Short name T699
Test name
Test status
Simulation time 29018923 ps
CPU time 2.11 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:54:14 PM PDT 24
Peak memory 203300 kb
Host smart-245fa6c0-2e68-43c7-9cbe-d2e731d7d582
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668532095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3668532095
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.816582371
Short name T303
Test name
Test status
Simulation time 1753596322 ps
CPU time 140.56 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:56:33 PM PDT 24
Peak memory 208736 kb
Host smart-8bd25b49-8e80-43bc-b547-c5ca2b7a6a7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=816582371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.816582371
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1735788475
Short name T805
Test name
Test status
Simulation time 58998090439 ps
CPU time 290.89 seconds
Started Jun 24 04:53:48 PM PDT 24
Finished Jun 24 04:58:44 PM PDT 24
Peak memory 207052 kb
Host smart-1849ad3c-5272-4f66-a00d-1335f530e322
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1735788475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1735788475
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1007465409
Short name T353
Test name
Test status
Simulation time 565242751 ps
CPU time 171.4 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:56:46 PM PDT 24
Peak memory 208152 kb
Host smart-62cf517c-8565-401e-b32c-691c558160eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1007465409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.1007465409
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3164825176
Short name T706
Test name
Test status
Simulation time 26573832269 ps
CPU time 473.86 seconds
Started Jun 24 04:54:02 PM PDT 24
Finished Jun 24 05:02:01 PM PDT 24
Peak memory 219792 kb
Host smart-d3f4cb85-7b8e-41f5-8d07-92e276250cde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3164825176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.3164825176
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.866846376
Short name T697
Test name
Test status
Simulation time 3059760035 ps
CPU time 63.31 seconds
Started Jun 24 04:53:50 PM PDT 24
Finished Jun 24 04:54:58 PM PDT 24
Peak memory 211576 kb
Host smart-1b2b90df-d048-46e7-965b-630073675a2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=866846376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.866846376
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2510526122
Short name T270
Test name
Test status
Simulation time 87839166400 ps
CPU time 430.12 seconds
Started Jun 24 04:53:50 PM PDT 24
Finished Jun 24 05:01:05 PM PDT 24
Peak memory 207016 kb
Host smart-29f2a8e1-6db8-4df5-ae9d-c415d073bb84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2510526122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.2510526122
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3935996496
Short name T310
Test name
Test status
Simulation time 521346772 ps
CPU time 16.06 seconds
Started Jun 24 04:53:52 PM PDT 24
Finished Jun 24 04:54:14 PM PDT 24
Peak memory 203424 kb
Host smart-24b0198a-f67d-4609-abc8-bcaf49455782
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3935996496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3935996496
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.3188279261
Short name T16
Test name
Test status
Simulation time 161033929 ps
CPU time 15.81 seconds
Started Jun 24 04:53:56 PM PDT 24
Finished Jun 24 04:54:17 PM PDT 24
Peak memory 203436 kb
Host smart-31421656-b010-4cb3-88bc-0f3011fd2958
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3188279261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3188279261
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.367403603
Short name T793
Test name
Test status
Simulation time 157186546 ps
CPU time 4.45 seconds
Started Jun 24 04:53:53 PM PDT 24
Finished Jun 24 04:54:02 PM PDT 24
Peak memory 203988 kb
Host smart-a51b6ef7-8ad7-47f2-afa8-9d38e576573a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=367403603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.367403603
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.403704307
Short name T382
Test name
Test status
Simulation time 8703892903 ps
CPU time 51.47 seconds
Started Jun 24 04:53:58 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 211612 kb
Host smart-f91b4bc7-89f0-4809-8095-735677fa17b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=403704307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.403704307
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2918744373
Short name T698
Test name
Test status
Simulation time 14491378523 ps
CPU time 99.97 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:55:35 PM PDT 24
Peak memory 211848 kb
Host smart-2e6aee0d-4b95-433b-9abf-c050a2712b81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2918744373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2918744373
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2436983544
Short name T801
Test name
Test status
Simulation time 184290028 ps
CPU time 13.39 seconds
Started Jun 24 04:53:51 PM PDT 24
Finished Jun 24 04:54:09 PM PDT 24
Peak memory 211588 kb
Host smart-925f97fb-3f74-4df7-81d9-7943337cfea7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436983544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2436983544
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.4166056137
Short name T587
Test name
Test status
Simulation time 856181240 ps
CPU time 13.65 seconds
Started Jun 24 04:53:56 PM PDT 24
Finished Jun 24 04:54:15 PM PDT 24
Peak memory 204096 kb
Host smart-60c6a5c5-6cfc-4199-ba0c-bfd0487daeb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4166056137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4166056137
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.231587855
Short name T625
Test name
Test status
Simulation time 139420256 ps
CPU time 3.61 seconds
Started Jun 24 04:53:50 PM PDT 24
Finished Jun 24 04:53:58 PM PDT 24
Peak memory 203408 kb
Host smart-f9769372-6823-4f6a-8f81-31607f534419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=231587855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.231587855
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1314188303
Short name T579
Test name
Test status
Simulation time 32677805736 ps
CPU time 37 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:51 PM PDT 24
Peak memory 203448 kb
Host smart-ab26d2e9-d30e-4918-99fa-33a586b4cd1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314188303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1314188303
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1388223316
Short name T104
Test name
Test status
Simulation time 5443195144 ps
CPU time 34.91 seconds
Started Jun 24 04:53:58 PM PDT 24
Finished Jun 24 04:54:38 PM PDT 24
Peak memory 203432 kb
Host smart-86b54d23-99a0-4f64-8011-35b33ed0242d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1388223316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1388223316
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1683641849
Short name T454
Test name
Test status
Simulation time 23920018 ps
CPU time 2.01 seconds
Started Jun 24 04:53:58 PM PDT 24
Finished Jun 24 04:54:05 PM PDT 24
Peak memory 203372 kb
Host smart-9d848a20-5349-405c-8376-cc0be934d1e5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683641849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1683641849
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.628453485
Short name T115
Test name
Test status
Simulation time 3952071825 ps
CPU time 110.69 seconds
Started Jun 24 04:54:02 PM PDT 24
Finished Jun 24 04:55:58 PM PDT 24
Peak memory 206972 kb
Host smart-1e50a1fc-b068-416d-99b4-d1002e2ceb10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=628453485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.628453485
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2489897968
Short name T876
Test name
Test status
Simulation time 4119856145 ps
CPU time 96.59 seconds
Started Jun 24 04:54:02 PM PDT 24
Finished Jun 24 04:55:44 PM PDT 24
Peak memory 207556 kb
Host smart-f4c2fba4-e84f-457e-a21e-d820aa071ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2489897968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2489897968
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.622284206
Short name T29
Test name
Test status
Simulation time 819301205 ps
CPU time 164.23 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:56:50 PM PDT 24
Peak memory 207920 kb
Host smart-de8c9028-cd84-417d-a4e8-b1f2a20bb7ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=622284206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_
reset.622284206
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.230798171
Short name T582
Test name
Test status
Simulation time 22426262902 ps
CPU time 496.29 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 05:02:34 PM PDT 24
Peak memory 220268 kb
Host smart-05cf3925-a016-4861-b8b6-7f78dcbeec75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=230798171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese
t_error.230798171
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2773369624
Short name T40
Test name
Test status
Simulation time 126649370 ps
CPU time 12.02 seconds
Started Jun 24 04:53:49 PM PDT 24
Finished Jun 24 04:54:06 PM PDT 24
Peak memory 211484 kb
Host smart-1b1a4b69-9cfc-40d4-805c-89539ef088f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2773369624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2773369624
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1086677369
Short name T703
Test name
Test status
Simulation time 3229831111 ps
CPU time 43.25 seconds
Started Jun 24 04:54:17 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 205272 kb
Host smart-e7fb5ea8-9e8f-4977-9cc0-61d20712423b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1086677369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1086677369
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3006555293
Short name T602
Test name
Test status
Simulation time 35401040618 ps
CPU time 336.39 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 05:00:11 PM PDT 24
Peak memory 206008 kb
Host smart-769b36b1-b3e3-4426-8a69-9376884740aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3006555293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.3006555293
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3489998606
Short name T502
Test name
Test status
Simulation time 973733539 ps
CPU time 18.97 seconds
Started Jun 24 04:54:40 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 203420 kb
Host smart-7eeadddf-0ea9-46ce-82c4-56f2a6242d6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3489998606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3489998606
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.3549751545
Short name T760
Test name
Test status
Simulation time 593900494 ps
CPU time 23.44 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203412 kb
Host smart-5efb6c2a-0647-4200-b494-f33034954647
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549751545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3549751545
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.490858521
Short name T254
Test name
Test status
Simulation time 415195062 ps
CPU time 11.89 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:54:29 PM PDT 24
Peak memory 211572 kb
Host smart-ef79cf1f-d875-4cf0-be9e-8ab556c9ffda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=490858521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.490858521
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.708946004
Short name T319
Test name
Test status
Simulation time 3752435704 ps
CPU time 23.16 seconds
Started Jun 24 04:54:19 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 204460 kb
Host smart-78f65e35-c440-41ea-b83a-0e8d950d015e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=708946004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.708946004
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1725619216
Short name T49
Test name
Test status
Simulation time 1527811996 ps
CPU time 9.5 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:25 PM PDT 24
Peak memory 203328 kb
Host smart-b38f189e-cd7d-4293-b7c4-ff82de482bc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1725619216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1725619216
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1886556650
Short name T313
Test name
Test status
Simulation time 225504987 ps
CPU time 22.19 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 211576 kb
Host smart-3c34d2e1-2c6c-44fe-b5c6-b616f00678ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886556650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1886556650
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2972131925
Short name T680
Test name
Test status
Simulation time 710804423 ps
CPU time 12.92 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 203356 kb
Host smart-d575bd08-7d63-487c-8bad-a2b20d3e6a23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2972131925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2972131925
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.1950349680
Short name T447
Test name
Test status
Simulation time 209738928 ps
CPU time 3.25 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:19 PM PDT 24
Peak memory 203320 kb
Host smart-50cc22b9-107a-4d94-9b69-da85af8bcbb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1950349680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1950349680
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3867887657
Short name T330
Test name
Test status
Simulation time 17213057820 ps
CPU time 37.8 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:53 PM PDT 24
Peak memory 203372 kb
Host smart-3dc68fdd-1882-4d79-b88f-86479a4136b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867887657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3867887657
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3952404486
Short name T274
Test name
Test status
Simulation time 9715256251 ps
CPU time 33.79 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203720 kb
Host smart-12abf1a1-adde-4a6d-924e-2e4f9a9eeb4f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3952404486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3952404486
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3394969144
Short name T436
Test name
Test status
Simulation time 28863886 ps
CPU time 2.43 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 203380 kb
Host smart-392e9ddc-c4f1-4837-9522-a60cb65ee846
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394969144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3394969144
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3976040109
Short name T791
Test name
Test status
Simulation time 7271188057 ps
CPU time 191.29 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:58:09 PM PDT 24
Peak memory 211592 kb
Host smart-dd277c2c-cc8f-4747-aa01-f9899470fcdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3976040109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3976040109
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3938784367
Short name T813
Test name
Test status
Simulation time 10683597542 ps
CPU time 102.52 seconds
Started Jun 24 04:54:31 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 208076 kb
Host smart-2762e58d-3796-426a-9de2-cbf1daec3314
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3938784367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3938784367
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3931431664
Short name T134
Test name
Test status
Simulation time 7432651292 ps
CPU time 433.49 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 05:01:44 PM PDT 24
Peak memory 219768 kb
Host smart-57118320-aef6-441f-a87b-3b5adb1e87fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3931431664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3931431664
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.4101722468
Short name T404
Test name
Test status
Simulation time 1578707827 ps
CPU time 305.35 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:59:43 PM PDT 24
Peak memory 223244 kb
Host smart-16ed0cbb-073e-4e81-aa9f-dea610b9d55b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4101722468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.4101722468
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.326280153
Short name T705
Test name
Test status
Simulation time 436932270 ps
CPU time 10.88 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:31 PM PDT 24
Peak memory 211508 kb
Host smart-08499b50-dc5f-43e7-8c44-7dea5524246f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=326280153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.326280153
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3437902526
Short name T84
Test name
Test status
Simulation time 1171976831 ps
CPU time 16.87 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 211492 kb
Host smart-261df993-990a-4d2d-a2d5-a613e84ac8e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437902526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3437902526
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2630360890
Short name T471
Test name
Test status
Simulation time 5257618128 ps
CPU time 37.56 seconds
Started Jun 24 04:54:33 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203460 kb
Host smart-0d4cfaa3-a56d-41ff-9886-d3d3fe604986
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2630360890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.2630360890
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3511108179
Short name T276
Test name
Test status
Simulation time 828417520 ps
CPU time 23.55 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:54:46 PM PDT 24
Peak memory 203660 kb
Host smart-c9427b4f-deac-46b9-9f59-95b3f015dd1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3511108179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3511108179
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.2097530939
Short name T297
Test name
Test status
Simulation time 189678260 ps
CPU time 6.6 seconds
Started Jun 24 04:54:21 PM PDT 24
Finished Jun 24 04:54:30 PM PDT 24
Peak memory 203420 kb
Host smart-8d2592d4-eec6-45b7-a38f-c760c25c2649
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2097530939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2097530939
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.2014439472
Short name T90
Test name
Test status
Simulation time 1136406745 ps
CPU time 18.38 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:54:49 PM PDT 24
Peak memory 211480 kb
Host smart-bd836222-bb3e-4386-ae8d-65ff7945f1e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2014439472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2014439472
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.415429999
Short name T100
Test name
Test status
Simulation time 42319169210 ps
CPU time 218.22 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:58:06 PM PDT 24
Peak memory 204704 kb
Host smart-78de1d50-c9ec-45ed-ac43-444faa42f626
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=415429999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.415429999
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3952392738
Short name T567
Test name
Test status
Simulation time 186351677245 ps
CPU time 378.13 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 05:01:05 PM PDT 24
Peak memory 205016 kb
Host smart-7b5de72a-9ffd-4dc9-9646-e45677a86571
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3952392738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3952392738
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1078134765
Short name T695
Test name
Test status
Simulation time 146272253 ps
CPU time 18.96 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 211560 kb
Host smart-66b9ea67-e69b-4280-b016-595b5d72b012
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078134765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1078134765
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.992306299
Short name T598
Test name
Test status
Simulation time 973847989 ps
CPU time 12.73 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 204336 kb
Host smart-4a71c091-a79d-463e-a93a-b48d81868027
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=992306299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.992306299
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.1182517710
Short name T293
Test name
Test status
Simulation time 611630430 ps
CPU time 4.26 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:54:28 PM PDT 24
Peak memory 203308 kb
Host smart-aa30a6f5-2788-493b-957c-4e85c0fb301d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1182517710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1182517710
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2687413121
Short name T728
Test name
Test status
Simulation time 11090306358 ps
CPU time 30.43 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203404 kb
Host smart-9e8043ae-f009-419f-a5cd-b348a07d12ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687413121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2687413121
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1005444121
Short name T720
Test name
Test status
Simulation time 22260801208 ps
CPU time 43.04 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:55:18 PM PDT 24
Peak memory 203460 kb
Host smart-2e2e5b23-c6d9-4efc-85b6-0e8b4b0a9b19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1005444121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1005444121
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.812088944
Short name T299
Test name
Test status
Simulation time 142087279 ps
CPU time 2.3 seconds
Started Jun 24 04:54:18 PM PDT 24
Finished Jun 24 04:54:24 PM PDT 24
Peak memory 203268 kb
Host smart-5cc0d76e-7bf5-4129-b31b-57b4bbc66047
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812088944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.812088944
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3436235889
Short name T220
Test name
Test status
Simulation time 1289999062 ps
CPU time 153.34 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:57:06 PM PDT 24
Peak memory 208252 kb
Host smart-a71ac248-7b8c-4f68-8819-f88670e45581
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3436235889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3436235889
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2906584483
Short name T401
Test name
Test status
Simulation time 2743555962 ps
CPU time 45.2 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 205076 kb
Host smart-b3409b2d-2f48-4b01-8d1c-cab144fee41a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2906584483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2906584483
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3502790788
Short name T145
Test name
Test status
Simulation time 5186998486 ps
CPU time 226.97 seconds
Started Jun 24 04:54:21 PM PDT 24
Finished Jun 24 04:58:11 PM PDT 24
Peak memory 208064 kb
Host smart-e3ccb5b8-6723-4a94-a13d-a494ed04e138
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3502790788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.3502790788
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2053943882
Short name T456
Test name
Test status
Simulation time 496864539 ps
CPU time 85.8 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 207328 kb
Host smart-7053e556-6a85-47d3-b880-696cf01b21d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2053943882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.2053943882
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2779624215
Short name T529
Test name
Test status
Simulation time 72497546 ps
CPU time 8.12 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 211572 kb
Host smart-73a8e294-3066-4edd-aa89-9997f5746db6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779624215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2779624215
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2130061757
Short name T739
Test name
Test status
Simulation time 509476343 ps
CPU time 31.84 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 211528 kb
Host smart-de4acfe5-401b-4c79-bce7-c3924671010f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2130061757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2130061757
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3046587796
Short name T155
Test name
Test status
Simulation time 182361953381 ps
CPU time 590.53 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 05:04:45 PM PDT 24
Peak memory 206932 kb
Host smart-90d3a942-33e4-42ad-8e79-18d56c8e9457
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3046587796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.3046587796
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3206473277
Short name T464
Test name
Test status
Simulation time 364150435 ps
CPU time 14.16 seconds
Started Jun 24 04:54:31 PM PDT 24
Finished Jun 24 04:54:49 PM PDT 24
Peak memory 203420 kb
Host smart-3be9c6d6-6f78-4b9a-832d-535373670ff6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3206473277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3206473277
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.2828518690
Short name T412
Test name
Test status
Simulation time 285643449 ps
CPU time 6.18 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:55:05 PM PDT 24
Peak memory 203304 kb
Host smart-fdde2679-8dcc-4f12-b34b-2ca2c33668e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2828518690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2828518690
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.2294769145
Short name T194
Test name
Test status
Simulation time 891433351 ps
CPU time 20.88 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:54:53 PM PDT 24
Peak memory 211496 kb
Host smart-3778b66d-7b15-4e9a-8c72-3d77bc0f8261
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2294769145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2294769145
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3540014304
Short name T257
Test name
Test status
Simulation time 24881550511 ps
CPU time 124.7 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 04:56:34 PM PDT 24
Peak memory 204616 kb
Host smart-7bf1bd1c-a700-4a53-bc24-14b21892d9a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540014304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3540014304
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3003129828
Short name T61
Test name
Test status
Simulation time 72927982953 ps
CPU time 200.95 seconds
Started Jun 24 04:54:24 PM PDT 24
Finished Jun 24 04:57:48 PM PDT 24
Peak memory 211596 kb
Host smart-a1473bbe-bff9-45b9-a502-4afa33c5d547
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3003129828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3003129828
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3982758421
Short name T239
Test name
Test status
Simulation time 183913484 ps
CPU time 20.01 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 211568 kb
Host smart-e491ebe3-e2f9-49a9-9171-851949bb0c12
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982758421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3982758421
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1903327456
Short name T225
Test name
Test status
Simulation time 509515966 ps
CPU time 6.67 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:54:58 PM PDT 24
Peak memory 204204 kb
Host smart-9fd963ff-77a9-41f0-92c6-a1a865f0c0aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1903327456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1903327456
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.16290234
Short name T729
Test name
Test status
Simulation time 1136702256 ps
CPU time 4.49 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 203396 kb
Host smart-c98d5db2-c0a2-4fcc-ae79-f3443ba120ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16290234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.16290234
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2652845203
Short name T511
Test name
Test status
Simulation time 10986124230 ps
CPU time 34.26 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:54 PM PDT 24
Peak memory 203712 kb
Host smart-99db5883-a115-49e0-9d5b-2865a31953c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652845203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2652845203
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.124521773
Short name T714
Test name
Test status
Simulation time 5948476127 ps
CPU time 29.75 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:55:02 PM PDT 24
Peak memory 203388 kb
Host smart-60d79de8-c00c-4d53-aad1-cb2076aa65ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=124521773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.124521773
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2586716277
Short name T236
Test name
Test status
Simulation time 34178589 ps
CPU time 2.2 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 203308 kb
Host smart-8e47cf40-cd2a-4efe-a9a7-5dafd30c3ffc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586716277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2586716277
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1061271636
Short name T577
Test name
Test status
Simulation time 6807789557 ps
CPU time 144.23 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:56:53 PM PDT 24
Peak memory 206088 kb
Host smart-cd9c8f15-a359-4ed9-9314-873e3719ebed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1061271636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1061271636
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3337457258
Short name T513
Test name
Test status
Simulation time 5945759755 ps
CPU time 56.31 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 206816 kb
Host smart-ac9272fe-0529-48ce-b787-7bbadfd9a198
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3337457258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3337457258
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.94210416
Short name T459
Test name
Test status
Simulation time 152809921 ps
CPU time 44.91 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:55:35 PM PDT 24
Peak memory 207804 kb
Host smart-f19c5abc-459e-42a4-8389-bc87a9fee0cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94210416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_
reset.94210416
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3539894244
Short name T22
Test name
Test status
Simulation time 1153701216 ps
CPU time 256.69 seconds
Started Jun 24 04:54:48 PM PDT 24
Finished Jun 24 04:59:13 PM PDT 24
Peak memory 219800 kb
Host smart-28d00de0-d24b-4053-b8fc-e512d4e0299b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3539894244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3539894244
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1720162852
Short name T406
Test name
Test status
Simulation time 85168355 ps
CPU time 7.95 seconds
Started Jun 24 04:54:40 PM PDT 24
Finished Jun 24 04:54:53 PM PDT 24
Peak memory 211556 kb
Host smart-fc806cc9-3621-4e37-a0b4-043212042fcb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1720162852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1720162852
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1287701327
Short name T81
Test name
Test status
Simulation time 2494682443 ps
CPU time 56.24 seconds
Started Jun 24 04:54:24 PM PDT 24
Finished Jun 24 04:55:23 PM PDT 24
Peak memory 211652 kb
Host smart-6f887903-a31e-4418-aebc-808909060971
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1287701327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1287701327
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2535504311
Short name T356
Test name
Test status
Simulation time 34505555 ps
CPU time 1.8 seconds
Started Jun 24 04:54:21 PM PDT 24
Finished Jun 24 04:54:25 PM PDT 24
Peak memory 203344 kb
Host smart-9155e265-897f-44e0-bc46-6562dc8b3133
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2535504311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2535504311
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.370475219
Short name T824
Test name
Test status
Simulation time 15816126 ps
CPU time 1.8 seconds
Started Jun 24 04:54:31 PM PDT 24
Finished Jun 24 04:54:37 PM PDT 24
Peak memory 203424 kb
Host smart-8dd9e917-6e8b-4e5f-9752-5c09ff533e06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=370475219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.370475219
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.3959319060
Short name T45
Test name
Test status
Simulation time 325140643 ps
CPU time 9 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:54:43 PM PDT 24
Peak memory 211560 kb
Host smart-ba90bf2f-0de2-4486-8d4d-ccd6bbafd3a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3959319060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3959319060
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3019545350
Short name T461
Test name
Test status
Simulation time 18981245872 ps
CPU time 54.81 seconds
Started Jun 24 04:54:31 PM PDT 24
Finished Jun 24 04:55:30 PM PDT 24
Peak memory 211560 kb
Host smart-06d244bf-d483-4530-9953-df9336505c60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019545350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3019545350
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2951521484
Short name T443
Test name
Test status
Simulation time 206698581186 ps
CPU time 410.03 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 05:01:13 PM PDT 24
Peak memory 211568 kb
Host smart-8906b3b6-65fa-4d2b-955f-298301edc281
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2951521484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2951521484
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3295029244
Short name T246
Test name
Test status
Simulation time 95630591 ps
CPU time 12.86 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:54:52 PM PDT 24
Peak memory 211740 kb
Host smart-3bceb308-090b-414d-b490-06bd7902e2a0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295029244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3295029244
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.3238694569
Short name T35
Test name
Test status
Simulation time 216680006 ps
CPU time 4.65 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 203576 kb
Host smart-d7a0b149-5a5c-4839-b310-170b108ce307
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3238694569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3238694569
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.1312446352
Short name T47
Test name
Test status
Simulation time 49275180 ps
CPU time 2.23 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 203380 kb
Host smart-337798f2-9525-4731-998a-c6655ac05f14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1312446352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1312446352
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1609752496
Short name T761
Test name
Test status
Simulation time 9912771547 ps
CPU time 31.81 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:54:57 PM PDT 24
Peak memory 203452 kb
Host smart-16ba3b0c-8dd8-44bc-9ae1-f018edc7b46d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609752496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1609752496
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2589586897
Short name T521
Test name
Test status
Simulation time 3341583118 ps
CPU time 27.12 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:54:59 PM PDT 24
Peak memory 203400 kb
Host smart-97051821-0de2-4300-a9f8-5c8cf07e9d09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2589586897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2589586897
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.998239655
Short name T306
Test name
Test status
Simulation time 27987823 ps
CPU time 2.48 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:54:35 PM PDT 24
Peak memory 203360 kb
Host smart-8c610fbd-97b1-4afc-ae97-08ddff4efa84
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998239655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.998239655
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.541428122
Short name T654
Test name
Test status
Simulation time 429521040 ps
CPU time 42.07 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:55:05 PM PDT 24
Peak memory 206284 kb
Host smart-39628c5a-12a8-4516-9575-64464c92b4f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=541428122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.541428122
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2767628441
Short name T650
Test name
Test status
Simulation time 4434121447 ps
CPU time 147.47 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:57:22 PM PDT 24
Peak memory 208740 kb
Host smart-0e17a5e4-49b5-4d17-ad88-0485d24e76d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2767628441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2767628441
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3003797088
Short name T580
Test name
Test status
Simulation time 580493530 ps
CPU time 177.72 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:57:39 PM PDT 24
Peak memory 208332 kb
Host smart-37a13df4-aa2b-447e-82ca-6934e8fc53a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3003797088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.3003797088
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2512353323
Short name T25
Test name
Test status
Simulation time 826521041 ps
CPU time 136.84 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:57:07 PM PDT 24
Peak memory 208852 kb
Host smart-1cdbf9b8-be89-4ad6-9435-e99ccec21cd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2512353323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.2512353323
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2882968851
Short name T351
Test name
Test status
Simulation time 137556314 ps
CPU time 5.11 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 211472 kb
Host smart-c20cea0f-a9b8-4a84-9c05-bbfbe63042ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2882968851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2882968851
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2237931149
Short name T52
Test name
Test status
Simulation time 2649108269 ps
CPU time 63.42 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:55:35 PM PDT 24
Peak memory 211564 kb
Host smart-af929346-b7c2-4324-9e28-5bffb6a47106
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2237931149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2237931149
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3442359472
Short name T300
Test name
Test status
Simulation time 331385901 ps
CPU time 10.98 seconds
Started Jun 24 04:54:31 PM PDT 24
Finished Jun 24 04:54:47 PM PDT 24
Peak memory 203420 kb
Host smart-d904b59a-7228-4b44-889a-ee2645fd56d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3442359472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3442359472
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2916826736
Short name T636
Test name
Test status
Simulation time 2130545041 ps
CPU time 28.59 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 04:54:58 PM PDT 24
Peak memory 203416 kb
Host smart-cbbb5263-0055-44ba-b108-fb1f3cca47ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2916826736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2916826736
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1873331051
Short name T683
Test name
Test status
Simulation time 1093832261 ps
CPU time 32.35 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 205016 kb
Host smart-71b0f399-0ad0-4b18-8038-caa5848deb03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1873331051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1873331051
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3491661427
Short name T378
Test name
Test status
Simulation time 24191857308 ps
CPU time 115.87 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:56:54 PM PDT 24
Peak memory 211556 kb
Host smart-4371803c-7f51-4af0-82f8-da9b9d0ff57c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491661427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3491661427
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.540474977
Short name T708
Test name
Test status
Simulation time 4015894698 ps
CPU time 18.18 seconds
Started Jun 24 04:54:19 PM PDT 24
Finished Jun 24 04:54:40 PM PDT 24
Peak memory 203388 kb
Host smart-86fa23a9-c7cd-423c-b612-08a88de9cbb9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=540474977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.540474977
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.180796947
Short name T626
Test name
Test status
Simulation time 357797388 ps
CPU time 27.23 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:11 PM PDT 24
Peak memory 211544 kb
Host smart-a74652cf-eca2-4d8d-8c85-609c9bbbcb2e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180796947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.180796947
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.4023556305
Short name T434
Test name
Test status
Simulation time 276294634 ps
CPU time 10.89 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:54:43 PM PDT 24
Peak memory 203988 kb
Host smart-f0eaaf9c-22b1-47b6-b760-36c3520b3c78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4023556305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4023556305
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.3397871464
Short name T392
Test name
Test status
Simulation time 285915137 ps
CPU time 3.6 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203392 kb
Host smart-b5f2c6e8-ae66-4023-b93a-6f250771bfe3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3397871464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3397871464
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3945306018
Short name T896
Test name
Test status
Simulation time 5022143578 ps
CPU time 26.41 seconds
Started Jun 24 04:54:19 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203420 kb
Host smart-93ffca2b-2496-4fc0-bfad-73e91b8478a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945306018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3945306018
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2757959397
Short name T411
Test name
Test status
Simulation time 9466328140 ps
CPU time 30.77 seconds
Started Jun 24 04:54:32 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 203376 kb
Host smart-3c458a20-3107-43b4-b799-128a4e1ac071
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2757959397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2757959397
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.901275516
Short name T553
Test name
Test status
Simulation time 31939003 ps
CPU time 1.82 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:54:26 PM PDT 24
Peak memory 203340 kb
Host smart-6cb1c538-3558-434c-906b-35839417a32f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901275516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.901275516
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3285722624
Short name T420
Test name
Test status
Simulation time 432874154 ps
CPU time 55.78 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 206540 kb
Host smart-477d37f5-8f6e-49c0-9a48-dfb4f8c5feb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3285722624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3285722624
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1269163052
Short name T10
Test name
Test status
Simulation time 1957051474 ps
CPU time 39.31 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 204436 kb
Host smart-121e4295-647d-437c-ae75-c980d609f193
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1269163052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1269163052
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.850841420
Short name T702
Test name
Test status
Simulation time 1732771534 ps
CPU time 179.92 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:57:32 PM PDT 24
Peak memory 210228 kb
Host smart-fb0bd3eb-5328-431e-8432-a08e53f2ea96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=850841420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand
_reset.850841420
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.240632786
Short name T342
Test name
Test status
Simulation time 404024957 ps
CPU time 118.8 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:56:58 PM PDT 24
Peak memory 210332 kb
Host smart-6ed35f7f-ca24-4164-bd81-e1f76e228199
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=240632786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res
et_error.240632786
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.748072838
Short name T82
Test name
Test status
Simulation time 650792321 ps
CPU time 20.25 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 211596 kb
Host smart-30b9ae9b-ba36-4134-9d8a-b4ccfd8b5ba7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748072838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.748072838
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.903852687
Short name T146
Test name
Test status
Simulation time 412559411 ps
CPU time 9.14 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 203396 kb
Host smart-30bfc3b5-c735-4532-ab9d-665286a4fe3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903852687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.903852687
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1192663539
Short name T79
Test name
Test status
Simulation time 146216490841 ps
CPU time 587.58 seconds
Started Jun 24 04:54:24 PM PDT 24
Finished Jun 24 05:04:15 PM PDT 24
Peak memory 211564 kb
Host smart-79b30233-0e11-4b7f-acfb-67eba942d523
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1192663539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1192663539
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1584697041
Short name T470
Test name
Test status
Simulation time 320744150 ps
CPU time 8.48 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 203336 kb
Host smart-14ba6cf4-1318-434a-bf94-187e3c88021c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1584697041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1584697041
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.2575153654
Short name T485
Test name
Test status
Simulation time 475676795 ps
CPU time 8.51 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203340 kb
Host smart-f7422080-7e35-4238-8a3b-17718f35c2a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575153654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2575153654
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.2934581964
Short name T103
Test name
Test status
Simulation time 221044797 ps
CPU time 14.18 seconds
Started Jun 24 04:54:40 PM PDT 24
Finished Jun 24 04:55:00 PM PDT 24
Peak memory 211504 kb
Host smart-12c4cddb-c917-4f1f-97cf-2aaac1abf69d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2934581964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2934581964
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.4185603263
Short name T500
Test name
Test status
Simulation time 48306413492 ps
CPU time 118.95 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:56:49 PM PDT 24
Peak memory 211640 kb
Host smart-34702249-942e-4aa8-8b3e-9ae443533db1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185603263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4185603263
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3202515995
Short name T621
Test name
Test status
Simulation time 34598453308 ps
CPU time 76.72 seconds
Started Jun 24 04:54:23 PM PDT 24
Finished Jun 24 04:55:42 PM PDT 24
Peak memory 211652 kb
Host smart-62b24f3e-d9ea-4f5f-87c9-18ff7a63ae21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3202515995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3202515995
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1668943086
Short name T327
Test name
Test status
Simulation time 116667394 ps
CPU time 12.19 seconds
Started Jun 24 04:54:40 PM PDT 24
Finished Jun 24 04:54:58 PM PDT 24
Peak memory 211508 kb
Host smart-4336a7fe-2247-4004-b545-a9899d315faf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668943086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1668943086
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.2344386446
Short name T70
Test name
Test status
Simulation time 2064787017 ps
CPU time 35.27 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 203404 kb
Host smart-47eca43f-a619-4c62-9b0a-480cc327a4ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2344386446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2344386446
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.68152816
Short name T777
Test name
Test status
Simulation time 69289982 ps
CPU time 2.42 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:54:31 PM PDT 24
Peak memory 203312 kb
Host smart-03336d52-1c6b-4f72-a48a-8bb5c05af0b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68152816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.68152816
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3551282717
Short name T377
Test name
Test status
Simulation time 10321630519 ps
CPU time 25.87 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 203440 kb
Host smart-662caac8-8f2a-4da8-8d2c-bbd069f14a69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551282717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3551282717
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2407501709
Short name T231
Test name
Test status
Simulation time 4382400683 ps
CPU time 31.14 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203340 kb
Host smart-ecfcdfa8-2fe5-4543-9025-d491ce95f8d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2407501709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2407501709
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2791072074
Short name T149
Test name
Test status
Simulation time 38199285 ps
CPU time 2.26 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:54:50 PM PDT 24
Peak memory 203376 kb
Host smart-5ba68c6e-73e6-4633-82f9-649b6f72bd44
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791072074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2791072074
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4114202268
Short name T221
Test name
Test status
Simulation time 1070751155 ps
CPU time 128.18 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:56:41 PM PDT 24
Peak memory 205848 kb
Host smart-69dece01-5dde-403a-aac8-37e285970220
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4114202268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4114202268
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2501741684
Short name T9
Test name
Test status
Simulation time 6398663435 ps
CPU time 174.57 seconds
Started Jun 24 04:54:48 PM PDT 24
Finished Jun 24 04:57:50 PM PDT 24
Peak memory 206212 kb
Host smart-c061ff14-8160-4d87-b8cb-dbdd86ac25a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2501741684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2501741684
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4055360407
Short name T341
Test name
Test status
Simulation time 5952165589 ps
CPU time 664.61 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 05:05:46 PM PDT 24
Peak memory 226224 kb
Host smart-97138d6b-da43-4871-bf05-cfeffb964d94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4055360407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.4055360407
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4289355584
Short name T552
Test name
Test status
Simulation time 818352362 ps
CPU time 152 seconds
Started Jun 24 04:54:32 PM PDT 24
Finished Jun 24 04:57:08 PM PDT 24
Peak memory 210484 kb
Host smart-3c9762be-0a2e-403a-8686-1b01dd3b3744
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4289355584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.4289355584
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1427292022
Short name T160
Test name
Test status
Simulation time 63998976 ps
CPU time 9.26 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 211512 kb
Host smart-2f322209-595c-4f36-87bd-0512e73e97fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1427292022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1427292022
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3360285849
Short name T219
Test name
Test status
Simulation time 299828317 ps
CPU time 37.11 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:55:27 PM PDT 24
Peak memory 211768 kb
Host smart-bdf8bb89-66d1-4d75-8164-517cdbb4885e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3360285849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3360285849
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3486367250
Short name T224
Test name
Test status
Simulation time 52942821219 ps
CPU time 399.26 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 05:01:18 PM PDT 24
Peak memory 211632 kb
Host smart-b2ba5e78-23bd-4cf4-a5e4-6ec9cfc04496
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3486367250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3486367250
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.270786849
Short name T608
Test name
Test status
Simulation time 91641214 ps
CPU time 3.71 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 04:54:43 PM PDT 24
Peak memory 203412 kb
Host smart-62cf5cfc-fe59-4360-98fe-309c7443f9cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=270786849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.270786849
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.27866524
Short name T796
Test name
Test status
Simulation time 1084583423 ps
CPU time 11.83 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:54:40 PM PDT 24
Peak memory 203332 kb
Host smart-39ae5d7c-e8be-41da-b8bb-d357a65972b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27866524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.27866524
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.1801118819
Short name T481
Test name
Test status
Simulation time 357990645 ps
CPU time 10.59 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 204484 kb
Host smart-2f7ae5b9-c24b-4fc1-8765-6b0d59f728eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1801118819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1801118819
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2565803436
Short name T320
Test name
Test status
Simulation time 5499388950 ps
CPU time 20.48 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203488 kb
Host smart-4169b44b-b177-4460-aab7-2e1f38156781
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565803436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2565803436
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1451253082
Short name T431
Test name
Test status
Simulation time 46052629847 ps
CPU time 209.81 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:58:02 PM PDT 24
Peak memory 205172 kb
Host smart-6e85fcff-ebf7-4baa-8d8e-6eefa13f3b0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1451253082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1451253082
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.44982338
Short name T477
Test name
Test status
Simulation time 112581699 ps
CPU time 16.03 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 211576 kb
Host smart-b6796766-fae2-45d8-91f0-234491c9cb13
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44982338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.44982338
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.3253951610
Short name T468
Test name
Test status
Simulation time 211614037 ps
CPU time 13.9 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:54:56 PM PDT 24
Peak memory 203636 kb
Host smart-a9e95ae6-f063-4348-90d5-879652b6afb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3253951610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3253951610
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.2883344536
Short name T841
Test name
Test status
Simulation time 147063100 ps
CPU time 3.23 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:54:52 PM PDT 24
Peak memory 203392 kb
Host smart-538a073f-d507-41a4-b640-a18bbdb84856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2883344536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2883344536
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.4008494946
Short name T452
Test name
Test status
Simulation time 7096154392 ps
CPU time 40.54 seconds
Started Jun 24 04:54:24 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 203464 kb
Host smart-e9f492da-f063-48b7-8dc2-8a90f4947182
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008494946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.4008494946
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3867803414
Short name T781
Test name
Test status
Simulation time 7725466380 ps
CPU time 37.06 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:55:09 PM PDT 24
Peak memory 203384 kb
Host smart-0b994365-7212-4979-bde1-7c8a315331d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3867803414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3867803414
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.184577365
Short name T891
Test name
Test status
Simulation time 44142804 ps
CPU time 2.56 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:54:54 PM PDT 24
Peak memory 203392 kb
Host smart-3f20dfe1-c493-49ca-adf6-882a30a9bdd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184577365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.184577365
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.669653255
Short name T340
Test name
Test status
Simulation time 7092880564 ps
CPU time 193.53 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:58:02 PM PDT 24
Peak memory 210832 kb
Host smart-d6340acd-ea22-4863-abc3-7c68f7b905c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=669653255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.669653255
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.354193097
Short name T768
Test name
Test status
Simulation time 861224047 ps
CPU time 13.5 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:47 PM PDT 24
Peak memory 203388 kb
Host smart-2364bb4d-025e-4094-81c9-47c31c147581
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=354193097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.354193097
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1318268346
Short name T93
Test name
Test status
Simulation time 13949203751 ps
CPU time 451.47 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 05:02:01 PM PDT 24
Peak memory 208600 kb
Host smart-0c63f3d6-c96a-4ea7-aba7-e8d07d55b808
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1318268346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.1318268346
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3488431959
Short name T556
Test name
Test status
Simulation time 688869825 ps
CPU time 166.73 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:57:15 PM PDT 24
Peak memory 211388 kb
Host smart-5f5b6cb6-8704-48e5-908d-879b9938e162
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3488431959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.3488431959
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1257288226
Short name T140
Test name
Test status
Simulation time 128845681 ps
CPU time 10.57 seconds
Started Jun 24 04:54:26 PM PDT 24
Finished Jun 24 04:54:40 PM PDT 24
Peak memory 211508 kb
Host smart-a7f4288b-a3cb-425f-b2fa-83b67862b9c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1257288226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1257288226
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3719030377
Short name T83
Test name
Test status
Simulation time 1785928935 ps
CPU time 63.91 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:55:53 PM PDT 24
Peak memory 206196 kb
Host smart-e6d510ba-2799-45cc-b297-615ebeb86197
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3719030377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3719030377
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2530083258
Short name T198
Test name
Test status
Simulation time 36812946558 ps
CPU time 209.41 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:58:09 PM PDT 24
Peak memory 211552 kb
Host smart-26dfdf42-afbf-453f-90bc-f3f72a9fe9ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2530083258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.2530083258
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3334754859
Short name T282
Test name
Test status
Simulation time 70116964 ps
CPU time 2.72 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:54:51 PM PDT 24
Peak memory 203412 kb
Host smart-93261aa7-1c2e-4149-a00f-b1679c686f01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3334754859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3334754859
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.1726163539
Short name T172
Test name
Test status
Simulation time 870945593 ps
CPU time 25.1 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 203416 kb
Host smart-bd8f2e1b-7f73-4412-92bb-8f5cacd4a31d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1726163539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1726163539
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.3175436059
Short name T46
Test name
Test status
Simulation time 383113311 ps
CPU time 26.66 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:10 PM PDT 24
Peak memory 211236 kb
Host smart-2c119c3f-a207-46eb-b5b6-3664299afee6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3175436059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3175436059
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1723965265
Short name T616
Test name
Test status
Simulation time 6016229616 ps
CPU time 28.66 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:55:06 PM PDT 24
Peak memory 211636 kb
Host smart-1760efad-e3c3-4d19-b6d3-2b56d2738168
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723965265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1723965265
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1597541097
Short name T228
Test name
Test status
Simulation time 46616595969 ps
CPU time 167.75 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:57:25 PM PDT 24
Peak memory 211632 kb
Host smart-394cf13a-2a2a-4646-b9e4-f1cf127e6b4b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1597541097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1597541097
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2459474976
Short name T403
Test name
Test status
Simulation time 47716812 ps
CPU time 4.5 seconds
Started Jun 24 04:54:28 PM PDT 24
Finished Jun 24 04:54:37 PM PDT 24
Peak memory 203352 kb
Host smart-fdcc6abe-15b5-4d45-8fa7-61a63dcc6681
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459474976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2459474976
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.1729126775
Short name T65
Test name
Test status
Simulation time 127163295 ps
CPU time 9.7 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 204008 kb
Host smart-db4c8ba6-afb1-4615-ad05-72a6f4c4ae5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1729126775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1729126775
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.441089809
Short name T290
Test name
Test status
Simulation time 25659994 ps
CPU time 2.16 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:54:52 PM PDT 24
Peak memory 203392 kb
Host smart-fd431aa1-9b6d-41f4-98cb-7f4bfbb32e85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=441089809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.441089809
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1474684917
Short name T345
Test name
Test status
Simulation time 21446151843 ps
CPU time 44.73 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:55:18 PM PDT 24
Peak memory 203716 kb
Host smart-df266a4e-6471-43da-8e75-13a25608179f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474684917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1474684917
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1359803096
Short name T295
Test name
Test status
Simulation time 6623555693 ps
CPU time 26.44 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:59 PM PDT 24
Peak memory 203460 kb
Host smart-5b9382ae-0820-4e50-b652-c26e6c1bd028
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1359803096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1359803096
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.272738348
Short name T822
Test name
Test status
Simulation time 42956729 ps
CPU time 1.98 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203384 kb
Host smart-7a8d5a24-6ad9-4c10-9184-8bfdc4369b15
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272738348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.272738348
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.4277482713
Short name T264
Test name
Test status
Simulation time 2030544686 ps
CPU time 42.91 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 211428 kb
Host smart-dc12a73c-54e4-40f2-a6ea-b9c65dd498b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4277482713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4277482713
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1541509202
Short name T167
Test name
Test status
Simulation time 6491186538 ps
CPU time 200.62 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:58:14 PM PDT 24
Peak memory 207052 kb
Host smart-1d31fd39-dd37-4f1a-bbd4-dbdfc2253040
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541509202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1541509202
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3897701292
Short name T387
Test name
Test status
Simulation time 7145296595 ps
CPU time 377.44 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 05:00:49 PM PDT 24
Peak memory 211612 kb
Host smart-908c52fe-db04-4b51-ba5e-554334a318c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3897701292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.3897701292
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1894806513
Short name T898
Test name
Test status
Simulation time 3564018944 ps
CPU time 256.54 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 04:58:56 PM PDT 24
Peak memory 211736 kb
Host smart-f58191fc-b9df-4af9-93eb-4e53f16b71f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1894806513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.1894806513
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3182513845
Short name T379
Test name
Test status
Simulation time 52467434 ps
CPU time 5.28 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 211584 kb
Host smart-026a8ed2-b751-4eba-b028-a62343ac12e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3182513845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3182513845
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1466714278
Short name T549
Test name
Test status
Simulation time 738527814 ps
CPU time 28.1 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 211308 kb
Host smart-a6296e0a-8cb8-4e91-b0bb-44b6e35b58ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1466714278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1466714278
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3883099844
Short name T366
Test name
Test status
Simulation time 26569600266 ps
CPU time 160.28 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:57:18 PM PDT 24
Peak memory 211652 kb
Host smart-2dd5539d-ff27-4a47-9ac0-b26fd3c2b2df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3883099844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.3883099844
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3025522913
Short name T482
Test name
Test status
Simulation time 110499778 ps
CPU time 5.29 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 203404 kb
Host smart-7f64a6db-435e-4a74-8ba3-5d5d9ca51b92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3025522913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3025522913
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.1330627151
Short name T900
Test name
Test status
Simulation time 3446591435 ps
CPU time 38.35 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 203484 kb
Host smart-a033e094-a285-4e78-a9ac-8ed289451b88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1330627151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1330627151
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3663084643
Short name T171
Test name
Test status
Simulation time 39256230013 ps
CPU time 225.9 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:58:36 PM PDT 24
Peak memory 211668 kb
Host smart-980d6593-8f8f-4f36-b0cd-c36c8099229a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663084643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3663084643
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2689046750
Short name T127
Test name
Test status
Simulation time 88651388344 ps
CPU time 141.47 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:56:49 PM PDT 24
Peak memory 211552 kb
Host smart-6bd101ce-6a6b-40fc-b794-af5b9cea4414
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2689046750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2689046750
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.161352378
Short name T162
Test name
Test status
Simulation time 230515271 ps
CPU time 29.78 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:55:20 PM PDT 24
Peak memory 211568 kb
Host smart-39844d69-28b6-441c-8082-4024c5805b34
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161352378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.161352378
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3753469621
Short name T507
Test name
Test status
Simulation time 434661636 ps
CPU time 5.97 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:54:44 PM PDT 24
Peak memory 203420 kb
Host smart-0072cca5-9af2-42ea-89b0-b179c44e82ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3753469621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3753469621
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.134255111
Short name T357
Test name
Test status
Simulation time 117030770 ps
CPU time 3.52 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:54:38 PM PDT 24
Peak memory 203340 kb
Host smart-2284b8c9-d893-479c-b46e-e71ce0f177c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=134255111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.134255111
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1653352670
Short name T741
Test name
Test status
Simulation time 38642443636 ps
CPU time 59.23 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:55:33 PM PDT 24
Peak memory 203464 kb
Host smart-c394289f-9206-4848-a449-ad94b0d5a11b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653352670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1653352670
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2281613825
Short name T555
Test name
Test status
Simulation time 20431694302 ps
CPU time 45.35 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 203412 kb
Host smart-763480fc-21a3-4e39-867e-bf904dfcb17d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2281613825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2281613825
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3746475752
Short name T872
Test name
Test status
Simulation time 81512121 ps
CPU time 1.94 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 203396 kb
Host smart-e1c548f8-6a1a-4b46-9d64-0ca646b38cd5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746475752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3746475752
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1903195952
Short name T441
Test name
Test status
Simulation time 988412573 ps
CPU time 85.11 seconds
Started Jun 24 04:54:46 PM PDT 24
Finished Jun 24 04:56:19 PM PDT 24
Peak memory 207120 kb
Host smart-c78e166a-32e2-4739-95f9-6bb1e9fe68d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1903195952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1903195952
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1511318030
Short name T666
Test name
Test status
Simulation time 875043278 ps
CPU time 36 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:55:31 PM PDT 24
Peak memory 204984 kb
Host smart-556e413e-638c-4b55-8be3-f94748eacf74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1511318030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1511318030
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2495798790
Short name T610
Test name
Test status
Simulation time 107033530 ps
CPU time 23.87 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 206792 kb
Host smart-f186c1b4-d7f0-46b9-abf9-685c1d45157f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2495798790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.2495798790
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3905320664
Short name T543
Test name
Test status
Simulation time 101981070 ps
CPU time 9.46 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:54:53 PM PDT 24
Peak memory 203408 kb
Host smart-feacdf5f-26ca-4f1f-9f68-aaa366aa35a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3905320664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3905320664
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1507956267
Short name T821
Test name
Test status
Simulation time 92109503 ps
CPU time 17.1 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 211484 kb
Host smart-5a5a5034-49d7-4b7b-8715-96f1aa5c3777
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1507956267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1507956267
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1736511724
Short name T505
Test name
Test status
Simulation time 121641901 ps
CPU time 14.22 seconds
Started Jun 24 04:54:58 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 204484 kb
Host smart-aab099d3-1c43-44d3-b8f0-8b4129e7ead4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1736511724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1736511724
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1798597368
Short name T847
Test name
Test status
Simulation time 6610952094 ps
CPU time 43.14 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:55:11 PM PDT 24
Peak memory 211540 kb
Host smart-aa93a7cb-d608-4092-a466-4987b3643598
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1798597368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.1798597368
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.434861419
Short name T433
Test name
Test status
Simulation time 263763482 ps
CPU time 8.71 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203648 kb
Host smart-4886ad81-6bce-485f-ad13-8be46787241b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=434861419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.434861419
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.828275612
Short name T462
Test name
Test status
Simulation time 297552478 ps
CPU time 24.67 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:08 PM PDT 24
Peak memory 203320 kb
Host smart-a3076948-8a7b-4ff2-8113-4106eee05b3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=828275612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.828275612
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.485433889
Short name T820
Test name
Test status
Simulation time 655872351 ps
CPU time 21.04 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 211592 kb
Host smart-d35b1bea-646c-4a32-90bb-10d6a315e633
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485433889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.485433889
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.717781137
Short name T183
Test name
Test status
Simulation time 43325158977 ps
CPU time 212.65 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:58:26 PM PDT 24
Peak memory 205208 kb
Host smart-4179619e-8285-4ae7-b7ce-10df5931a648
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=717781137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.717781137
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3236644595
Short name T36
Test name
Test status
Simulation time 21836823379 ps
CPU time 158.65 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:57:27 PM PDT 24
Peak memory 211656 kb
Host smart-8bf2c3a0-67a2-489d-bf73-58fd5d3b219b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3236644595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3236644595
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2096825819
Short name T828
Test name
Test status
Simulation time 140754918 ps
CPU time 19.71 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:55:10 PM PDT 24
Peak memory 204516 kb
Host smart-c2cd2d36-ec59-4d37-b54e-1e722ce02f54
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096825819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2096825819
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.513601528
Short name T823
Test name
Test status
Simulation time 1259337873 ps
CPU time 28.59 seconds
Started Jun 24 04:54:46 PM PDT 24
Finished Jun 24 04:55:22 PM PDT 24
Peak memory 203468 kb
Host smart-76718f70-b93a-48c3-973a-77c41c32789d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=513601528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.513601528
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2288654248
Short name T767
Test name
Test status
Simulation time 137146750 ps
CPU time 3.63 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 203396 kb
Host smart-444a01bb-8cea-4531-ad23-e84717d3affe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2288654248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2288654248
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3737351494
Short name T206
Test name
Test status
Simulation time 5906588329 ps
CPU time 35.32 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203456 kb
Host smart-ee4e238f-0907-4b20-9ffb-cf9f7502005f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737351494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3737351494
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3019668484
Short name T43
Test name
Test status
Simulation time 3646905181 ps
CPU time 22.94 seconds
Started Jun 24 04:54:48 PM PDT 24
Finished Jun 24 04:55:20 PM PDT 24
Peak memory 203456 kb
Host smart-01825ac0-68cf-43e0-b440-a226a17f4d99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3019668484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3019668484
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.4087905976
Short name T449
Test name
Test status
Simulation time 26144009 ps
CPU time 2.14 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:54:44 PM PDT 24
Peak memory 203388 kb
Host smart-85919c77-555d-492d-93ca-08c9928b47a3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087905976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.4087905976
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.243459786
Short name T548
Test name
Test status
Simulation time 1097712243 ps
CPU time 101.01 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:56:25 PM PDT 24
Peak memory 206704 kb
Host smart-8e85732d-7760-41f5-9cce-cc7ce1b0ad81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=243459786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.243459786
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.913492949
Short name T735
Test name
Test status
Simulation time 2105534276 ps
CPU time 99.66 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:56:31 PM PDT 24
Peak memory 206136 kb
Host smart-62fdc34e-099e-4e6a-90a7-370e89aacfa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=913492949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.913492949
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3372057746
Short name T215
Test name
Test status
Simulation time 2938519582 ps
CPU time 423.16 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 05:01:54 PM PDT 24
Peak memory 211436 kb
Host smart-d2c01ba7-8e1d-416d-854c-139cc23bbbfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3372057746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.3372057746
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1449577307
Short name T213
Test name
Test status
Simulation time 289700178 ps
CPU time 68.12 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:55:50 PM PDT 24
Peak memory 208572 kb
Host smart-f981774a-4949-47c9-bef7-a77e809fcba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449577307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1449577307
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.64690141
Short name T574
Test name
Test status
Simulation time 19154057 ps
CPU time 3.17 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 04:55:00 PM PDT 24
Peak memory 211488 kb
Host smart-7116a7c3-bbe5-4b0d-acb7-65074612276f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64690141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.64690141
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.992662930
Short name T258
Test name
Test status
Simulation time 183594475 ps
CPU time 6.98 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:15 PM PDT 24
Peak memory 203640 kb
Host smart-1acfde04-60e3-4b0f-b033-83292dbd3408
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=992662930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.992662930
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2120110269
Short name T128
Test name
Test status
Simulation time 141726447137 ps
CPU time 720.13 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 05:06:16 PM PDT 24
Peak memory 211624 kb
Host smart-fbaa41a8-b3e3-4a9e-b86b-240c5cb7a709
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2120110269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.2120110269
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1933344672
Short name T314
Test name
Test status
Simulation time 778801705 ps
CPU time 17.46 seconds
Started Jun 24 04:54:02 PM PDT 24
Finished Jun 24 04:54:25 PM PDT 24
Peak memory 203372 kb
Host smart-248a3441-c922-4b92-9811-24bcbc98e515
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1933344672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1933344672
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.1623554269
Short name T726
Test name
Test status
Simulation time 223790459 ps
CPU time 21.88 seconds
Started Jun 24 04:53:59 PM PDT 24
Finished Jun 24 04:54:26 PM PDT 24
Peak memory 203420 kb
Host smart-60be5a18-c595-4bf0-94ab-fcd385893bd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1623554269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1623554269
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.2754750212
Short name T250
Test name
Test status
Simulation time 73304411 ps
CPU time 4.23 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:54:17 PM PDT 24
Peak memory 204132 kb
Host smart-9f92add4-d83a-47ba-9694-635f3d7a983b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2754750212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2754750212
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.414956609
Short name T185
Test name
Test status
Simulation time 150095301917 ps
CPU time 305.19 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:59:11 PM PDT 24
Peak memory 211556 kb
Host smart-7f5c48a1-dc42-4b2a-b864-40520c3003a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=414956609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.414956609
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3187768537
Short name T106
Test name
Test status
Simulation time 66824652934 ps
CPU time 198.94 seconds
Started Jun 24 04:54:15 PM PDT 24
Finished Jun 24 04:57:38 PM PDT 24
Peak memory 211624 kb
Host smart-6d3c440a-f2b5-4756-8cbf-72c603a41548
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3187768537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3187768537
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.560326877
Short name T490
Test name
Test status
Simulation time 808081545 ps
CPU time 16.88 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:24 PM PDT 24
Peak memory 204976 kb
Host smart-efaf0039-5e06-4293-9170-42b41f4d67f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560326877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.560326877
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.3875701857
Short name T475
Test name
Test status
Simulation time 167537583 ps
CPU time 10.28 seconds
Started Jun 24 04:54:02 PM PDT 24
Finished Jun 24 04:54:17 PM PDT 24
Peak memory 203380 kb
Host smart-e61674db-ed25-4e1a-a5f3-c1d9db051ec8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3875701857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3875701857
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.1913579399
Short name T329
Test name
Test status
Simulation time 241137224 ps
CPU time 3.64 seconds
Started Jun 24 04:54:05 PM PDT 24
Finished Jun 24 04:54:14 PM PDT 24
Peak memory 203328 kb
Host smart-48948fdb-c0fd-44a9-b8cb-ec58bb7aaebb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1913579399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1913579399
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.938768534
Short name T539
Test name
Test status
Simulation time 11327893957 ps
CPU time 36.43 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 203448 kb
Host smart-c804a506-1627-4d61-a586-0a2e7615b8ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=938768534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.938768534
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.548207648
Short name T599
Test name
Test status
Simulation time 11068468531 ps
CPU time 37.46 seconds
Started Jun 24 04:53:58 PM PDT 24
Finished Jun 24 04:54:40 PM PDT 24
Peak memory 203372 kb
Host smart-0e52f91a-5c73-4113-a6be-b7c9ae5bece4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=548207648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.548207648
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3770640502
Short name T355
Test name
Test status
Simulation time 124027743 ps
CPU time 2.25 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 203304 kb
Host smart-1aa496c3-437d-4292-8028-e50c99c92ed4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770640502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3770640502
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3706773513
Short name T208
Test name
Test status
Simulation time 1126850306 ps
CPU time 77.87 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 207408 kb
Host smart-9ef8a4cf-66d3-4940-81ce-05c3837c9571
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3706773513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3706773513
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3694768140
Short name T679
Test name
Test status
Simulation time 1198783245 ps
CPU time 29.78 seconds
Started Jun 24 04:54:07 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 204572 kb
Host smart-4f7fb232-8911-4539-b3c3-e0226f42cf83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3694768140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3694768140
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3286376890
Short name T744
Test name
Test status
Simulation time 6188523962 ps
CPU time 467.21 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 05:02:06 PM PDT 24
Peak memory 209944 kb
Host smart-b9e58240-c5bc-4a7f-be17-0ee774bab049
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3286376890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.3286376890
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1468429072
Short name T21
Test name
Test status
Simulation time 2136473335 ps
CPU time 286.83 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:59:03 PM PDT 24
Peak memory 211224 kb
Host smart-f38f3986-974b-4260-ad91-1ba30b7dcf37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468429072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.1468429072
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.372457145
Short name T305
Test name
Test status
Simulation time 109835497 ps
CPU time 4.2 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:54:27 PM PDT 24
Peak memory 211568 kb
Host smart-2a49b0bc-5113-4e17-a543-c209a913369e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=372457145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.372457145
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1673455276
Short name T632
Test name
Test status
Simulation time 3508152496 ps
CPU time 45.98 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:55:28 PM PDT 24
Peak memory 211568 kb
Host smart-f2411658-c376-4319-9004-551ef45f157e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1673455276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1673455276
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3266502858
Short name T557
Test name
Test status
Simulation time 9841493211 ps
CPU time 91.41 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:56:21 PM PDT 24
Peak memory 211652 kb
Host smart-56dfac50-eee1-4d70-8241-5046e1a69239
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3266502858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3266502858
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3922464244
Short name T212
Test name
Test status
Simulation time 726666815 ps
CPU time 11.67 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:55:11 PM PDT 24
Peak memory 203408 kb
Host smart-0260409d-61ad-44eb-9a5d-d84eb40c1f29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3922464244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3922464244
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.566490636
Short name T887
Test name
Test status
Simulation time 306818059 ps
CPU time 20.51 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:55:09 PM PDT 24
Peak memory 203440 kb
Host smart-16da7185-6931-4651-8498-b4f0e5422c06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=566490636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.566490636
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.2788171409
Short name T765
Test name
Test status
Simulation time 196561799 ps
CPU time 24.85 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:55:02 PM PDT 24
Peak memory 211524 kb
Host smart-09efc79a-2406-42c9-9237-3e7faaa32eac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2788171409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2788171409
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4288095862
Short name T863
Test name
Test status
Simulation time 40133702646 ps
CPU time 122.64 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:56:45 PM PDT 24
Peak memory 211580 kb
Host smart-7afc2466-dbb1-43f8-a185-89ad2b111b8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288095862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4288095862
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.253876651
Short name T642
Test name
Test status
Simulation time 1189816873 ps
CPU time 10.92 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 04:54:53 PM PDT 24
Peak memory 203340 kb
Host smart-637ce62a-7425-4ce1-8d3b-78064430e30a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=253876651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.253876651
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.841466888
Short name T388
Test name
Test status
Simulation time 218798987 ps
CPU time 16.06 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:54:57 PM PDT 24
Peak memory 204572 kb
Host smart-a25021c0-a015-4438-beeb-cf1ae88cca96
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841466888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.841466888
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.4061555141
Short name T524
Test name
Test status
Simulation time 228296453 ps
CPU time 9.02 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 203968 kb
Host smart-fae509fe-0c69-4a18-8b6f-3db6ec053662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4061555141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.4061555141
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.3223509606
Short name T662
Test name
Test status
Simulation time 121672889 ps
CPU time 3.4 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:54:47 PM PDT 24
Peak memory 203336 kb
Host smart-e9d85984-4dbd-4b1a-be3a-fa3a9ef78026
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3223509606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3223509606
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2399761649
Short name T495
Test name
Test status
Simulation time 9610449291 ps
CPU time 29.84 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 04:55:27 PM PDT 24
Peak memory 203464 kb
Host smart-b9039098-5dd6-4201-8d45-17b85aad2e52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399761649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2399761649
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2000515211
Short name T671
Test name
Test status
Simulation time 13044136519 ps
CPU time 39.43 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:55:34 PM PDT 24
Peak memory 203440 kb
Host smart-be669057-6afc-4918-a17a-e7579165d725
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2000515211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2000515211
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1709258732
Short name T628
Test name
Test status
Simulation time 55041485 ps
CPU time 2.24 seconds
Started Jun 24 04:54:48 PM PDT 24
Finished Jun 24 04:54:58 PM PDT 24
Peak memory 203384 kb
Host smart-c8457046-689a-4a44-b4de-7410cfdaa079
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709258732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1709258732
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3217983824
Short name T363
Test name
Test status
Simulation time 1627575286 ps
CPU time 111.5 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 04:56:30 PM PDT 24
Peak memory 208172 kb
Host smart-583c2159-6162-4ce1-a812-02ecbf241e1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3217983824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3217983824
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1742383616
Short name T584
Test name
Test status
Simulation time 1561762144 ps
CPU time 114.3 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:56:52 PM PDT 24
Peak memory 207440 kb
Host smart-9f61a58a-bb14-4e93-bee7-73be0a824f41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1742383616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1742383616
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.362043729
Short name T812
Test name
Test status
Simulation time 4832735854 ps
CPU time 379.03 seconds
Started Jun 24 04:54:38 PM PDT 24
Finished Jun 24 05:01:01 PM PDT 24
Peak memory 211444 kb
Host smart-6a15e34f-614a-462e-8868-14cde4f9e14a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=362043729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.362043729
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.754012463
Short name T681
Test name
Test status
Simulation time 110365445 ps
CPU time 16.97 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:54:57 PM PDT 24
Peak memory 211596 kb
Host smart-08904ef1-98b9-40b8-9f9f-92010a271857
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=754012463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.754012463
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2178590484
Short name T204
Test name
Test status
Simulation time 268371915 ps
CPU time 34.75 seconds
Started Jun 24 04:54:46 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 205072 kb
Host smart-bc96b313-6e52-4ddc-8ffc-d584b9e6bf2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2178590484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2178590484
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1308328251
Short name T846
Test name
Test status
Simulation time 43986375293 ps
CPU time 244.66 seconds
Started Jun 24 04:54:46 PM PDT 24
Finished Jun 24 04:58:59 PM PDT 24
Peak memory 211652 kb
Host smart-7720ef22-06d6-44e6-b303-eca70aff884e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1308328251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.1308328251
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2693091739
Short name T747
Test name
Test status
Simulation time 548227619 ps
CPU time 12.18 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 203936 kb
Host smart-cecb8209-a8d4-4577-9f2c-a1accf4cdae0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2693091739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2693091739
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.529782967
Short name T247
Test name
Test status
Simulation time 458010890 ps
CPU time 15.81 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203428 kb
Host smart-9d05f642-9a23-4a43-a5b7-3e5dc3295f19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=529782967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.529782967
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.58212086
Short name T794
Test name
Test status
Simulation time 122320412 ps
CPU time 19.67 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 211576 kb
Host smart-c4420ead-60fd-4e70-b52e-bc6082fc9fa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58212086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.58212086
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1748060339
Short name T799
Test name
Test status
Simulation time 49103940940 ps
CPU time 223.46 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:58:42 PM PDT 24
Peak memory 211540 kb
Host smart-eac689f7-863c-435d-9fff-189fb18f437a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748060339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1748060339
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1942129069
Short name T774
Test name
Test status
Simulation time 37868932457 ps
CPU time 227.6 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:58:28 PM PDT 24
Peak memory 204648 kb
Host smart-f7b1b747-1169-4bad-97d7-575cf3a980ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1942129069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1942129069
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3353794727
Short name T877
Test name
Test status
Simulation time 304103241 ps
CPU time 8.23 seconds
Started Jun 24 04:54:59 PM PDT 24
Finished Jun 24 04:55:11 PM PDT 24
Peak memory 211556 kb
Host smart-f1ef7b90-da69-4e79-a0d2-8e0f31d9454a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353794727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3353794727
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2290821068
Short name T272
Test name
Test status
Simulation time 737638633 ps
CPU time 5.96 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:54:54 PM PDT 24
Peak memory 203416 kb
Host smart-85b8732a-bd32-452e-9162-14ab244f356a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2290821068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2290821068
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.378038176
Short name T259
Test name
Test status
Simulation time 160728038 ps
CPU time 3.3 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:54:46 PM PDT 24
Peak memory 203324 kb
Host smart-f851e574-7beb-4708-894e-7a0e6fd61b31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=378038176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.378038176
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2564937267
Short name T607
Test name
Test status
Simulation time 17117284170 ps
CPU time 31.96 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 203472 kb
Host smart-b4530528-01dc-4777-8a5f-9ccf8b8a716f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564937267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2564937267
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3275272289
Short name T844
Test name
Test status
Simulation time 4219087687 ps
CPU time 34.98 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:55:26 PM PDT 24
Peak memory 203380 kb
Host smart-e153409d-815c-4c97-8be9-b43a737a4ec3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3275272289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3275272289
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.87586092
Short name T687
Test name
Test status
Simulation time 32408686 ps
CPU time 2.28 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:54:55 PM PDT 24
Peak memory 203304 kb
Host smart-feeb8ecf-8693-4695-ad6f-2eb3aa0beeb6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87586092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.87586092
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.377195482
Short name T562
Test name
Test status
Simulation time 13069334491 ps
CPU time 261.2 seconds
Started Jun 24 04:54:46 PM PDT 24
Finished Jun 24 04:59:16 PM PDT 24
Peak memory 211604 kb
Host smart-d548ca8f-047d-4d3f-839a-23e6f0c96cfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=377195482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.377195482
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.349083434
Short name T842
Test name
Test status
Simulation time 591879808 ps
CPU time 216.43 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:58:20 PM PDT 24
Peak memory 209772 kb
Host smart-d285f89d-1d16-4c33-a84a-d91885ba7f55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=349083434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand
_reset.349083434
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2902488846
Short name T211
Test name
Test status
Simulation time 1918882860 ps
CPU time 187.36 seconds
Started Jun 24 04:54:33 PM PDT 24
Finished Jun 24 04:57:44 PM PDT 24
Peak memory 211468 kb
Host smart-11d88ed8-dade-407e-933f-2dafcee155a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2902488846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.2902488846
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3664465684
Short name T181
Test name
Test status
Simulation time 1926999065 ps
CPU time 14.1 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 211596 kb
Host smart-8390adfa-fdef-4a08-a472-a07231bb22eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3664465684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3664465684
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2152609667
Short name T210
Test name
Test status
Simulation time 190854011 ps
CPU time 26.64 seconds
Started Jun 24 04:54:59 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 211604 kb
Host smart-649e785a-5d9d-4323-9a9d-60d009d8e8ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2152609667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2152609667
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3779310
Short name T795
Test name
Test status
Simulation time 5916931161 ps
CPU time 31.6 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:55:31 PM PDT 24
Peak memory 211652 kb
Host smart-81ea71af-d27f-412e-9ff3-1c764179e548
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3779310
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.3571921169
Short name T806
Test name
Test status
Simulation time 73423356 ps
CPU time 5.48 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:54:57 PM PDT 24
Peak memory 203296 kb
Host smart-cc76be4c-64ac-45a3-8c1d-ef6e4c43d99f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3571921169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3571921169
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.1769032297
Short name T384
Test name
Test status
Simulation time 392114027 ps
CPU time 15.63 seconds
Started Jun 24 04:54:56 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 204524 kb
Host smart-ecd2b3f5-0d13-4ba9-9f3a-4d3622bffaf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1769032297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1769032297
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2645917169
Short name T234
Test name
Test status
Simulation time 17616378512 ps
CPU time 105.62 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:56:25 PM PDT 24
Peak memory 211540 kb
Host smart-d7c8ee57-d062-4c82-8122-d1656470e3a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645917169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2645917169
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3345360074
Short name T165
Test name
Test status
Simulation time 12778505713 ps
CPU time 83.24 seconds
Started Jun 24 04:54:52 PM PDT 24
Finished Jun 24 04:56:22 PM PDT 24
Peak memory 211636 kb
Host smart-9b6cfa00-afa8-4ade-b918-b813a4608eda
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3345360074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3345360074
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.964552675
Short name T713
Test name
Test status
Simulation time 254994937 ps
CPU time 26.66 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 211504 kb
Host smart-2c8ce552-496c-4be0-97cc-4f350a1bc68f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964552675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.964552675
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.1877152596
Short name T255
Test name
Test status
Simulation time 2696647861 ps
CPU time 19.26 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 204272 kb
Host smart-57284c82-69f9-4baa-8944-accb0e0e864b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1877152596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1877152596
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.1795906169
Short name T400
Test name
Test status
Simulation time 299832440 ps
CPU time 3.63 seconds
Started Jun 24 04:54:47 PM PDT 24
Finished Jun 24 04:54:58 PM PDT 24
Peak memory 203388 kb
Host smart-486a43e8-7673-40b6-bcc2-d62831e19399
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1795906169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1795906169
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.193641408
Short name T790
Test name
Test status
Simulation time 12201101213 ps
CPU time 23.58 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203396 kb
Host smart-a9d671fb-7379-49b8-b4ba-3d8cb5c7340c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=193641408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.193641408
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2970135124
Short name T389
Test name
Test status
Simulation time 20513022713 ps
CPU time 36.87 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:55:18 PM PDT 24
Peak memory 203376 kb
Host smart-b16c6d3c-b17f-4ccc-8fdf-f92fb4e80c70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2970135124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2970135124
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3525605502
Short name T349
Test name
Test status
Simulation time 38902476 ps
CPU time 2.67 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203384 kb
Host smart-b3a6a1c8-f1f5-4490-b3ce-dbcb308e56f0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525605502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3525605502
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2709544184
Short name T289
Test name
Test status
Simulation time 3169176731 ps
CPU time 121.84 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:57:00 PM PDT 24
Peak memory 208008 kb
Host smart-1c2292c3-f419-42fe-ba5f-3c8691ccc361
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2709544184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2709544184
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.407938070
Short name T849
Test name
Test status
Simulation time 8934968398 ps
CPU time 260.23 seconds
Started Jun 24 04:54:34 PM PDT 24
Finished Jun 24 04:58:58 PM PDT 24
Peak memory 210888 kb
Host smart-83912edb-249c-47c9-bc04-5b40075e3756
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=407938070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.407938070
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1895073843
Short name T298
Test name
Test status
Simulation time 991210650 ps
CPU time 92.08 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:56:30 PM PDT 24
Peak memory 206948 kb
Host smart-95cb2506-dce1-459e-9126-907aa6f1642f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1895073843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1895073843
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.4048164718
Short name T442
Test name
Test status
Simulation time 1641185677 ps
CPU time 321.75 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 05:00:18 PM PDT 24
Peak memory 219812 kb
Host smart-a57447d6-9a01-478a-a342-8da33b7d1a9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048164718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.4048164718
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3467790422
Short name T361
Test name
Test status
Simulation time 48020199 ps
CPU time 7.26 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:55:05 PM PDT 24
Peak memory 211596 kb
Host smart-95ffe05a-4147-4043-97b9-1a23d7009278
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3467790422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3467790422
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2776753003
Short name T830
Test name
Test status
Simulation time 1476319069 ps
CPU time 61.24 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 205480 kb
Host smart-fba8f2bc-bacc-4530-b211-022c53009080
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2776753003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2776753003
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1733040845
Short name T426
Test name
Test status
Simulation time 3760068250 ps
CPU time 33.88 seconds
Started Jun 24 04:54:54 PM PDT 24
Finished Jun 24 04:55:34 PM PDT 24
Peak memory 203452 kb
Host smart-88d06fb7-383d-4621-a63e-6019bf3cb457
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1733040845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.1733040845
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2991388637
Short name T649
Test name
Test status
Simulation time 34023960 ps
CPU time 4.13 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203528 kb
Host smart-ad234299-802f-42e6-b734-d66c6c3e41ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2991388637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2991388637
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.2329832292
Short name T613
Test name
Test status
Simulation time 18940211 ps
CPU time 1.97 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:55:06 PM PDT 24
Peak memory 203376 kb
Host smart-208be221-577e-403b-b26f-562a3cbcc9f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2329832292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2329832292
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.54460527
Short name T333
Test name
Test status
Simulation time 1294331420 ps
CPU time 30.43 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 211520 kb
Host smart-98947b6e-1e96-4ece-a593-73a83baebe5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54460527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.54460527
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1054205998
Short name T417
Test name
Test status
Simulation time 1997898583 ps
CPU time 13.23 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 203416 kb
Host smart-538df47f-e384-4ce2-928e-7786142299d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054205998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1054205998
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.644309163
Short name T370
Test name
Test status
Simulation time 4272609513 ps
CPU time 32.53 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:55:30 PM PDT 24
Peak memory 203492 kb
Host smart-4e55c7e9-d837-4e5e-bb41-e6c4a45692c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=644309163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.644309163
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1076774380
Short name T277
Test name
Test status
Simulation time 145604651 ps
CPU time 21.28 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 211588 kb
Host smart-b0e72bee-0abd-475d-adaa-5b7375384760
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076774380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1076774380
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.2552488045
Short name T494
Test name
Test status
Simulation time 99867892 ps
CPU time 3.23 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:55:01 PM PDT 24
Peak memory 203604 kb
Host smart-79b8e8f8-8897-45eb-a774-a7bb9fd42685
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2552488045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2552488045
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.4152391353
Short name T450
Test name
Test status
Simulation time 25148817 ps
CPU time 1.87 seconds
Started Jun 24 04:54:37 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203392 kb
Host smart-d5d19024-8df7-47b3-9f08-960556156ea7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4152391353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4152391353
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.201678615
Short name T251
Test name
Test status
Simulation time 27057629167 ps
CPU time 39.51 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 203376 kb
Host smart-bc44ef99-51ed-4ef5-8773-ba0d5f6f003d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=201678615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.201678615
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2357372050
Short name T37
Test name
Test status
Simulation time 7585885439 ps
CPU time 28.24 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 203456 kb
Host smart-1b90163a-c446-409c-9579-d0f249dc675c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2357372050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2357372050
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1388036751
Short name T756
Test name
Test status
Simulation time 59344054 ps
CPU time 2.67 seconds
Started Jun 24 04:54:43 PM PDT 24
Finished Jun 24 04:54:53 PM PDT 24
Peak memory 203388 kb
Host smart-3d07caab-b5fa-4c31-acb2-ae42cc7d54f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388036751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1388036751
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.421219484
Short name T311
Test name
Test status
Simulation time 14582436767 ps
CPU time 128.1 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:57:08 PM PDT 24
Peak memory 208088 kb
Host smart-18b8a27e-3b28-42a2-af05-3546870507a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=421219484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.421219484
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.103919234
Short name T209
Test name
Test status
Simulation time 5974449820 ps
CPU time 224.72 seconds
Started Jun 24 04:54:59 PM PDT 24
Finished Jun 24 04:58:47 PM PDT 24
Peak memory 208792 kb
Host smart-20c5c606-4110-46ae-9b13-e0c2ad1847d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103919234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand
_reset.103919234
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.700179278
Short name T653
Test name
Test status
Simulation time 215976807 ps
CPU time 8.04 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:55:15 PM PDT 24
Peak memory 205036 kb
Host smart-743b0e74-63fd-4db9-b40a-fe78f81a5854
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=700179278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.700179278
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2934324171
Short name T87
Test name
Test status
Simulation time 7539056526 ps
CPU time 42.13 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 211636 kb
Host smart-dfde76f1-320f-463e-b293-73fda881a472
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2934324171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2934324171
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2067986891
Short name T489
Test name
Test status
Simulation time 6894403283 ps
CPU time 29.48 seconds
Started Jun 24 04:54:50 PM PDT 24
Finished Jun 24 04:55:28 PM PDT 24
Peak memory 203468 kb
Host smart-422cbee5-8b51-43b9-b391-1e937a6d34e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2067986891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.2067986891
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3492566897
Short name T421
Test name
Test status
Simulation time 2476711780 ps
CPU time 21.2 seconds
Started Jun 24 04:54:59 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 204012 kb
Host smart-dd946d21-6156-4c97-947f-2738e0d2cb82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3492566897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3492566897
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.3445699612
Short name T811
Test name
Test status
Simulation time 229161113 ps
CPU time 4.15 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203280 kb
Host smart-c6a68dd7-1d23-4d7d-978e-1d806cb2813b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3445699612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3445699612
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2948937889
Short name T858
Test name
Test status
Simulation time 60894948 ps
CPU time 8.72 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:55:07 PM PDT 24
Peak memory 211484 kb
Host smart-6e69e6ff-e614-4faa-ac8c-f8f573de3bd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2948937889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2948937889
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4180501968
Short name T230
Test name
Test status
Simulation time 31645356001 ps
CPU time 200.94 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:58:10 PM PDT 24
Peak memory 211664 kb
Host smart-13a9e169-f370-4818-9f7d-9fa0e6465d69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180501968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4180501968
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3091646320
Short name T328
Test name
Test status
Simulation time 22912173976 ps
CPU time 104.68 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:56:31 PM PDT 24
Peak memory 211656 kb
Host smart-2b29c54c-e95c-40b0-a4d2-39a73854d640
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3091646320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3091646320
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2083700235
Short name T428
Test name
Test status
Simulation time 134883361 ps
CPU time 12.49 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 211480 kb
Host smart-852ff482-6bed-4ada-9735-0cf7c265e530
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083700235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2083700235
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.758678924
Short name T484
Test name
Test status
Simulation time 1922516487 ps
CPU time 24.93 seconds
Started Jun 24 04:54:59 PM PDT 24
Finished Jun 24 04:55:27 PM PDT 24
Peak memory 204224 kb
Host smart-3ccef48d-ee26-40e3-b33b-1aa53d0c26e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=758678924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.758678924
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.2636815966
Short name T397
Test name
Test status
Simulation time 423454616 ps
CPU time 3.02 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 04:55:00 PM PDT 24
Peak memory 203396 kb
Host smart-41308252-025c-4114-b406-73857a04a453
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2636815966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2636815966
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2603353337
Short name T691
Test name
Test status
Simulation time 13761307259 ps
CPU time 33.74 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 203468 kb
Host smart-0f07210d-bd3e-4d28-9c1e-87ca55b92d10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603353337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2603353337
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.846704586
Short name T445
Test name
Test status
Simulation time 10900889280 ps
CPU time 32.39 seconds
Started Jun 24 04:54:54 PM PDT 24
Finished Jun 24 04:55:33 PM PDT 24
Peak memory 203436 kb
Host smart-c0e731ff-f0d2-4393-8dfc-04de544621fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=846704586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.846704586
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1092075469
Short name T879
Test name
Test status
Simulation time 31046377 ps
CPU time 2.12 seconds
Started Jun 24 04:54:55 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 203572 kb
Host smart-7db6e730-df1d-41e0-830c-7ad49b26e9c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092075469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1092075469
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.156705942
Short name T883
Test name
Test status
Simulation time 8678795137 ps
CPU time 168.19 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:57:36 PM PDT 24
Peak memory 208104 kb
Host smart-617ed9d1-940f-4bbd-bfc7-31671a3d0c3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=156705942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.156705942
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3994656983
Short name T186
Test name
Test status
Simulation time 7611479841 ps
CPU time 143.71 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:57:12 PM PDT 24
Peak memory 206444 kb
Host smart-1094be4b-7f38-4fef-89bd-486dcc1aa8e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3994656983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3994656983
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3106420651
Short name T108
Test name
Test status
Simulation time 804413179 ps
CPU time 264.82 seconds
Started Jun 24 04:54:42 PM PDT 24
Finished Jun 24 04:59:14 PM PDT 24
Peak memory 209596 kb
Host smart-da5213ac-fd01-4ce3-8f0a-4409631ff03e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3106420651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.3106420651
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4194681237
Short name T559
Test name
Test status
Simulation time 798417872 ps
CPU time 74.99 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:56:07 PM PDT 24
Peak memory 208068 kb
Host smart-302af509-ddbc-4a5f-a664-d26b3a50e58c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4194681237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.4194681237
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2704567656
Short name T285
Test name
Test status
Simulation time 78508515 ps
CPU time 2.14 seconds
Started Jun 24 04:54:49 PM PDT 24
Finished Jun 24 04:54:59 PM PDT 24
Peak memory 203412 kb
Host smart-89459515-4dcc-43c0-82ee-fff27a1c893d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2704567656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2704567656
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.862353891
Short name T855
Test name
Test status
Simulation time 1746102413 ps
CPU time 63.63 seconds
Started Jun 24 04:54:59 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 211576 kb
Host smart-ede56a02-36be-4514-b470-864783e3ece0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862353891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.862353891
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.4052293225
Short name T746
Test name
Test status
Simulation time 51014739230 ps
CPU time 235.67 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:58:54 PM PDT 24
Peak memory 206624 kb
Host smart-f7e8ad4c-f08d-4500-8c92-8cdfa0c078cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4052293225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.4052293225
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.599496279
Short name T759
Test name
Test status
Simulation time 419450850 ps
CPU time 11.09 seconds
Started Jun 24 04:54:46 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 203420 kb
Host smart-15a732ba-6103-4de9-af5c-74ed443c69a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=599496279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.599496279
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.1856498633
Short name T788
Test name
Test status
Simulation time 804422790 ps
CPU time 15.13 seconds
Started Jun 24 04:54:56 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 203416 kb
Host smart-ec0a0a3b-61b9-4713-9f67-c1a322e5bda0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1856498633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1856498633
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.1083355009
Short name T551
Test name
Test status
Simulation time 122164513 ps
CPU time 12.55 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 204476 kb
Host smart-5806a174-e74a-4c9d-87af-51dc73bb25f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1083355009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1083355009
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1182168658
Short name T180
Test name
Test status
Simulation time 49781558915 ps
CPU time 192.62 seconds
Started Jun 24 04:54:52 PM PDT 24
Finished Jun 24 04:58:11 PM PDT 24
Peak memory 204812 kb
Host smart-fa70d0c6-d59d-42ea-95c0-e4607addd25f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182168658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1182168658
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1468842394
Short name T170
Test name
Test status
Simulation time 37713566759 ps
CPU time 197.3 seconds
Started Jun 24 04:54:52 PM PDT 24
Finished Jun 24 04:58:16 PM PDT 24
Peak memory 211612 kb
Host smart-d4e2766d-981c-4cec-87fc-fab58cb3d3da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1468842394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1468842394
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.25500590
Short name T787
Test name
Test status
Simulation time 226110025 ps
CPU time 20.55 seconds
Started Jun 24 04:54:48 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 204452 kb
Host smart-7f257652-c5bb-4c61-8039-bf7cd4e1da0e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25500590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.25500590
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.3656115140
Short name T717
Test name
Test status
Simulation time 1998820090 ps
CPU time 24.55 seconds
Started Jun 24 04:54:51 PM PDT 24
Finished Jun 24 04:55:23 PM PDT 24
Peak memory 203944 kb
Host smart-d4597935-74f7-4ad2-a530-39eb3f8337b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656115140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3656115140
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.1008878343
Short name T487
Test name
Test status
Simulation time 436888875 ps
CPU time 3.77 seconds
Started Jun 24 04:54:55 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 203272 kb
Host smart-6fef25cb-c51a-4432-b324-1d865afce31f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1008878343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1008878343
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.380340690
Short name T528
Test name
Test status
Simulation time 13913040848 ps
CPU time 35.33 seconds
Started Jun 24 04:54:45 PM PDT 24
Finished Jun 24 04:55:28 PM PDT 24
Peak memory 203452 kb
Host smart-87a08a4e-b17f-470c-9e36-04c8b71863df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=380340690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.380340690
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.4012692644
Short name T622
Test name
Test status
Simulation time 9241280240 ps
CPU time 25.63 seconds
Started Jun 24 04:54:52 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 203456 kb
Host smart-0903d86f-72b3-40d7-a8bf-96b33c3abc35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4012692644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4012692644
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2565414238
Short name T325
Test name
Test status
Simulation time 28382374 ps
CPU time 2.37 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 203392 kb
Host smart-e86df1ff-5c93-4478-a809-f8f74025dccc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565414238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2565414238
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3633578564
Short name T32
Test name
Test status
Simulation time 17984296728 ps
CPU time 283.53 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:59:51 PM PDT 24
Peak memory 207420 kb
Host smart-ca047819-c741-477b-af80-e060e9cc162e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3633578564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3633578564
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.667122910
Short name T612
Test name
Test status
Simulation time 1299696734 ps
CPU time 113.25 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:56:59 PM PDT 24
Peak memory 205584 kb
Host smart-199da0bc-b6b2-4263-9c25-f6522be20b29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=667122910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.667122910
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1152418009
Short name T30
Test name
Test status
Simulation time 201243195 ps
CPU time 82.09 seconds
Started Jun 24 04:55:02 PM PDT 24
Finished Jun 24 04:56:28 PM PDT 24
Peak memory 207308 kb
Host smart-268fb9f4-afed-43a0-98ca-3857e5418ab0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1152418009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.1152418009
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.282882541
Short name T271
Test name
Test status
Simulation time 1644342082 ps
CPU time 141.61 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:57:28 PM PDT 24
Peak memory 210656 kb
Host smart-12894be2-80de-4be6-af8d-2bc6edaa8f76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=282882541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res
et_error.282882541
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2019834077
Short name T265
Test name
Test status
Simulation time 5148634069 ps
CPU time 27.73 seconds
Started Jun 24 04:54:44 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 211616 kb
Host smart-4612bd8a-76ea-4aac-92e2-2a520b1bd581
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2019834077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2019834077
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3000916310
Short name T675
Test name
Test status
Simulation time 1106780907 ps
CPU time 41.24 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 04:55:51 PM PDT 24
Peak memory 211604 kb
Host smart-a6e8a96f-6c90-468c-9349-56363a8b8f92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3000916310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3000916310
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1576494447
Short name T519
Test name
Test status
Simulation time 50448307297 ps
CPU time 468.04 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 05:02:58 PM PDT 24
Peak memory 211628 kb
Host smart-5da3fec6-007a-48c0-afbc-dd07bf6dca24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1576494447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.1576494447
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1073873219
Short name T732
Test name
Test status
Simulation time 918138359 ps
CPU time 23.56 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:55:28 PM PDT 24
Peak memory 203332 kb
Host smart-22758906-5e5c-42ec-82a9-122dcbd855b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1073873219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1073873219
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.3043167118
Short name T834
Test name
Test status
Simulation time 1019348217 ps
CPU time 11.61 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:27 PM PDT 24
Peak memory 203420 kb
Host smart-c9843bc0-4762-45ce-b491-58e6fd2724e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3043167118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3043167118
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.4267698453
Short name T58
Test name
Test status
Simulation time 1007016235 ps
CPU time 32.33 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 204500 kb
Host smart-5dc81dc2-ed5d-4b68-a0cd-69117334ab87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4267698453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.4267698453
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4269572925
Short name T152
Test name
Test status
Simulation time 42463655072 ps
CPU time 128.74 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:57:13 PM PDT 24
Peak memory 211636 kb
Host smart-8ff24775-2af2-44b9-96f6-57acb7f50a50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269572925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4269572925
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1950990621
Short name T199
Test name
Test status
Simulation time 36035369072 ps
CPU time 220.64 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:58:46 PM PDT 24
Peak memory 204740 kb
Host smart-a24d627f-8107-4a5a-9865-a63cdd47bf48
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1950990621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1950990621
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3718381738
Short name T595
Test name
Test status
Simulation time 92236471 ps
CPU time 6.32 seconds
Started Jun 24 04:55:02 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 204508 kb
Host smart-a2d2fe95-a391-4e37-a89f-d5a20c8eb984
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718381738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3718381738
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.4003998884
Short name T575
Test name
Test status
Simulation time 154294484 ps
CPU time 6.17 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:55:09 PM PDT 24
Peak memory 203872 kb
Host smart-6379943d-8314-4b8a-8ce1-90a040552141
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003998884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4003998884
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.2475496936
Short name T391
Test name
Test status
Simulation time 109421159 ps
CPU time 2.26 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:55:06 PM PDT 24
Peak memory 203392 kb
Host smart-9dad062f-e8d4-4507-bf32-ca14dc238f3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2475496936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2475496936
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.854336164
Short name T67
Test name
Test status
Simulation time 7371294852 ps
CPU time 29.15 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 203440 kb
Host smart-6e63a90c-23ae-4323-97a2-07001b76c1cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=854336164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.854336164
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.191952522
Short name T245
Test name
Test status
Simulation time 3599212499 ps
CPU time 24.03 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:55:28 PM PDT 24
Peak memory 203448 kb
Host smart-69f3cca8-acae-4014-976b-c9aedb076424
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=191952522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.191952522
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1097109758
Short name T541
Test name
Test status
Simulation time 80512013 ps
CPU time 2.43 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 203388 kb
Host smart-ce6efeab-41ba-488a-8c57-0807048440f0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097109758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1097109758
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2932379469
Short name T836
Test name
Test status
Simulation time 993835766 ps
CPU time 29.63 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:55:34 PM PDT 24
Peak memory 205448 kb
Host smart-05b1baef-97a0-4560-805d-2ca96d1d30d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2932379469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2932379469
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2245633756
Short name T563
Test name
Test status
Simulation time 3621857905 ps
CPU time 92.87 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:56:37 PM PDT 24
Peak memory 207416 kb
Host smart-d7db1f9b-8e7e-49a2-8a96-22bc73210840
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2245633756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2245633756
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.999575100
Short name T119
Test name
Test status
Simulation time 189353684 ps
CPU time 33.43 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:48 PM PDT 24
Peak memory 206504 kb
Host smart-77715b13-2e58-4a38-bf49-c09af0f4a08c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=999575100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand
_reset.999575100
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3661761713
Short name T664
Test name
Test status
Simulation time 93653811 ps
CPU time 7.12 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203580 kb
Host smart-84c66f75-00f9-4341-9bb2-7699dbdd2f04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3661761713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.3661761713
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.483185344
Short name T435
Test name
Test status
Simulation time 514063946 ps
CPU time 18.33 seconds
Started Jun 24 04:55:02 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 211512 kb
Host smart-e0036010-8f18-4744-84b1-032edfcb1239
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=483185344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.483185344
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.570380682
Short name T852
Test name
Test status
Simulation time 657871160 ps
CPU time 34.71 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:42 PM PDT 24
Peak memory 204680 kb
Host smart-2c45d3b0-248f-4fcc-a8c9-206b7f142047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=570380682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.570380682
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.827741692
Short name T13
Test name
Test status
Simulation time 442882968 ps
CPU time 17.85 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 203348 kb
Host smart-69b49781-ad65-4bc1-87ce-24a3feea0a7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=827741692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.827741692
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.144887970
Short name T3
Test name
Test status
Simulation time 46701691 ps
CPU time 5.16 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 203428 kb
Host smart-e1cb0c43-b5ff-484f-b15e-27f74915e082
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=144887970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.144887970
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.1594543736
Short name T586
Test name
Test status
Simulation time 1520400514 ps
CPU time 35.47 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 04:55:45 PM PDT 24
Peak memory 211832 kb
Host smart-b58dd1c3-611f-48ba-a8e2-ef8aa8b2e1fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1594543736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1594543736
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2320316841
Short name T460
Test name
Test status
Simulation time 4970044309 ps
CPU time 24.94 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:32 PM PDT 24
Peak memory 203484 kb
Host smart-67cd2127-c818-443b-95e0-79709e16dd9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320316841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2320316841
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.343228263
Short name T56
Test name
Test status
Simulation time 19348448924 ps
CPU time 147.15 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:57:34 PM PDT 24
Peak memory 204792 kb
Host smart-72320f41-645b-4d4b-974f-605c0344b288
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=343228263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.343228263
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1215520640
Short name T503
Test name
Test status
Simulation time 386005073 ps
CPU time 14.38 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 211436 kb
Host smart-7329ea2a-ece9-4d64-a38e-b8d214339ee6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215520640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1215520640
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.4104484133
Short name T850
Test name
Test status
Simulation time 8668102059 ps
CPU time 33.52 seconds
Started Jun 24 04:55:02 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 204556 kb
Host smart-06272229-c83b-4938-90ab-d8d356d98583
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4104484133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.4104484133
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.1669230903
Short name T660
Test name
Test status
Simulation time 122261209 ps
CPU time 3.26 seconds
Started Jun 24 04:55:09 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203388 kb
Host smart-e3f5920a-d7a4-47cd-ab0a-4d8ae777c0e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1669230903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1669230903
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2725789456
Short name T256
Test name
Test status
Simulation time 7098748296 ps
CPU time 27.64 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 203456 kb
Host smart-eb3741bc-a138-4964-9c24-72ec6222a23d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725789456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2725789456
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.34904447
Short name T644
Test name
Test status
Simulation time 3146969191 ps
CPU time 25.1 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:55:28 PM PDT 24
Peak memory 203452 kb
Host smart-539a394a-0d4e-4884-8a7d-8ccd44c7d2c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34904447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.34904447
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.111168112
Short name T472
Test name
Test status
Simulation time 45831065 ps
CPU time 2.68 seconds
Started Jun 24 04:55:02 PM PDT 24
Finished Jun 24 04:55:08 PM PDT 24
Peak memory 203336 kb
Host smart-4a539961-ee4f-48f7-aec6-2244715e35aa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111168112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.111168112
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.4063111603
Short name T269
Test name
Test status
Simulation time 2736016855 ps
CPU time 68.31 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 206204 kb
Host smart-63e9b19f-4921-40e7-bbf2-77f56aed7a2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4063111603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4063111603
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1269998966
Short name T645
Test name
Test status
Simulation time 1780430429 ps
CPU time 216.15 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:58:39 PM PDT 24
Peak memory 208568 kb
Host smart-0363d5c5-e77b-47fa-a63f-00a2d9bbbe38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1269998966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.1269998966
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3498001133
Short name T169
Test name
Test status
Simulation time 1756407779 ps
CPU time 180.19 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:58:04 PM PDT 24
Peak memory 219724 kb
Host smart-f8319e74-9a5d-42b1-830a-2cf43dc69b55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3498001133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.3498001133
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2038500532
Short name T676
Test name
Test status
Simulation time 879674058 ps
CPU time 26.17 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 205028 kb
Host smart-cbd90362-fa39-4072-b23d-5055e242753b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2038500532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2038500532
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.4028510411
Short name T514
Test name
Test status
Simulation time 484675639 ps
CPU time 28.61 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:55:37 PM PDT 24
Peak memory 211504 kb
Host smart-b96dd97d-cd50-4bc9-84b0-3a5a57cfa000
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4028510411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.4028510411
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.345755363
Short name T407
Test name
Test status
Simulation time 80422079825 ps
CPU time 505.45 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 05:03:34 PM PDT 24
Peak memory 211540 kb
Host smart-f00ff21a-ab14-46cc-9e1d-45040fa0d04c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=345755363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo
w_rsp.345755363
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2392295141
Short name T571
Test name
Test status
Simulation time 2421233011 ps
CPU time 24.55 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:35 PM PDT 24
Peak memory 203476 kb
Host smart-1cf3c1af-bea8-4100-a48b-0e6fa112f2d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2392295141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2392295141
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.2078783365
Short name T178
Test name
Test status
Simulation time 166484352 ps
CPU time 14.76 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:22 PM PDT 24
Peak memory 203504 kb
Host smart-6ee7d62c-223a-4f4f-8f46-de51177bc337
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2078783365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2078783365
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.2776264252
Short name T814
Test name
Test status
Simulation time 89130839 ps
CPU time 3.15 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:10 PM PDT 24
Peak memory 203416 kb
Host smart-f23f8176-bf1f-4724-93b6-46aef0479280
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2776264252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2776264252
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2636887695
Short name T802
Test name
Test status
Simulation time 100791421870 ps
CPU time 274.33 seconds
Started Jun 24 04:55:10 PM PDT 24
Finished Jun 24 04:59:46 PM PDT 24
Peak memory 211664 kb
Host smart-447e44d1-b787-425b-91cb-934341f544f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636887695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2636887695
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2065918649
Short name T51
Test name
Test status
Simulation time 26136776407 ps
CPU time 243.52 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:59:12 PM PDT 24
Peak memory 211584 kb
Host smart-db359ec6-a916-478c-b5e6-59eb5d81ba0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2065918649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2065918649
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2340012670
Short name T161
Test name
Test status
Simulation time 37733166 ps
CPU time 2.48 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:09 PM PDT 24
Peak memory 203320 kb
Host smart-00a542b0-c138-483d-b7d2-95cfddf14c23
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340012670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2340012670
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.3576753459
Short name T244
Test name
Test status
Simulation time 282922972 ps
CPU time 18.61 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203920 kb
Host smart-bb42e015-9b57-4423-9853-58ae8e0706d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3576753459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3576753459
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.4288783784
Short name T772
Test name
Test status
Simulation time 148455802 ps
CPU time 3.11 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:55:10 PM PDT 24
Peak memory 203308 kb
Host smart-30e8af02-0ebb-4d43-b3cc-296210bd20bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4288783784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4288783784
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1376735474
Short name T614
Test name
Test status
Simulation time 6558708628 ps
CPU time 28.59 seconds
Started Jun 24 04:55:00 PM PDT 24
Finished Jun 24 04:55:32 PM PDT 24
Peak memory 203464 kb
Host smart-661fed5e-1302-4efe-b2e9-3023f83f49ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376735474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1376735474
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3146148256
Short name T669
Test name
Test status
Simulation time 5150860512 ps
CPU time 35.15 seconds
Started Jun 24 04:55:16 PM PDT 24
Finished Jun 24 04:55:53 PM PDT 24
Peak memory 203440 kb
Host smart-daeb124f-d87b-408f-a79d-82d379b31212
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3146148256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3146148256
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3079872522
Short name T18
Test name
Test status
Simulation time 22787672 ps
CPU time 1.91 seconds
Started Jun 24 04:55:11 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203388 kb
Host smart-c9c47f16-f744-4cbd-9e84-2d29bb0d72b6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079872522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3079872522
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.525477032
Short name T91
Test name
Test status
Simulation time 5030694672 ps
CPU time 68.06 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 206592 kb
Host smart-28abeca7-8ef2-4b54-b084-af90a2c058cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=525477032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.525477032
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.115332981
Short name T334
Test name
Test status
Simulation time 124196254 ps
CPU time 15.07 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:55:22 PM PDT 24
Peak memory 204928 kb
Host smart-d11be8ff-ecc2-4e81-abcd-f22dc575f43d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115332981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.115332981
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1823121514
Short name T692
Test name
Test status
Simulation time 3198115315 ps
CPU time 255.56 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:59:30 PM PDT 24
Peak memory 208568 kb
Host smart-352ed6e8-74b5-4978-88e3-29c69e37715e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1823121514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.1823121514
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1910798452
Short name T718
Test name
Test status
Simulation time 556729338 ps
CPU time 104.68 seconds
Started Jun 24 04:55:07 PM PDT 24
Finished Jun 24 04:56:54 PM PDT 24
Peak memory 209708 kb
Host smart-9e917f42-7a6f-4c08-90f4-329aee93ae25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1910798452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1910798452
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3514287494
Short name T899
Test name
Test status
Simulation time 705799035 ps
CPU time 26.31 seconds
Started Jun 24 04:55:01 PM PDT 24
Finished Jun 24 04:55:31 PM PDT 24
Peak memory 211596 kb
Host smart-31931af4-53cd-40ca-848f-94abe9e9ed47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3514287494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3514287494
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1937508870
Short name T851
Test name
Test status
Simulation time 451846123 ps
CPU time 31.03 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:48 PM PDT 24
Peak memory 211516 kb
Host smart-f87f64f5-cd11-497a-91bd-ae8054d7deb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937508870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1937508870
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1058502982
Short name T196
Test name
Test status
Simulation time 42380213057 ps
CPU time 202.71 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:58:30 PM PDT 24
Peak memory 211600 kb
Host smart-91e0106a-ec84-4c2c-b589-128737f0cc48
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1058502982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.1058502982
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.806866040
Short name T672
Test name
Test status
Simulation time 432781307 ps
CPU time 15.37 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:33 PM PDT 24
Peak memory 203420 kb
Host smart-efe088f0-bbb9-4486-a2ae-dfd141d89ae0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=806866040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.806866040
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.3782605811
Short name T880
Test name
Test status
Simulation time 744390390 ps
CPU time 8.39 seconds
Started Jun 24 04:55:09 PM PDT 24
Finished Jun 24 04:55:20 PM PDT 24
Peak memory 203404 kb
Host smart-071f8e86-29ad-4d19-959b-b7f882141208
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3782605811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3782605811
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.543661738
Short name T284
Test name
Test status
Simulation time 369468705 ps
CPU time 10.3 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:21 PM PDT 24
Peak memory 204528 kb
Host smart-5045fae0-b966-4cc5-a779-83e98f8fa4ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=543661738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.543661738
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.75714179
Short name T685
Test name
Test status
Simulation time 64900512826 ps
CPU time 221.07 seconds
Started Jun 24 04:55:16 PM PDT 24
Finished Jun 24 04:58:59 PM PDT 24
Peak memory 204984 kb
Host smart-7ac76a16-9670-4de2-aae2-6b055338606e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=75714179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.75714179
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3987294589
Short name T415
Test name
Test status
Simulation time 28878853080 ps
CPU time 216.26 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:58:43 PM PDT 24
Peak memory 211548 kb
Host smart-076db5f6-cf29-4629-b1ad-53a1c5987919
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3987294589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3987294589
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.4006765260
Short name T141
Test name
Test status
Simulation time 202263227 ps
CPU time 21.99 seconds
Started Jun 24 04:55:12 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 211556 kb
Host smart-9d2bbb28-4006-4309-9aa2-cbbe186b58f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006765260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.4006765260
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.2178168731
Short name T497
Test name
Test status
Simulation time 2630941034 ps
CPU time 33.12 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:48 PM PDT 24
Peak memory 211636 kb
Host smart-6329afdc-b604-41c8-8e9b-530c6764ad73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2178168731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2178168731
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.2611789093
Short name T4
Test name
Test status
Simulation time 22539004 ps
CPU time 2.23 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 203392 kb
Host smart-365e3518-6a3a-4aa9-b3f9-e913feb0d4f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2611789093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2611789093
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2415297383
Short name T709
Test name
Test status
Simulation time 7467935156 ps
CPU time 28.92 seconds
Started Jun 24 04:55:16 PM PDT 24
Finished Jun 24 04:55:47 PM PDT 24
Peak memory 203468 kb
Host smart-ab528729-e17e-4f40-bced-d49a5540055e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415297383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2415297383
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2205049104
Short name T864
Test name
Test status
Simulation time 9354239557 ps
CPU time 38.45 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 203464 kb
Host smart-ac8c4a26-31a2-463c-af42-2570c78824d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2205049104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2205049104
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1429627801
Short name T520
Test name
Test status
Simulation time 46151500 ps
CPU time 2.14 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:13 PM PDT 24
Peak memory 203300 kb
Host smart-824f927d-494d-4ffe-976e-6598e8744241
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429627801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1429627801
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.547829534
Short name T819
Test name
Test status
Simulation time 7888469518 ps
CPU time 224.45 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:59:00 PM PDT 24
Peak memory 210088 kb
Host smart-decdaeeb-9785-44fa-961c-b507593fae98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547829534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.547829534
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.178030530
Short name T118
Test name
Test status
Simulation time 198441197 ps
CPU time 3.8 seconds
Started Jun 24 04:55:08 PM PDT 24
Finished Jun 24 04:55:14 PM PDT 24
Peak memory 203332 kb
Host smart-cdc455f9-6312-4acd-86c3-9dc23dac0101
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=178030530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.178030530
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1056132213
Short name T742
Test name
Test status
Simulation time 518048831 ps
CPU time 237.49 seconds
Started Jun 24 04:55:04 PM PDT 24
Finished Jun 24 04:59:05 PM PDT 24
Peak memory 209456 kb
Host smart-676cc756-87e9-4947-bc3f-aa1ae98ac347
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1056132213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1056132213
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.350261712
Short name T867
Test name
Test status
Simulation time 142652032 ps
CPU time 13.13 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:55:21 PM PDT 24
Peak memory 205104 kb
Host smart-bb5bbb47-0a15-4250-9e74-259e611be848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=350261712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res
et_error.350261712
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2525473563
Short name T214
Test name
Test status
Simulation time 658232658 ps
CPU time 5.31 seconds
Started Jun 24 04:55:11 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 204576 kb
Host smart-a34fcf0f-9647-4dab-b86c-4cf22dc42620
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2525473563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2525473563
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2973996821
Short name T690
Test name
Test status
Simulation time 67338318 ps
CPU time 5.74 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:14 PM PDT 24
Peak memory 203444 kb
Host smart-9280add3-19f3-4de9-8e2e-d976d0a5f494
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2973996821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2973996821
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1987411333
Short name T522
Test name
Test status
Simulation time 49902685013 ps
CPU time 312.93 seconds
Started Jun 24 04:54:17 PM PDT 24
Finished Jun 24 04:59:34 PM PDT 24
Peak memory 211628 kb
Host smart-5a77e1cb-0a9b-4d20-854b-12d4ed6e2ce2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1987411333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.1987411333
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3635194892
Short name T418
Test name
Test status
Simulation time 171473004 ps
CPU time 3.93 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:20 PM PDT 24
Peak memory 203420 kb
Host smart-0d17e6a9-d5d2-4c54-98bd-c50d7fb82848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3635194892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3635194892
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.1383419206
Short name T707
Test name
Test status
Simulation time 685347278 ps
CPU time 16.58 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 203428 kb
Host smart-932bdb04-1fcb-48bf-a7f3-b04f29f60161
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1383419206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1383419206
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.513948423
Short name T545
Test name
Test status
Simulation time 199138114 ps
CPU time 7.17 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 211444 kb
Host smart-9143511a-7c2f-477c-b9f5-a61c9e692e1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=513948423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.513948423
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3524955279
Short name T75
Test name
Test status
Simulation time 35881672768 ps
CPU time 118.54 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:56:11 PM PDT 24
Peak memory 211660 kb
Host smart-3b2f60cc-7174-44a6-b35c-af1cba85863b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524955279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3524955279
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4162484744
Short name T615
Test name
Test status
Simulation time 9219060771 ps
CPU time 30.11 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 211632 kb
Host smart-f166790a-d5eb-4324-b92c-7a51465bf507
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4162484744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4162484744
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.387169043
Short name T523
Test name
Test status
Simulation time 80534915 ps
CPU time 10.27 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:30 PM PDT 24
Peak memory 211572 kb
Host smart-3bb06289-9d91-4416-8de1-ef2cb3e8186a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387169043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.387169043
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3909277781
Short name T530
Test name
Test status
Simulation time 284919952 ps
CPU time 17.59 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:54:35 PM PDT 24
Peak memory 203936 kb
Host smart-f50fc7c3-9b2e-4073-8d25-0eaaf12f18af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3909277781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3909277781
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.3272485366
Short name T385
Test name
Test status
Simulation time 155555677 ps
CPU time 3.61 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:54:10 PM PDT 24
Peak memory 203384 kb
Host smart-5b67e39f-fdb6-4600-8b5c-ca9783c089bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3272485366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3272485366
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4084764553
Short name T156
Test name
Test status
Simulation time 4645959256 ps
CPU time 22.98 seconds
Started Jun 24 04:53:58 PM PDT 24
Finished Jun 24 04:54:26 PM PDT 24
Peak memory 203364 kb
Host smart-31a947a2-df6e-48e6-908c-bb87554cb5fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084764553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4084764553
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.164133304
Short name T469
Test name
Test status
Simulation time 3949592499 ps
CPU time 31.38 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 203452 kb
Host smart-81aab094-bdb6-4b85-99dd-2b164d2c8581
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=164133304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.164133304
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1749644943
Short name T302
Test name
Test status
Simulation time 27798636 ps
CPU time 2.3 seconds
Started Jun 24 04:54:07 PM PDT 24
Finished Jun 24 04:54:14 PM PDT 24
Peak memory 203376 kb
Host smart-427c47cc-9df6-4146-9df2-a56c02678be6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749644943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1749644943
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.871080532
Short name T429
Test name
Test status
Simulation time 40124195749 ps
CPU time 346.1 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:59:52 PM PDT 24
Peak memory 211560 kb
Host smart-78e529fe-9177-4441-b52c-0369b7c38f23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=871080532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.871080532
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2234988987
Short name T860
Test name
Test status
Simulation time 5300984434 ps
CPU time 151.08 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:56:49 PM PDT 24
Peak memory 209136 kb
Host smart-8cb3e9d6-5f26-48c5-af1c-413843febc84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2234988987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2234988987
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3790178808
Short name T164
Test name
Test status
Simulation time 9302258668 ps
CPU time 137.05 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:56:37 PM PDT 24
Peak memory 208384 kb
Host smart-c8239bc8-0427-4f94-82f8-efaa91707c7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3790178808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.3790178808
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1021244811
Short name T596
Test name
Test status
Simulation time 4147519427 ps
CPU time 149.08 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:56:47 PM PDT 24
Peak memory 207872 kb
Host smart-3c4c1436-51f0-4b18-9d19-c102099c39b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1021244811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1021244811
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.4115010799
Short name T292
Test name
Test status
Simulation time 102758603 ps
CPU time 5.67 seconds
Started Jun 24 04:54:02 PM PDT 24
Finished Jun 24 04:54:13 PM PDT 24
Peak memory 211592 kb
Host smart-c982b31e-7037-4777-be72-85184a0af00d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115010799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4115010799
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3303071666
Short name T782
Test name
Test status
Simulation time 127431038 ps
CPU time 5.36 seconds
Started Jun 24 04:55:12 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 203420 kb
Host smart-27c43d54-6040-45e0-8890-b849d949705d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3303071666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3303071666
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3624601579
Short name T476
Test name
Test status
Simulation time 3636090497 ps
CPU time 27.45 seconds
Started Jun 24 04:55:17 PM PDT 24
Finished Jun 24 04:55:46 PM PDT 24
Peak memory 203492 kb
Host smart-7bd09c5c-4142-4e0f-9046-08a3e4b55eb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3624601579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3624601579
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.2172794945
Short name T474
Test name
Test status
Simulation time 391658857 ps
CPU time 8.49 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 203328 kb
Host smart-fdb8fb59-bfd1-4074-97ff-c569adb071f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2172794945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2172794945
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.2287923200
Short name T223
Test name
Test status
Simulation time 799586359 ps
CPU time 23 seconds
Started Jun 24 04:55:11 PM PDT 24
Finished Jun 24 04:55:35 PM PDT 24
Peak memory 204528 kb
Host smart-cf1f6488-90cc-4f90-904e-36239b83b2fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2287923200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2287923200
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1940307761
Short name T865
Test name
Test status
Simulation time 21687846672 ps
CPU time 98.34 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:56:45 PM PDT 24
Peak memory 204696 kb
Host smart-2eddba10-bfd5-4130-8cfe-446a20eb3226
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940307761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1940307761
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1287199391
Short name T673
Test name
Test status
Simulation time 35535074080 ps
CPU time 264.51 seconds
Started Jun 24 04:55:06 PM PDT 24
Finished Jun 24 04:59:34 PM PDT 24
Peak memory 211588 kb
Host smart-ace4a3bd-4fc6-4aae-9e8a-ad82fd43847c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1287199391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1287199391
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2950134280
Short name T321
Test name
Test status
Simulation time 608557057 ps
CPU time 16.33 seconds
Started Jun 24 04:55:06 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 204380 kb
Host smart-c0ceecc6-19f8-4902-bdde-551c9ed0bb5a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950134280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2950134280
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.609957419
Short name T121
Test name
Test status
Simulation time 536201837 ps
CPU time 11.91 seconds
Started Jun 24 04:55:03 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 204024 kb
Host smart-9dc7a293-3e32-4b5a-b5b5-e53302fc3614
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=609957419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.609957419
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.582983474
Short name T158
Test name
Test status
Simulation time 241332921 ps
CPU time 3.98 seconds
Started Jun 24 04:55:11 PM PDT 24
Finished Jun 24 04:55:17 PM PDT 24
Peak memory 203392 kb
Host smart-95d0eaa7-f0a6-4510-b6c7-a37798c7459a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=582983474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.582983474
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2037645526
Short name T738
Test name
Test status
Simulation time 20675332127 ps
CPU time 35.07 seconds
Started Jun 24 04:55:05 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 203452 kb
Host smart-05565ae0-7d16-4a98-b5a3-569d0806dfbe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037645526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2037645526
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.4070505765
Short name T280
Test name
Test status
Simulation time 7135565933 ps
CPU time 27.22 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:45 PM PDT 24
Peak memory 203460 kb
Host smart-fceb7409-f31d-4220-b8ff-16df88307010
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4070505765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4070505765
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1549391668
Short name T98
Test name
Test status
Simulation time 48354626 ps
CPU time 2.47 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 203388 kb
Host smart-3b99747a-cdca-4413-929f-1ba5baff1dfa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549391668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1549391668
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2870081755
Short name T150
Test name
Test status
Simulation time 949105649 ps
CPU time 80.04 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:56:37 PM PDT 24
Peak memory 211488 kb
Host smart-d53f019d-cdbc-43a7-9921-41b03a9c41ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2870081755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2870081755
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3564963170
Short name T372
Test name
Test status
Simulation time 2226997251 ps
CPU time 57.01 seconds
Started Jun 24 04:55:17 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 205000 kb
Host smart-cff8dda0-5116-4fb5-afcf-263c188ec3d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3564963170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3564963170
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.19154423
Short name T560
Test name
Test status
Simulation time 463552461 ps
CPU time 161.11 seconds
Started Jun 24 04:55:12 PM PDT 24
Finished Jun 24 04:57:55 PM PDT 24
Peak memory 208700 kb
Host smart-027adc43-f247-46c2-9687-867bb97449b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19154423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_
reset.19154423
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.4112496353
Short name T508
Test name
Test status
Simulation time 8755827521 ps
CPU time 363.51 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 05:01:19 PM PDT 24
Peak memory 219784 kb
Host smart-5e29a4e7-931f-4222-bc87-e26d443900b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4112496353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.4112496353
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1139418919
Short name T240
Test name
Test status
Simulation time 189237831 ps
CPU time 13.86 seconds
Started Jun 24 04:55:16 PM PDT 24
Finished Jun 24 04:55:32 PM PDT 24
Peak memory 205048 kb
Host smart-4362f623-d955-4e71-8e5b-3df36382b1c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1139418919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1139418919
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2352963659
Short name T249
Test name
Test status
Simulation time 100000570 ps
CPU time 5.03 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 04:55:21 PM PDT 24
Peak memory 203516 kb
Host smart-36d02939-b480-4edd-921a-b49294d25e5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2352963659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2352963659
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3649424099
Short name T262
Test name
Test status
Simulation time 502076914407 ps
CPU time 755.08 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 05:07:51 PM PDT 24
Peak memory 207416 kb
Host smart-54806d00-766c-41c1-8bc9-563cb3effdb4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3649424099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.3649424099
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3386040532
Short name T326
Test name
Test status
Simulation time 2389371514 ps
CPU time 26.77 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 203640 kb
Host smart-edc022e4-4ff7-4ff9-948e-b07e0c6718f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3386040532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3386040532
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.3769526853
Short name T296
Test name
Test status
Simulation time 560517890 ps
CPU time 8.75 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 203420 kb
Host smart-dbbc1d9c-49f8-4110-919e-5808cdff00b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3769526853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3769526853
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.1988254893
Short name T80
Test name
Test status
Simulation time 978802062 ps
CPU time 41.68 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 04:55:58 PM PDT 24
Peak memory 211568 kb
Host smart-2918ab72-6cf0-44fd-8858-c6a1bd982f40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1988254893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1988254893
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.320046198
Short name T112
Test name
Test status
Simulation time 66415027637 ps
CPU time 236.48 seconds
Started Jun 24 04:55:12 PM PDT 24
Finished Jun 24 04:59:10 PM PDT 24
Peak memory 211620 kb
Host smart-50556222-8b6d-4f8d-9ae8-cb837e85a856
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=320046198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.320046198
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.372601227
Short name T658
Test name
Test status
Simulation time 22229544783 ps
CPU time 183.16 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:58:18 PM PDT 24
Peak memory 211544 kb
Host smart-2e3a7c06-002c-48fa-8bf8-02b3412e2913
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=372601227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.372601227
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.719405112
Short name T789
Test name
Test status
Simulation time 274083211 ps
CPU time 21.81 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 04:55:38 PM PDT 24
Peak memory 204860 kb
Host smart-716c6556-3f98-42af-99f7-8fafdebee361
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719405112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.719405112
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.4052727425
Short name T618
Test name
Test status
Simulation time 599183256 ps
CPU time 4.27 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 203416 kb
Host smart-cb2f19ff-33e1-4029-8797-9de86b796f2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4052727425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4052727425
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.268963685
Short name T882
Test name
Test status
Simulation time 211261416 ps
CPU time 4.04 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 203396 kb
Host smart-834584d8-f30a-46ef-9f48-27c7e4bf56ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=268963685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.268963685
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4051928671
Short name T109
Test name
Test status
Simulation time 7322653639 ps
CPU time 32.5 seconds
Started Jun 24 04:55:14 PM PDT 24
Finished Jun 24 04:55:48 PM PDT 24
Peak memory 203380 kb
Host smart-e3432221-7043-430a-9e58-58ca007b5d55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051928671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4051928671
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3950737035
Short name T657
Test name
Test status
Simulation time 22742026798 ps
CPU time 50.22 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:56:05 PM PDT 24
Peak memory 203376 kb
Host smart-29275432-c2d2-4871-ae0c-01181bb745c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3950737035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3950737035
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1051985308
Short name T376
Test name
Test status
Simulation time 50399737 ps
CPU time 2.67 seconds
Started Jun 24 04:55:12 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 203392 kb
Host smart-d3786ac7-480d-4e2d-b769-fab404e2a9c9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051985308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1051985308
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1229423293
Short name T77
Test name
Test status
Simulation time 1711929752 ps
CPU time 50.23 seconds
Started Jun 24 04:55:17 PM PDT 24
Finished Jun 24 04:56:09 PM PDT 24
Peak memory 206060 kb
Host smart-407210fb-07db-4796-9e94-cf656fc9d22f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1229423293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1229423293
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4075960300
Short name T294
Test name
Test status
Simulation time 2541605412 ps
CPU time 164.57 seconds
Started Jun 24 04:55:10 PM PDT 24
Finished Jun 24 04:57:56 PM PDT 24
Peak memory 210256 kb
Host smart-fa8444a5-35d8-4c11-a77a-852f51f08d2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4075960300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4075960300
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1853089202
Short name T34
Test name
Test status
Simulation time 456737583 ps
CPU time 156.28 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:57:52 PM PDT 24
Peak memory 211548 kb
Host smart-c9923500-58fc-42a5-aabb-198b7650ad46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1853089202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.1853089202
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4191611205
Short name T458
Test name
Test status
Simulation time 3966261672 ps
CPU time 24.51 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:41 PM PDT 24
Peak memory 211568 kb
Host smart-5c825354-2915-4c10-86c2-da88a208a535
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4191611205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4191611205
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2191490709
Short name T651
Test name
Test status
Simulation time 1137119061 ps
CPU time 44.64 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:56:09 PM PDT 24
Peak memory 211528 kb
Host smart-8e2c1b02-8f80-4c5d-9046-85f5aad4d046
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2191490709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2191490709
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2514147375
Short name T646
Test name
Test status
Simulation time 49512566437 ps
CPU time 396.75 seconds
Started Jun 24 04:55:21 PM PDT 24
Finished Jun 24 05:01:59 PM PDT 24
Peak memory 211652 kb
Host smart-4f709b10-e9e4-4373-8cdb-4a67ec2aa2a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2514147375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.2514147375
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2144877692
Short name T886
Test name
Test status
Simulation time 199100666 ps
CPU time 12.85 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:38 PM PDT 24
Peak memory 203416 kb
Host smart-ac39a6c5-07d4-4745-b57f-6af0b45ffb77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2144877692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2144877692
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.1529509437
Short name T890
Test name
Test status
Simulation time 186571357 ps
CPU time 8.57 seconds
Started Jun 24 04:55:20 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203336 kb
Host smart-be9714e2-2f46-44ff-aeb9-38e014fd2319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529509437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1529509437
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2431178807
Short name T826
Test name
Test status
Simulation time 340532755 ps
CPU time 7.35 seconds
Started Jun 24 04:55:15 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 211548 kb
Host smart-5766684b-1443-4c37-8ba6-2884eb7c3180
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2431178807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2431178807
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.32620047
Short name T722
Test name
Test status
Simulation time 32270432001 ps
CPU time 147.98 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:57:43 PM PDT 24
Peak memory 205048 kb
Host smart-33fcd606-a176-4f37-a586-9158ac9bd582
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=32620047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.32620047
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.872272656
Short name T583
Test name
Test status
Simulation time 14243578838 ps
CPU time 50.66 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 204660 kb
Host smart-3cc9413d-f1dc-4348-963c-1e919c5044b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=872272656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.872272656
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1949733329
Short name T151
Test name
Test status
Simulation time 69292613 ps
CPU time 8.07 seconds
Started Jun 24 04:55:10 PM PDT 24
Finished Jun 24 04:55:20 PM PDT 24
Peak memory 211572 kb
Host smart-5c834cc9-1343-480f-9e9c-1e76cee02115
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949733329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1949733329
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.4243523308
Short name T291
Test name
Test status
Simulation time 168826831 ps
CPU time 5 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:31 PM PDT 24
Peak memory 203972 kb
Host smart-f1cd54f1-9997-4d48-a98f-827bccefb1a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4243523308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4243523308
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.1884882555
Short name T59
Test name
Test status
Simulation time 169053915 ps
CPU time 3.77 seconds
Started Jun 24 04:55:17 PM PDT 24
Finished Jun 24 04:55:23 PM PDT 24
Peak memory 203392 kb
Host smart-7ac43d62-dd0e-40f6-a1d6-4989c6e7c784
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1884882555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1884882555
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.249078645
Short name T620
Test name
Test status
Simulation time 27597923096 ps
CPU time 45.29 seconds
Started Jun 24 04:55:11 PM PDT 24
Finished Jun 24 04:55:58 PM PDT 24
Peak memory 203360 kb
Host smart-69b8cfd7-b398-4fe1-a4a2-ab0658d8d37b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=249078645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.249078645
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.290815574
Short name T138
Test name
Test status
Simulation time 2225326953 ps
CPU time 21.41 seconds
Started Jun 24 04:55:11 PM PDT 24
Finished Jun 24 04:55:34 PM PDT 24
Peak memory 203468 kb
Host smart-4e7269ba-2366-48d2-8973-75f225086ddf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=290815574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.290815574
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.705854398
Short name T633
Test name
Test status
Simulation time 66558374 ps
CPU time 2.43 seconds
Started Jun 24 04:55:13 PM PDT 24
Finished Jun 24 04:55:18 PM PDT 24
Peak memory 203376 kb
Host smart-1c25c202-0ca1-4e95-ae24-a438a9d6db11
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705854398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.705854398
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1132075563
Short name T656
Test name
Test status
Simulation time 315402039 ps
CPU time 3.79 seconds
Started Jun 24 04:55:19 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 203656 kb
Host smart-01e6d35c-10a3-4d76-b0b2-7506d50f2581
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1132075563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1132075563
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4091159540
Short name T866
Test name
Test status
Simulation time 3295245643 ps
CPU time 159.3 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:58:05 PM PDT 24
Peak memory 208532 kb
Host smart-b8baed20-0733-430c-b82d-93de08ca125a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4091159540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4091159540
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3646090370
Short name T123
Test name
Test status
Simulation time 9956170249 ps
CPU time 326.32 seconds
Started Jun 24 04:55:20 PM PDT 24
Finished Jun 24 05:00:48 PM PDT 24
Peak memory 210244 kb
Host smart-047d6cce-3017-4daa-9770-968bdab1dfca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3646090370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.3646090370
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4286093341
Short name T72
Test name
Test status
Simulation time 480628789 ps
CPU time 163.38 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:58:07 PM PDT 24
Peak memory 211116 kb
Host smart-4a5fb741-b261-4389-ad5a-91ea22d5653a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4286093341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.4286093341
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.642937892
Short name T348
Test name
Test status
Simulation time 463623665 ps
CPU time 8.79 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:55:33 PM PDT 24
Peak memory 211508 kb
Host smart-f84807c9-4ce7-438d-9bc4-543ac817b88f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=642937892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.642937892
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.2884399049
Short name T88
Test name
Test status
Simulation time 3524836752 ps
CPU time 49.42 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 206108 kb
Host smart-29d272f8-8e90-4c5a-a6dc-5283ca0091b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2884399049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2884399049
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.718084247
Short name T159
Test name
Test status
Simulation time 35589194416 ps
CPU time 212.8 seconds
Started Jun 24 04:55:25 PM PDT 24
Finished Jun 24 04:59:00 PM PDT 24
Peak memory 211652 kb
Host smart-5a2039c7-3cec-48af-bcf8-473c8c72a9a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=718084247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo
w_rsp.718084247
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3837047421
Short name T346
Test name
Test status
Simulation time 40192011 ps
CPU time 5.66 seconds
Started Jun 24 04:55:26 PM PDT 24
Finished Jun 24 04:55:33 PM PDT 24
Peak memory 203328 kb
Host smart-f06611a5-0ac0-4583-8608-26bf71865bdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3837047421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3837047421
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.340780599
Short name T430
Test name
Test status
Simulation time 63149738 ps
CPU time 2.46 seconds
Started Jun 24 04:55:25 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203424 kb
Host smart-dcdf2cab-dac6-4ff5-b587-374b3c50c227
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=340780599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.340780599
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3309585198
Short name T723
Test name
Test status
Simulation time 246813123 ps
CPU time 15.67 seconds
Started Jun 24 04:55:21 PM PDT 24
Finished Jun 24 04:55:38 PM PDT 24
Peak memory 211500 kb
Host smart-e26a7719-7d85-4e28-9fe0-1524853c8cc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3309585198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3309585198
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3727667976
Short name T526
Test name
Test status
Simulation time 27415844245 ps
CPU time 90.67 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:56:57 PM PDT 24
Peak memory 204776 kb
Host smart-2c0b6229-dde9-4654-a1b6-4218fc36a5b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727667976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3727667976
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3620571321
Short name T66
Test name
Test status
Simulation time 9268582677 ps
CPU time 69.57 seconds
Started Jun 24 04:55:26 PM PDT 24
Finished Jun 24 04:56:37 PM PDT 24
Peak memory 204888 kb
Host smart-b4e3fc5f-3a0d-4eb8-81c7-8f6b3d78ed90
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3620571321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3620571321
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1308015348
Short name T97
Test name
Test status
Simulation time 180424678 ps
CPU time 14.13 seconds
Started Jun 24 04:55:24 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 204492 kb
Host smart-c2ef842e-b125-4231-8f91-f0a14828a434
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308015348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1308015348
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1274537670
Short name T755
Test name
Test status
Simulation time 1084464941 ps
CPU time 19.17 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 211488 kb
Host smart-dc3c74f7-a5f3-434d-a9cb-9af1d48f5e97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1274537670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1274537670
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.179321188
Short name T60
Test name
Test status
Simulation time 173841246 ps
CPU time 3.18 seconds
Started Jun 24 04:55:21 PM PDT 24
Finished Jun 24 04:55:26 PM PDT 24
Peak memory 203316 kb
Host smart-f6832684-2fe1-4b4d-9481-1a86d327a1de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=179321188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.179321188
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2017068669
Short name T243
Test name
Test status
Simulation time 12392115157 ps
CPU time 30.45 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:57 PM PDT 24
Peak memory 203464 kb
Host smart-3189ca7f-fabb-4e27-9017-821b2d7aff63
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017068669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2017068669
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1656262766
Short name T825
Test name
Test status
Simulation time 3218357758 ps
CPU time 29.15 seconds
Started Jun 24 04:55:19 PM PDT 24
Finished Jun 24 04:55:49 PM PDT 24
Peak memory 203464 kb
Host smart-473a4179-b88f-4218-9086-b04cbc45177a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1656262766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1656262766
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2603695597
Short name T54
Test name
Test status
Simulation time 24893536 ps
CPU time 2.3 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:27 PM PDT 24
Peak memory 203392 kb
Host smart-6b7d0080-4689-45f3-8c39-d6edcf4e59ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603695597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2603695597
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1883220891
Short name T731
Test name
Test status
Simulation time 5752173917 ps
CPU time 56.19 seconds
Started Jun 24 04:55:20 PM PDT 24
Finished Jun 24 04:56:18 PM PDT 24
Peak memory 207112 kb
Host smart-0447df19-ccde-42aa-86c6-1d21d3710920
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1883220891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1883220891
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2970690420
Short name T335
Test name
Test status
Simulation time 10633342293 ps
CPU time 285.92 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 05:00:12 PM PDT 24
Peak memory 219980 kb
Host smart-3bdd45c5-fe15-449f-b7b4-b46e92c27db9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2970690420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2970690420
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3338069611
Short name T229
Test name
Test status
Simulation time 2655525124 ps
CPU time 420.3 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 05:02:24 PM PDT 24
Peak memory 210700 kb
Host smart-63ddf23c-a6c2-4081-b036-decf4e4855c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3338069611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3338069611
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2569672895
Short name T367
Test name
Test status
Simulation time 3015760163 ps
CPU time 160.29 seconds
Started Jun 24 04:55:21 PM PDT 24
Finished Jun 24 04:58:03 PM PDT 24
Peak memory 211048 kb
Host smart-50e80d87-297a-45cd-b4c3-a531e2988bbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2569672895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.2569672895
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1535932670
Short name T532
Test name
Test status
Simulation time 46861711 ps
CPU time 5.81 seconds
Started Jun 24 04:55:19 PM PDT 24
Finished Jun 24 04:55:26 PM PDT 24
Peak memory 211508 kb
Host smart-3051571c-ca1c-42cb-ac1c-81ea9f843a01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1535932670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1535932670
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1966884969
Short name T635
Test name
Test status
Simulation time 652270901 ps
CPU time 11.5 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:37 PM PDT 24
Peak memory 211568 kb
Host smart-4a9954a4-b3df-48a4-a5a3-cd7161a21a5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1966884969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1966884969
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.800464091
Short name T734
Test name
Test status
Simulation time 16251592637 ps
CPU time 129.83 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:57:34 PM PDT 24
Peak memory 211644 kb
Host smart-5c68c6b8-c30c-4638-bb93-bd4be206cea9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=800464091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo
w_rsp.800464091
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2026147855
Short name T603
Test name
Test status
Simulation time 1607094462 ps
CPU time 27.93 seconds
Started Jun 24 04:55:21 PM PDT 24
Finished Jun 24 04:55:51 PM PDT 24
Peak memory 203424 kb
Host smart-9699629b-945b-4ad7-b0ac-8d2b19acd30b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2026147855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2026147855
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.4135632189
Short name T878
Test name
Test status
Simulation time 1753740266 ps
CPU time 41.09 seconds
Started Jun 24 04:55:24 PM PDT 24
Finished Jun 24 04:56:08 PM PDT 24
Peak memory 203352 kb
Host smart-bfab1da8-1f52-4037-ad04-284b5070c838
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4135632189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4135632189
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.95881028
Short name T380
Test name
Test status
Simulation time 185009075 ps
CPU time 10.28 seconds
Started Jun 24 04:55:25 PM PDT 24
Finished Jun 24 04:55:37 PM PDT 24
Peak memory 211588 kb
Host smart-26aba2cd-66f0-4aff-adb8-d93a4e9ffee4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95881028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.95881028
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.86964892
Short name T439
Test name
Test status
Simulation time 8456214028 ps
CPU time 54.71 seconds
Started Jun 24 04:55:27 PM PDT 24
Finished Jun 24 04:56:23 PM PDT 24
Peak memory 211612 kb
Host smart-aac87060-364d-4408-98ec-6dfb92d4f91d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=86964892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.86964892
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1980672212
Short name T647
Test name
Test status
Simulation time 19960078381 ps
CPU time 129.87 seconds
Started Jun 24 04:55:21 PM PDT 24
Finished Jun 24 04:57:33 PM PDT 24
Peak memory 204948 kb
Host smart-b66d9428-5368-44e8-b869-dfd057666a25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1980672212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1980672212
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1275391554
Short name T343
Test name
Test status
Simulation time 605430041 ps
CPU time 22.54 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:48 PM PDT 24
Peak memory 204596 kb
Host smart-b0fcda53-8ded-4070-8149-095c6422a839
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275391554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1275391554
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.1195633509
Short name T260
Test name
Test status
Simulation time 3230843273 ps
CPU time 27.56 seconds
Started Jun 24 04:55:24 PM PDT 24
Finished Jun 24 04:55:54 PM PDT 24
Peak memory 203420 kb
Host smart-df35d98b-518e-4d36-b7c7-f0cada0d345a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1195633509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1195633509
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.3594445640
Short name T716
Test name
Test status
Simulation time 383930033 ps
CPU time 3.07 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203384 kb
Host smart-5f0151ec-6172-405b-941e-29c3e627d77f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3594445640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3594445640
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1420147080
Short name T578
Test name
Test status
Simulation time 4267200318 ps
CPU time 25.66 seconds
Started Jun 24 04:55:20 PM PDT 24
Finished Jun 24 04:55:46 PM PDT 24
Peak memory 203404 kb
Host smart-d990946b-5818-45a4-922d-37162cb6bbe9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420147080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1420147080
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1292896371
Short name T7
Test name
Test status
Simulation time 3623046558 ps
CPU time 21.24 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:55:45 PM PDT 24
Peak memory 203456 kb
Host smart-400f038b-4dc7-425c-86fe-86128eb5b874
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1292896371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1292896371
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1015099179
Short name T525
Test name
Test status
Simulation time 34072306 ps
CPU time 2.17 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:55:26 PM PDT 24
Peak memory 203304 kb
Host smart-be4aeb7f-53f4-4960-87ad-0ac7ce90034a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015099179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1015099179
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1204590368
Short name T506
Test name
Test status
Simulation time 328868595 ps
CPU time 39.11 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:56:04 PM PDT 24
Peak memory 205040 kb
Host smart-a8acfafa-6435-422d-92d8-46a2ecec4543
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204590368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1204590368
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.942608506
Short name T585
Test name
Test status
Simulation time 1474207195 ps
CPU time 146.25 seconds
Started Jun 24 04:55:24 PM PDT 24
Finished Jun 24 04:57:53 PM PDT 24
Peak memory 209120 kb
Host smart-587aade8-742b-4393-89d0-5e8b435f3f7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=942608506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.942608506
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2908971966
Short name T31
Test name
Test status
Simulation time 549591836 ps
CPU time 207.82 seconds
Started Jun 24 04:55:25 PM PDT 24
Finished Jun 24 04:58:55 PM PDT 24
Peak memory 207992 kb
Host smart-ebfce54d-20af-4814-bc3f-048cc60800e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2908971966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.2908971966
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1352815723
Short name T27
Test name
Test status
Simulation time 473095171 ps
CPU time 221.78 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:59:08 PM PDT 24
Peak memory 211496 kb
Host smart-ce52a1dc-3cb9-463e-922b-a10748db550a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1352815723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1352815723
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2629111721
Short name T730
Test name
Test status
Simulation time 218618180 ps
CPU time 20.8 seconds
Started Jun 24 04:55:22 PM PDT 24
Finished Jun 24 04:55:46 PM PDT 24
Peak memory 211596 kb
Host smart-c21a1cf2-e6e8-4865-9f4a-ed86f7de722f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2629111721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2629111721
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2696749845
Short name T568
Test name
Test status
Simulation time 3786615294 ps
CPU time 64.27 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:56:40 PM PDT 24
Peak memory 205904 kb
Host smart-895f194a-2c75-4454-82c3-4ca83b42d937
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2696749845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2696749845
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1904632246
Short name T132
Test name
Test status
Simulation time 21291255023 ps
CPU time 126.11 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:57:41 PM PDT 24
Peak memory 211632 kb
Host smart-df50acde-df41-4264-8cbd-38f215bfc0bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1904632246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1904632246
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2589618322
Short name T832
Test name
Test status
Simulation time 288325807 ps
CPU time 13.65 seconds
Started Jun 24 04:55:38 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 203852 kb
Host smart-e1933e58-9bc8-4802-b4cf-65bb28a8bd2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2589618322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2589618322
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3922318087
Short name T339
Test name
Test status
Simulation time 115165483 ps
CPU time 12.48 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:55:45 PM PDT 24
Peak memory 203424 kb
Host smart-9c8fa169-1b75-42f5-9357-993d74d4eb88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3922318087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3922318087
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.284165584
Short name T125
Test name
Test status
Simulation time 527658552 ps
CPU time 25.15 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:56:02 PM PDT 24
Peak memory 211556 kb
Host smart-b1d105de-092e-4c54-b7d5-e0caf5daed22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284165584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.284165584
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1388527257
Short name T648
Test name
Test status
Simulation time 24099749093 ps
CPU time 146.81 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:58:00 PM PDT 24
Peak memory 211536 kb
Host smart-cc178fec-3651-4bdb-b05a-51daaddab720
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388527257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1388527257
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.4237679967
Short name T803
Test name
Test status
Simulation time 38759961255 ps
CPU time 227.05 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:59:22 PM PDT 24
Peak memory 211636 kb
Host smart-137ab158-8da8-4716-a682-539ea5cd4dc7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4237679967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4237679967
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3185197814
Short name T619
Test name
Test status
Simulation time 20675519 ps
CPU time 1.99 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:55:38 PM PDT 24
Peak memory 203312 kb
Host smart-a834c1cc-6c5e-485b-97a5-d32435ab2731
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185197814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3185197814
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3104530692
Short name T423
Test name
Test status
Simulation time 360356942 ps
CPU time 15.13 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:55:49 PM PDT 24
Peak memory 204152 kb
Host smart-66808759-02e1-49d7-89ea-c9850893db63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3104530692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3104530692
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.3091313331
Short name T187
Test name
Test status
Simulation time 131868334 ps
CPU time 3.29 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203396 kb
Host smart-0fe924f2-ebf1-4388-af4b-d7b5f3fe8e82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091313331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3091313331
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3753492206
Short name T527
Test name
Test status
Simulation time 11426452344 ps
CPU time 28.89 seconds
Started Jun 24 04:55:23 PM PDT 24
Finished Jun 24 04:55:54 PM PDT 24
Peak memory 203464 kb
Host smart-fd3a96b2-8c6d-418a-ad3b-502982d23d54
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753492206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3753492206
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1152689257
Short name T101
Test name
Test status
Simulation time 7324521421 ps
CPU time 32.37 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 203408 kb
Host smart-6d25cdb9-388a-4ff7-828c-caaf64597f20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1152689257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1152689257
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3135917070
Short name T457
Test name
Test status
Simulation time 39858411 ps
CPU time 2.2 seconds
Started Jun 24 04:55:19 PM PDT 24
Finished Jun 24 04:55:22 PM PDT 24
Peak memory 203392 kb
Host smart-db19b460-26ba-400e-a514-e7453ddb7b75
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135917070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3135917070
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.94447595
Short name T797
Test name
Test status
Simulation time 6141835615 ps
CPU time 109.67 seconds
Started Jun 24 04:55:34 PM PDT 24
Finished Jun 24 04:57:28 PM PDT 24
Peak memory 208200 kb
Host smart-03ae8536-67ae-493f-bd26-2e9fc8ca2575
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94447595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.94447595
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3471290223
Short name T242
Test name
Test status
Simulation time 4916999114 ps
CPU time 133.65 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:57:50 PM PDT 24
Peak memory 208044 kb
Host smart-0f00c052-683a-474b-9c78-f21c0eef94e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3471290223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3471290223
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3676817408
Short name T884
Test name
Test status
Simulation time 14100019177 ps
CPU time 584.9 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 05:05:17 PM PDT 24
Peak memory 210072 kb
Host smart-e801291d-2166-4111-b410-55d7c8d63459
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3676817408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.3676817408
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1996334471
Short name T715
Test name
Test status
Simulation time 847368702 ps
CPU time 8.89 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:55:46 PM PDT 24
Peak memory 211572 kb
Host smart-696e4a73-b05f-4476-8e00-f1a1ec38686e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1996334471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1996334471
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.204040726
Short name T592
Test name
Test status
Simulation time 2533001268 ps
CPU time 48.44 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:56:24 PM PDT 24
Peak memory 211552 kb
Host smart-651e4e9f-ff32-4264-bc8a-fa8b14065960
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=204040726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.204040726
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1380260146
Short name T758
Test name
Test status
Simulation time 78253692859 ps
CPU time 350.14 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 05:01:30 PM PDT 24
Peak memory 206940 kb
Host smart-8ed00e4e-41ad-4e04-b8f4-b2ff715320b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1380260146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.1380260146
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1189529329
Short name T116
Test name
Test status
Simulation time 56571155 ps
CPU time 3.37 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:55:38 PM PDT 24
Peak memory 203444 kb
Host smart-39c82ebf-eaed-4987-ac23-bbc4f134fefb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1189529329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1189529329
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2103316489
Short name T422
Test name
Test status
Simulation time 573212962 ps
CPU time 22.98 seconds
Started Jun 24 04:55:34 PM PDT 24
Finished Jun 24 04:56:00 PM PDT 24
Peak memory 203340 kb
Host smart-7c313331-d9fc-4b8d-9a69-c946fa51eff9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2103316489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2103316489
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.3732440782
Short name T769
Test name
Test status
Simulation time 3204760411 ps
CPU time 39.66 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 211572 kb
Host smart-1f3b1580-6fd0-4d80-b3b0-5b84ea64882c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3732440782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3732440782
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1236539452
Short name T499
Test name
Test status
Simulation time 29406535931 ps
CPU time 145.67 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:58:01 PM PDT 24
Peak memory 205072 kb
Host smart-f3f869f2-c9ad-4241-a3ba-84406f4c6de8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236539452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1236539452
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1727799039
Short name T301
Test name
Test status
Simulation time 57242898986 ps
CPU time 156.24 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:58:13 PM PDT 24
Peak memory 211652 kb
Host smart-2c0605a0-2d55-4e2c-b770-1198fa774d9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1727799039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1727799039
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3756508522
Short name T173
Test name
Test status
Simulation time 320115634 ps
CPU time 26.89 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:56:02 PM PDT 24
Peak memory 211560 kb
Host smart-daea8b63-63f3-4d24-b3fc-063681dc95d0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756508522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3756508522
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.3519159892
Short name T479
Test name
Test status
Simulation time 546992424 ps
CPU time 8.2 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 203876 kb
Host smart-da205028-7e51-45a0-a260-a31f95d0a000
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3519159892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3519159892
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.2786828374
Short name T337
Test name
Test status
Simulation time 33822569 ps
CPU time 1.95 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 203396 kb
Host smart-ec02a2a9-5277-4e10-9f62-8049a961f5a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2786828374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2786828374
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2765583171
Short name T810
Test name
Test status
Simulation time 8652124780 ps
CPU time 36.15 seconds
Started Jun 24 04:55:34 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203440 kb
Host smart-69391b55-a18f-4970-99a1-a546f35fc8eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765583171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2765583171
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3921055879
Short name T235
Test name
Test status
Simulation time 7827135863 ps
CPU time 33.91 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 203456 kb
Host smart-dc35fe4e-8541-49f3-8274-3140f91f9252
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3921055879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3921055879
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1465569206
Short name T854
Test name
Test status
Simulation time 27978106 ps
CPU time 2.07 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 203376 kb
Host smart-f3fa1a7d-1f0d-40fa-b95e-29e9ac6e5531
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465569206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1465569206
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.154573440
Short name T416
Test name
Test status
Simulation time 33082949784 ps
CPU time 476.86 seconds
Started Jun 24 04:55:30 PM PDT 24
Finished Jun 24 05:03:28 PM PDT 24
Peak memory 207620 kb
Host smart-91f20460-56ed-4f84-9bd3-47235c6800dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=154573440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.154573440
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.4265336437
Short name T492
Test name
Test status
Simulation time 446548865 ps
CPU time 35.96 seconds
Started Jun 24 04:55:34 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203976 kb
Host smart-3c116f25-b6a3-4695-9ef4-25ec87b7d6dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4265336437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.4265336437
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.979546202
Short name T252
Test name
Test status
Simulation time 2920761123 ps
CPU time 134.41 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:57:50 PM PDT 24
Peak memory 208628 kb
Host smart-c2b3faf4-c7d2-40d5-83b7-e38ec5335603
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=979546202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand
_reset.979546202
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1864972719
Short name T754
Test name
Test status
Simulation time 77694058 ps
CPU time 24.02 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:55:57 PM PDT 24
Peak memory 205964 kb
Host smart-9f28381a-3103-43b0-9ec5-05242e9413df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1864972719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.1864972719
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1498379416
Short name T338
Test name
Test status
Simulation time 477627885 ps
CPU time 5.03 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:55:41 PM PDT 24
Peak memory 204788 kb
Host smart-cf49b0de-fd32-4ed1-a0fc-760d7b9bbed8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1498379416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1498379416
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2595385440
Short name T408
Test name
Test status
Simulation time 1426376502 ps
CPU time 53.9 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:56:35 PM PDT 24
Peak memory 206288 kb
Host smart-9af83a28-89e0-4753-993a-25dbf91db7dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2595385440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2595385440
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3076546000
Short name T638
Test name
Test status
Simulation time 95621955559 ps
CPU time 420.62 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 05:02:42 PM PDT 24
Peak memory 206936 kb
Host smart-9e132320-dde2-4d12-ac71-92cd786239e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3076546000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.3076546000
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3635538726
Short name T386
Test name
Test status
Simulation time 453240057 ps
CPU time 17.52 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:55:57 PM PDT 24
Peak memory 203416 kb
Host smart-0b9e0930-7012-4110-9aa7-69260b2c916a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3635538726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3635538726
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.3489679909
Short name T888
Test name
Test status
Simulation time 1054335244 ps
CPU time 33.87 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203416 kb
Host smart-02bf2bae-6064-41c3-8f83-860b2e088a2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3489679909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3489679909
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.2462546107
Short name T624
Test name
Test status
Simulation time 925442872 ps
CPU time 18.87 seconds
Started Jun 24 04:55:34 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 211500 kb
Host smart-e547ee62-2d87-4beb-8dd5-5ad3df1b55ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2462546107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2462546107
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.696278331
Short name T875
Test name
Test status
Simulation time 40599304200 ps
CPU time 180.79 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:58:36 PM PDT 24
Peak memory 204724 kb
Host smart-747442d7-1722-4ce8-8c1a-815c3c9123d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=696278331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.696278331
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3314854184
Short name T750
Test name
Test status
Simulation time 33329035333 ps
CPU time 256.13 seconds
Started Jun 24 04:55:38 PM PDT 24
Finished Jun 24 04:59:58 PM PDT 24
Peak memory 204724 kb
Host smart-7ee32fb0-c4fd-4f5e-8713-2119b952c057
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3314854184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3314854184
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3451058547
Short name T570
Test name
Test status
Simulation time 135539970 ps
CPU time 13.69 seconds
Started Jun 24 04:55:38 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 204544 kb
Host smart-8aaf4e46-025a-460f-9da0-fafd9de7ff50
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451058547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3451058547
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.4206405015
Short name T316
Test name
Test status
Simulation time 1110534361 ps
CPU time 19.6 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:56:00 PM PDT 24
Peak memory 203868 kb
Host smart-76792f1b-1907-4cf2-87a2-3f319c161282
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206405015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4206405015
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.2645443735
Short name T465
Test name
Test status
Simulation time 253695777 ps
CPU time 3.94 seconds
Started Jun 24 04:55:33 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 203332 kb
Host smart-1f5c5833-abd2-4b41-b20c-c0215eff8f30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2645443735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2645443735
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2652262573
Short name T50
Test name
Test status
Simulation time 7057764404 ps
CPU time 30.2 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:56:10 PM PDT 24
Peak memory 203232 kb
Host smart-afa39157-7c59-421f-8c61-0d5e68abfc5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652262573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2652262573
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2819108836
Short name T540
Test name
Test status
Simulation time 13627180824 ps
CPU time 26.66 seconds
Started Jun 24 04:55:32 PM PDT 24
Finished Jun 24 04:56:02 PM PDT 24
Peak memory 203416 kb
Host smart-76ae371d-2a3c-43a4-89f9-84634fe5610b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2819108836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2819108836
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.207716207
Short name T897
Test name
Test status
Simulation time 28150730 ps
CPU time 2.38 seconds
Started Jun 24 04:55:31 PM PDT 24
Finished Jun 24 04:55:36 PM PDT 24
Peak memory 203312 kb
Host smart-54dc9ecd-5d05-4276-8996-9a1da7523bfa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207716207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.207716207
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.468631986
Short name T425
Test name
Test status
Simulation time 7187697142 ps
CPU time 148.55 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:58:09 PM PDT 24
Peak memory 208644 kb
Host smart-35dcac6e-e5a7-4597-8250-f0f0ae73ded3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=468631986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.468631986
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1628019727
Short name T153
Test name
Test status
Simulation time 1131943846 ps
CPU time 36.63 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:56:18 PM PDT 24
Peak memory 203416 kb
Host smart-0f71677f-13df-4230-8554-510a08e3f028
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1628019727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1628019727
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.89268589
Short name T775
Test name
Test status
Simulation time 265556967 ps
CPU time 91.12 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:57:12 PM PDT 24
Peak memory 208036 kb
Host smart-54cd8851-e2d0-42d2-a307-bfc7fb5299ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89268589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_
reset.89268589
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2235753801
Short name T531
Test name
Test status
Simulation time 1303680927 ps
CPU time 79.83 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:57:00 PM PDT 24
Peak memory 208972 kb
Host smart-a71e802f-143a-4158-943a-ba7f41a0e28e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2235753801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2235753801
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.748339604
Short name T536
Test name
Test status
Simulation time 44912932 ps
CPU time 2.41 seconds
Started Jun 24 04:55:34 PM PDT 24
Finished Jun 24 04:55:41 PM PDT 24
Peak memory 203668 kb
Host smart-38a3c717-4ffc-43cc-bd74-41525e1cda88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748339604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.748339604
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.912980912
Short name T323
Test name
Test status
Simulation time 807163554 ps
CPU time 26.53 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:56:07 PM PDT 24
Peak memory 204448 kb
Host smart-99eb5b4c-8cb0-4855-9971-94e4a1373a55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912980912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.912980912
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3129391346
Short name T268
Test name
Test status
Simulation time 75502218811 ps
CPU time 635.14 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 05:06:15 PM PDT 24
Peak memory 205652 kb
Host smart-13da3411-86c9-4695-98fc-70f36b6944e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3129391346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3129391346
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2488268930
Short name T674
Test name
Test status
Simulation time 194085972 ps
CPU time 14.75 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:55:55 PM PDT 24
Peak memory 203316 kb
Host smart-566f3c19-ce6e-48f0-a352-038d25d8f346
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2488268930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2488268930
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.969921587
Short name T542
Test name
Test status
Simulation time 522070091 ps
CPU time 14.19 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 203420 kb
Host smart-b0acd17c-1377-4db5-9096-c47dcbc4b2e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=969921587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.969921587
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.1467954355
Short name T78
Test name
Test status
Simulation time 484308226 ps
CPU time 20.38 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:56:01 PM PDT 24
Peak memory 204404 kb
Host smart-43ecad8a-5275-47d1-8329-b1dd38c331e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1467954355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1467954355
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3198253097
Short name T719
Test name
Test status
Simulation time 5976214697 ps
CPU time 36.44 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 204500 kb
Host smart-8f66c633-97b5-4b0e-a7c9-cfbd7a5d6206
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198253097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3198253097
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2093445658
Short name T38
Test name
Test status
Simulation time 16113172954 ps
CPU time 87.31 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:57:08 PM PDT 24
Peak memory 211648 kb
Host smart-fda600f6-66f7-41cd-b587-ed6fa33ac2be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2093445658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2093445658
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.58665072
Short name T402
Test name
Test status
Simulation time 58145814 ps
CPU time 4.61 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:55:46 PM PDT 24
Peak memory 211556 kb
Host smart-02ed861e-14de-4f5f-a04b-303d7a8e35a8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58665072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.58665072
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.3054569833
Short name T419
Test name
Test status
Simulation time 161261859 ps
CPU time 10.43 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:55:50 PM PDT 24
Peak memory 203848 kb
Host smart-42b567ea-e2db-425b-9906-aa5d7628fa99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3054569833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3054569833
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.3339093937
Short name T332
Test name
Test status
Simulation time 624128655 ps
CPU time 3.23 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 203388 kb
Host smart-7ec9404e-7b9f-4209-a68a-e88a7cefe195
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3339093937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3339093937
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.4002440798
Short name T396
Test name
Test status
Simulation time 11911693518 ps
CPU time 32.88 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203460 kb
Host smart-273db38a-d2cb-4385-a1ec-2ff1f206b519
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002440798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4002440798
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2228868387
Short name T448
Test name
Test status
Simulation time 5156050405 ps
CPU time 33.14 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203436 kb
Host smart-fc3b9032-e848-4266-9708-6e46f629f8e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2228868387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2228868387
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3370999408
Short name T279
Test name
Test status
Simulation time 33962416 ps
CPU time 2.39 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:55:42 PM PDT 24
Peak memory 203320 kb
Host smart-4d21c411-ac2b-42b5-b5da-47e9844bdcd7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370999408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3370999408
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.612726093
Short name T809
Test name
Test status
Simulation time 36281419663 ps
CPU time 254.16 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:59:55 PM PDT 24
Peak memory 209772 kb
Host smart-df2c4950-2249-4c88-a6de-fa4acec6163d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=612726093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.612726093
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1544893716
Short name T308
Test name
Test status
Simulation time 179437942 ps
CPU time 3.53 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:55:42 PM PDT 24
Peak memory 203408 kb
Host smart-9e76975d-8df7-4506-980d-3a37012d90f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1544893716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1544893716
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2193927941
Short name T704
Test name
Test status
Simulation time 2272763627 ps
CPU time 238.76 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:59:40 PM PDT 24
Peak memory 210872 kb
Host smart-612bfa7d-293b-4632-92dc-9e04796c0788
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193927941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2193927941
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3669336820
Short name T881
Test name
Test status
Simulation time 3875931389 ps
CPU time 488.98 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 05:03:50 PM PDT 24
Peak memory 228016 kb
Host smart-969b9a3d-a78b-476b-bcf1-54f83cc7cb4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3669336820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3669336820
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2251073175
Short name T885
Test name
Test status
Simulation time 406900625 ps
CPU time 4.35 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:55:45 PM PDT 24
Peak memory 211568 kb
Host smart-33e624a2-0ab6-4656-9542-bf73d7da633b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2251073175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2251073175
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2732309658
Short name T668
Test name
Test status
Simulation time 114498325 ps
CPU time 4.23 seconds
Started Jun 24 04:55:46 PM PDT 24
Finished Jun 24 04:55:52 PM PDT 24
Peak memory 202660 kb
Host smart-5a57fe0e-18e7-49ff-8012-2fb23ed1315c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2732309658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2732309658
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1516406844
Short name T517
Test name
Test status
Simulation time 73703113496 ps
CPU time 506.49 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 05:04:12 PM PDT 24
Peak memory 211636 kb
Host smart-7be2f6b6-5723-4e00-8312-53a41dba20ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1516406844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.1516406844
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3189952437
Short name T516
Test name
Test status
Simulation time 51904765 ps
CPU time 7.15 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:55:52 PM PDT 24
Peak memory 203320 kb
Host smart-803eede3-10a8-4dfb-80b3-c48eaf4090d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3189952437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3189952437
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.2454522564
Short name T395
Test name
Test status
Simulation time 1727272661 ps
CPU time 34.86 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 04:56:19 PM PDT 24
Peak memory 203352 kb
Host smart-3d956367-e781-4c57-a9e0-9cbcf8888319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2454522564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2454522564
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.3653854304
Short name T253
Test name
Test status
Simulation time 3240995285 ps
CPU time 40.75 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:56:23 PM PDT 24
Peak memory 204512 kb
Host smart-15b7ae2b-5e9c-4358-9503-8b288a19ae63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3653854304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3653854304
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3664039025
Short name T394
Test name
Test status
Simulation time 113480450326 ps
CPU time 238.24 seconds
Started Jun 24 04:55:41 PM PDT 24
Finished Jun 24 04:59:41 PM PDT 24
Peak memory 211644 kb
Host smart-c2e02992-1451-4d0c-87fd-691c17dbdd8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664039025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3664039025
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1758160278
Short name T20
Test name
Test status
Simulation time 24741612273 ps
CPU time 200.88 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:59:07 PM PDT 24
Peak memory 211828 kb
Host smart-70a72132-a533-4441-92a1-ab3eff824f79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1758160278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1758160278
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.332653750
Short name T655
Test name
Test status
Simulation time 179805415 ps
CPU time 24.46 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 211584 kb
Host smart-1d3ffa75-622f-4fcd-a898-50e85847c53a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332653750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.332653750
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.2722896326
Short name T438
Test name
Test status
Simulation time 1133993310 ps
CPU time 22.61 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:56:10 PM PDT 24
Peak memory 203452 kb
Host smart-95d4527d-03ee-48e2-ab3d-e73675416b74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2722896326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2722896326
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3310141780
Short name T534
Test name
Test status
Simulation time 329318872 ps
CPU time 3.62 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:55:42 PM PDT 24
Peak memory 203392 kb
Host smart-1bf60b87-091c-482c-8160-1f2bf943ad74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3310141780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3310141780
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2253705821
Short name T606
Test name
Test status
Simulation time 6537946358 ps
CPU time 31.49 seconds
Started Jun 24 04:55:35 PM PDT 24
Finished Jun 24 04:56:11 PM PDT 24
Peak memory 203436 kb
Host smart-75695a5b-5417-4efc-9c06-1d42ab1c0d2c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253705821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2253705821
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3009260429
Short name T627
Test name
Test status
Simulation time 6605769803 ps
CPU time 30.45 seconds
Started Jun 24 04:55:37 PM PDT 24
Finished Jun 24 04:56:12 PM PDT 24
Peak memory 203468 kb
Host smart-78f268e9-e048-4cf1-8549-34febcfebc29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3009260429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3009260429
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2908608384
Short name T359
Test name
Test status
Simulation time 36623177 ps
CPU time 2.49 seconds
Started Jun 24 04:55:36 PM PDT 24
Finished Jun 24 04:55:43 PM PDT 24
Peak memory 203304 kb
Host smart-cbf10121-ddd4-4713-97f2-1114d11e1dbf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908608384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2908608384
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.4190926145
Short name T393
Test name
Test status
Simulation time 12313970808 ps
CPU time 232.43 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:59:38 PM PDT 24
Peak memory 211640 kb
Host smart-56b1567b-95b0-4381-8311-9b3ac85014fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4190926145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4190926145
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3208996345
Short name T501
Test name
Test status
Simulation time 295654270 ps
CPU time 8.01 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:55:55 PM PDT 24
Peak memory 203424 kb
Host smart-fdbf2801-7901-4f8c-b85d-8283e7a06a3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3208996345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3208996345
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.456348770
Short name T399
Test name
Test status
Simulation time 430141565 ps
CPU time 198.87 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 04:59:03 PM PDT 24
Peak memory 208492 kb
Host smart-b795a29d-2203-408a-9f38-41d99a4fc152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=456348770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand
_reset.456348770
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.503168139
Short name T670
Test name
Test status
Simulation time 1274284233 ps
CPU time 185.28 seconds
Started Jun 24 04:55:47 PM PDT 24
Finished Jun 24 04:58:54 PM PDT 24
Peak memory 211588 kb
Host smart-674f3442-2c19-4e69-a375-03ff9ea512af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=503168139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.503168139
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1792280193
Short name T493
Test name
Test status
Simulation time 46561628 ps
CPU time 4.67 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:55:52 PM PDT 24
Peak memory 204828 kb
Host smart-65003450-2c5d-4be3-8517-19c52d6ec00e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1792280193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1792280193
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2819290177
Short name T248
Test name
Test status
Simulation time 523741758 ps
CPU time 17.14 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:31 PM PDT 24
Peak memory 204548 kb
Host smart-f1c01830-f93a-411b-8493-388c0b5cb1c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819290177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2819290177
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.822336
Short name T267
Test name
Test status
Simulation time 398540430632 ps
CPU time 909.72 seconds
Started Jun 24 04:54:15 PM PDT 24
Finished Jun 24 05:09:33 PM PDT 24
Peak memory 211664 kb
Host smart-a882cb51-6a86-431e-a39c-e4e036553309
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=822336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.822336
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2649431868
Short name T593
Test name
Test status
Simulation time 478239803 ps
CPU time 8.32 seconds
Started Jun 24 04:54:15 PM PDT 24
Finished Jun 24 04:54:27 PM PDT 24
Peak memory 203440 kb
Host smart-d6afbfbc-49f5-4657-8cc0-fee881181347
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2649431868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2649431868
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3405741689
Short name T24
Test name
Test status
Simulation time 753178093 ps
CPU time 16.49 seconds
Started Jun 24 04:54:23 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203336 kb
Host smart-e74d9135-0db3-469d-af26-c066a36bdd95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3405741689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3405741689
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.772423252
Short name T710
Test name
Test status
Simulation time 977993424 ps
CPU time 38.29 seconds
Started Jun 24 04:54:06 PM PDT 24
Finished Jun 24 04:54:49 PM PDT 24
Peak memory 204932 kb
Host smart-4d59ff3a-8ed6-4ccb-a01d-531a1793b6a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=772423252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.772423252
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2125081045
Short name T807
Test name
Test status
Simulation time 11394671507 ps
CPU time 62.95 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:55:16 PM PDT 24
Peak memory 204676 kb
Host smart-6ce20185-9ada-40df-b612-78fa83d0b997
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125081045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2125081045
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1559626368
Short name T538
Test name
Test status
Simulation time 41904104702 ps
CPU time 103.2 seconds
Started Jun 24 04:54:18 PM PDT 24
Finished Jun 24 04:56:04 PM PDT 24
Peak memory 204976 kb
Host smart-a6ed28fe-1b21-47d7-b532-ff938087a1ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1559626368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1559626368
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2322028776
Short name T766
Test name
Test status
Simulation time 226448309 ps
CPU time 27.19 seconds
Started Jun 24 04:54:18 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 211540 kb
Host smart-0fc6f6b6-56a6-4d32-a060-f038c63f96c9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322028776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2322028776
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.1667668159
Short name T641
Test name
Test status
Simulation time 1547100008 ps
CPU time 13.49 seconds
Started Jun 24 04:54:05 PM PDT 24
Finished Jun 24 04:54:23 PM PDT 24
Peak memory 203240 kb
Host smart-8fa051ef-40ad-44a5-a927-c28d1911a289
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1667668159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1667668159
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.624858261
Short name T498
Test name
Test status
Simulation time 179924232 ps
CPU time 3.56 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:54:21 PM PDT 24
Peak memory 203392 kb
Host smart-e79315be-7f42-4e77-9c22-8867afcda3f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=624858261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.624858261
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3448758201
Short name T281
Test name
Test status
Simulation time 39856543312 ps
CPU time 40.11 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203448 kb
Host smart-c07e167a-e51b-41e7-820c-4534d8e080a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448758201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3448758201
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1221042408
Short name T129
Test name
Test status
Simulation time 7710725304 ps
CPU time 28.64 seconds
Started Jun 24 04:54:07 PM PDT 24
Finished Jun 24 04:54:40 PM PDT 24
Peak memory 203436 kb
Host smart-86783dda-2171-4152-b55e-fd9f638f679d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1221042408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1221042408
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1483930846
Short name T600
Test name
Test status
Simulation time 67457104 ps
CPU time 2.14 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:54:15 PM PDT 24
Peak memory 203388 kb
Host smart-49fef01d-be94-48fb-9f1b-fd9b5f72ba35
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483930846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1483930846
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1229090902
Short name T733
Test name
Test status
Simulation time 1177058347 ps
CPU time 33.48 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 205652 kb
Host smart-c349c1c8-740d-457a-8085-0932f0e930f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1229090902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1229090902
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.273465418
Short name T804
Test name
Test status
Simulation time 834613169 ps
CPU time 67.42 seconds
Started Jun 24 04:53:59 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 205268 kb
Host smart-e03977db-3635-4f9f-b46c-2a95be1ed910
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273465418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.273465418
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1497409005
Short name T569
Test name
Test status
Simulation time 111790177 ps
CPU time 26.53 seconds
Started Jun 24 04:54:05 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 206604 kb
Host smart-3d1a43ae-75a3-43c4-a5a0-701d4e7dae10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1497409005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.1497409005
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2739656181
Short name T483
Test name
Test status
Simulation time 3093947492 ps
CPU time 378.56 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 05:00:27 PM PDT 24
Peak memory 220048 kb
Host smart-7fb88b01-0ff2-4fc3-93a3-dc06a7ef74bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739656181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.2739656181
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1542400938
Short name T663
Test name
Test status
Simulation time 713937510 ps
CPU time 16.33 seconds
Started Jun 24 04:54:23 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 211508 kb
Host smart-6de2ae73-4ce6-4fb1-a171-7b57ba203ce4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1542400938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1542400938
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4248378000
Short name T336
Test name
Test status
Simulation time 4684302584 ps
CPU time 31.17 seconds
Started Jun 24 04:55:41 PM PDT 24
Finished Jun 24 04:56:15 PM PDT 24
Peak memory 211592 kb
Host smart-2e6c801f-82e4-473a-aa3a-d3c8b192e193
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4248378000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4248378000
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.190382740
Short name T126
Test name
Test status
Simulation time 82302375044 ps
CPU time 753.7 seconds
Started Jun 24 04:55:41 PM PDT 24
Finished Jun 24 05:08:17 PM PDT 24
Peak memory 211652 kb
Host smart-8e3083cc-5398-45f0-805b-e740b22fbf66
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=190382740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.190382740
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.686756454
Short name T368
Test name
Test status
Simulation time 175053315 ps
CPU time 12.2 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:55:59 PM PDT 24
Peak memory 203356 kb
Host smart-07b9bcef-3cda-46d4-9b08-db0df368ad8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=686756454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.686756454
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.827037468
Short name T862
Test name
Test status
Simulation time 492303870 ps
CPU time 16.51 seconds
Started Jun 24 04:55:46 PM PDT 24
Finished Jun 24 04:56:05 PM PDT 24
Peak memory 202524 kb
Host smart-5a7a8694-1303-496f-a7d4-b73aaa00e5c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=827037468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.827037468
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.70641541
Short name T558
Test name
Test status
Simulation time 1220541145 ps
CPU time 36.2 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:56:23 PM PDT 24
Peak memory 211580 kb
Host smart-e35df6f1-034d-4886-a3a9-73e243a5788e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70641541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.70641541
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1470445266
Short name T201
Test name
Test status
Simulation time 27825927435 ps
CPU time 125.37 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:57:52 PM PDT 24
Peak memory 205032 kb
Host smart-140fed5d-a53b-4106-92f4-320146b2a86c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470445266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1470445266
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.4104928087
Short name T405
Test name
Test status
Simulation time 7316423013 ps
CPU time 46.41 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:56:32 PM PDT 24
Peak memory 211644 kb
Host smart-e4b716a7-16e0-422b-81ec-6e5da4a25b81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4104928087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4104928087
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2609603618
Short name T848
Test name
Test status
Simulation time 64160077 ps
CPU time 5.21 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:55:51 PM PDT 24
Peak memory 211540 kb
Host smart-67d13480-9438-40dc-965c-a27bd6709544
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609603618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2609603618
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2836140014
Short name T455
Test name
Test status
Simulation time 6592837141 ps
CPU time 25.08 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 04:56:09 PM PDT 24
Peak memory 211576 kb
Host smart-485d0e7b-846b-4d9b-941b-f51bab67bb57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836140014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2836140014
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.553883523
Short name T55
Test name
Test status
Simulation time 245956151 ps
CPU time 3.21 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:55:48 PM PDT 24
Peak memory 203368 kb
Host smart-d49158e4-f5d5-4efb-b7cf-77c13d4ce812
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=553883523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.553883523
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2132942181
Short name T238
Test name
Test status
Simulation time 14640887349 ps
CPU time 35.84 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:56:21 PM PDT 24
Peak memory 203464 kb
Host smart-7bfd2f04-0845-437a-b27a-970040e06ee0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132942181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2132942181
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1356837677
Short name T44
Test name
Test status
Simulation time 3377542273 ps
CPU time 25.81 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:56:13 PM PDT 24
Peak memory 203400 kb
Host smart-911a71bd-a520-43c9-9556-a1a3056508f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1356837677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1356837677
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.4007069749
Short name T154
Test name
Test status
Simulation time 97424288 ps
CPU time 2.36 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 04:55:47 PM PDT 24
Peak memory 203384 kb
Host smart-97c011cd-e560-4849-88d0-2455318a6820
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007069749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.4007069749
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.940667694
Short name T200
Test name
Test status
Simulation time 788212486 ps
CPU time 100.59 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:57:26 PM PDT 24
Peak memory 206760 kb
Host smart-2f74b247-a98d-43ac-a833-5d1e71ad5fe5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=940667694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.940667694
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.495209477
Short name T748
Test name
Test status
Simulation time 6474246 ps
CPU time 0.83 seconds
Started Jun 24 04:55:46 PM PDT 24
Finished Jun 24 04:55:49 PM PDT 24
Peak memory 195180 kb
Host smart-90356f9d-e700-41c9-831d-8a9c87eb1ced
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=495209477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.495209477
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.909322381
Short name T889
Test name
Test status
Simulation time 456266906 ps
CPU time 173.71 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:58:40 PM PDT 24
Peak memory 208344 kb
Host smart-7976a4f2-f3fc-41ac-868d-40a0265bffbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=909322381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand
_reset.909322381
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.419385733
Short name T437
Test name
Test status
Simulation time 1171647224 ps
CPU time 312.86 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 05:00:57 PM PDT 24
Peak memory 219716 kb
Host smart-b56e132f-945e-425e-85d9-e94a6e8f0784
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=419385733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res
et_error.419385733
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2079019546
Short name T137
Test name
Test status
Simulation time 131182452 ps
CPU time 5.13 seconds
Started Jun 24 04:55:43 PM PDT 24
Finished Jun 24 04:55:51 PM PDT 24
Peak memory 211568 kb
Host smart-44840217-aacf-4db4-b429-c9ff9f8a9164
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2079019546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2079019546
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.761202267
Short name T763
Test name
Test status
Simulation time 205076591 ps
CPU time 11.78 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:55:58 PM PDT 24
Peak memory 211588 kb
Host smart-ee17b237-2c69-4dad-b6f7-8f4299439546
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=761202267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.761202267
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2681861156
Short name T874
Test name
Test status
Simulation time 103182048197 ps
CPU time 635.94 seconds
Started Jun 24 04:55:41 PM PDT 24
Finished Jun 24 05:06:19 PM PDT 24
Peak memory 211652 kb
Host smart-cea39de8-1b3c-4254-88f7-3d76098415d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2681861156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.2681861156
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4005671857
Short name T69
Test name
Test status
Simulation time 3257452589 ps
CPU time 20.32 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 04:56:11 PM PDT 24
Peak memory 203404 kb
Host smart-8e38e2ed-7540-4b35-8d24-e2d34c146edb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005671857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4005671857
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.1740163839
Short name T533
Test name
Test status
Simulation time 198618504 ps
CPU time 18.06 seconds
Started Jun 24 04:55:47 PM PDT 24
Finished Jun 24 04:56:07 PM PDT 24
Peak memory 203420 kb
Host smart-1ab43f6f-7f45-4612-a0a5-f86ea009958f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1740163839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1740163839
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.592299755
Short name T42
Test name
Test status
Simulation time 206954719 ps
CPU time 2.62 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 04:55:47 PM PDT 24
Peak memory 203668 kb
Host smart-01ed3e6a-09b3-4d6d-8c30-f56ccfba662c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=592299755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.592299755
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2056060369
Short name T233
Test name
Test status
Simulation time 48862202948 ps
CPU time 139.44 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:58:07 PM PDT 24
Peak memory 211660 kb
Host smart-3481bbfd-8c11-4822-aa1a-130ee240e8ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056060369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2056060369
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1934638064
Short name T111
Test name
Test status
Simulation time 15942780466 ps
CPU time 133.8 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:58:01 PM PDT 24
Peak memory 204796 kb
Host smart-ae647e6f-e700-4e3a-aa10-cf21d6d08984
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1934638064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1934638064
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1558264691
Short name T868
Test name
Test status
Simulation time 131924831 ps
CPU time 17.05 seconds
Started Jun 24 04:55:46 PM PDT 24
Finished Jun 24 04:56:05 PM PDT 24
Peak memory 211552 kb
Host smart-e35af137-923a-46c4-8558-2019e7d785df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558264691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1558264691
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.1658623584
Short name T605
Test name
Test status
Simulation time 436930369 ps
CPU time 7.42 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:55:53 PM PDT 24
Peak memory 203964 kb
Host smart-c0fdd77d-f118-46f5-ad66-b0ec42da671c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658623584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1658623584
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1101908713
Short name T57
Test name
Test status
Simulation time 149568902 ps
CPU time 2.77 seconds
Started Jun 24 04:55:44 PM PDT 24
Finished Jun 24 04:55:49 PM PDT 24
Peak memory 203340 kb
Host smart-bbe47c1b-768d-4843-8c64-b03e1708d0ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1101908713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1101908713
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.85294808
Short name T785
Test name
Test status
Simulation time 6720827175 ps
CPU time 29.88 seconds
Started Jun 24 04:55:45 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 203380 kb
Host smart-2d5d2484-00e5-4cdf-accc-7bf970a33a72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=85294808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.85294808
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2281775969
Short name T283
Test name
Test status
Simulation time 2764862276 ps
CPU time 24.77 seconds
Started Jun 24 04:55:46 PM PDT 24
Finished Jun 24 04:56:12 PM PDT 24
Peak memory 203460 kb
Host smart-01aba92e-de46-45f5-82a7-da4d6c063546
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2281775969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2281775969
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2409112243
Short name T686
Test name
Test status
Simulation time 32668928 ps
CPU time 2.06 seconds
Started Jun 24 04:55:42 PM PDT 24
Finished Jun 24 04:55:46 PM PDT 24
Peak memory 203268 kb
Host smart-3e417946-800d-419a-91f2-a4c178afaae2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409112243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2409112243
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.345309052
Short name T446
Test name
Test status
Simulation time 2952871550 ps
CPU time 113.4 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:57:47 PM PDT 24
Peak memory 207616 kb
Host smart-037308bb-677a-4524-ad20-9c81a0115808
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=345309052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.345309052
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.281001599
Short name T358
Test name
Test status
Simulation time 5164718450 ps
CPU time 123.3 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:57:56 PM PDT 24
Peak memory 205584 kb
Host smart-57c54dd1-40bb-4d49-b1ee-bd1cc95abb41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=281001599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.281001599
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4206484463
Short name T634
Test name
Test status
Simulation time 1477284252 ps
CPU time 240.56 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:59:59 PM PDT 24
Peak memory 211608 kb
Host smart-3fb17753-2c85-4cbb-b840-d3adfac4c807
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206484463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.4206484463
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2595504210
Short name T473
Test name
Test status
Simulation time 13177821330 ps
CPU time 457.66 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 05:03:29 PM PDT 24
Peak memory 219864 kb
Host smart-3bdadb4f-3cba-4246-8686-aefada647158
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2595504210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2595504210
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2124523458
Short name T783
Test name
Test status
Simulation time 420920955 ps
CPU time 6.67 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:00 PM PDT 24
Peak memory 211520 kb
Host smart-4304beac-ac3b-4586-85cb-68dde9fcccc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124523458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2124523458
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1981947179
Short name T331
Test name
Test status
Simulation time 2118139521 ps
CPU time 63.01 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:56:56 PM PDT 24
Peak memory 205344 kb
Host smart-86939418-a863-4a92-afd2-9c5cb401df9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1981947179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1981947179
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2500533854
Short name T266
Test name
Test status
Simulation time 128208122938 ps
CPU time 579.4 seconds
Started Jun 24 04:55:53 PM PDT 24
Finished Jun 24 05:05:34 PM PDT 24
Peak memory 207320 kb
Host smart-61cb8628-8d78-4f95-9950-90e9218669b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2500533854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.2500533854
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3485766533
Short name T630
Test name
Test status
Simulation time 788361327 ps
CPU time 26.11 seconds
Started Jun 24 04:55:53 PM PDT 24
Finished Jun 24 04:56:20 PM PDT 24
Peak memory 203420 kb
Host smart-eaed79d5-0e39-4e82-a86e-20b01a844fd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3485766533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3485766533
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.1792590730
Short name T573
Test name
Test status
Simulation time 492678404 ps
CPU time 8.63 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:01 PM PDT 24
Peak memory 203376 kb
Host smart-47b6a9e1-f729-4f23-a9cd-df91542f6d1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1792590730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1792590730
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2463263604
Short name T581
Test name
Test status
Simulation time 4111901650 ps
CPU time 34.19 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:56:33 PM PDT 24
Peak memory 204872 kb
Host smart-38b5d461-e961-4729-a402-9f4ada546ba0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2463263604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2463263604
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3831417413
Short name T725
Test name
Test status
Simulation time 45288639675 ps
CPU time 199.2 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:59:12 PM PDT 24
Peak memory 211636 kb
Host smart-a9d9ee46-48d3-44e1-b32d-c3eed1cd7d57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831417413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3831417413
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2897158147
Short name T751
Test name
Test status
Simulation time 8249650941 ps
CPU time 18.02 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:11 PM PDT 24
Peak memory 203388 kb
Host smart-e7a95e3e-3596-48dc-a9bc-28066896fac5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2897158147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2897158147
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.435071626
Short name T833
Test name
Test status
Simulation time 225785967 ps
CPU time 22.85 seconds
Started Jun 24 04:55:55 PM PDT 24
Finished Jun 24 04:56:19 PM PDT 24
Peak memory 211476 kb
Host smart-0217a5ff-f808-4a16-b710-d4defd823c0b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435071626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.435071626
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.176242587
Short name T309
Test name
Test status
Simulation time 559467243 ps
CPU time 11.27 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:56:05 PM PDT 24
Peak memory 203424 kb
Host smart-c0288180-6442-472a-b176-6fcd3bfac9c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=176242587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.176242587
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.408175375
Short name T142
Test name
Test status
Simulation time 167838050 ps
CPU time 3.85 seconds
Started Jun 24 04:55:53 PM PDT 24
Finished Jun 24 04:55:58 PM PDT 24
Peak memory 203660 kb
Host smart-61dc44e8-c3a4-4bf8-b5f2-e3349c01940c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=408175375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.408175375
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3049486795
Short name T288
Test name
Test status
Simulation time 5799997280 ps
CPU time 31.99 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:25 PM PDT 24
Peak memory 203464 kb
Host smart-a5321dc8-ecf8-4bb8-b1fc-808317ea19e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049486795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3049486795
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3393223426
Short name T566
Test name
Test status
Simulation time 13583415802 ps
CPU time 34.44 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:28 PM PDT 24
Peak memory 203380 kb
Host smart-78d9eaf8-2e9b-47a7-a704-d90615f2c089
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3393223426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3393223426
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2351460827
Short name T667
Test name
Test status
Simulation time 74754045 ps
CPU time 2.31 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 203392 kb
Host smart-e30ae102-ac17-4825-8d9d-95bd826c6bcf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351460827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2351460827
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2542585706
Short name T518
Test name
Test status
Simulation time 9198719276 ps
CPU time 195.01 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:59:07 PM PDT 24
Peak memory 207312 kb
Host smart-83b96e6a-6e23-4fd8-9428-906c5ad8858a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2542585706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2542585706
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3559103357
Short name T561
Test name
Test status
Simulation time 91098011 ps
CPU time 9.16 seconds
Started Jun 24 04:55:55 PM PDT 24
Finished Jun 24 04:56:05 PM PDT 24
Peak memory 203328 kb
Host smart-f1aca227-b862-4061-a4e7-b1610dc94d02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3559103357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3559103357
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3533587051
Short name T440
Test name
Test status
Simulation time 181359367 ps
CPU time 80.79 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:57:15 PM PDT 24
Peak memory 208256 kb
Host smart-80933cbb-07e4-40c2-b334-0ae06a75ab22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3533587051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.3533587051
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1566230498
Short name T572
Test name
Test status
Simulation time 1262492252 ps
CPU time 288.66 seconds
Started Jun 24 04:55:49 PM PDT 24
Finished Jun 24 05:00:39 PM PDT 24
Peak memory 211516 kb
Host smart-add2e3f7-8447-477d-9162-f4aaea89c06a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1566230498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.1566230498
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2231300688
Short name T96
Test name
Test status
Simulation time 739001944 ps
CPU time 23.76 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 211592 kb
Host smart-2ed19708-79a6-4535-aadf-f0909dfd4308
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2231300688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2231300688
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3197638926
Short name T147
Test name
Test status
Simulation time 7187442726 ps
CPU time 46.59 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 04:56:39 PM PDT 24
Peak memory 211664 kb
Host smart-82d436f0-560b-429f-b839-6a10051644ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3197638926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3197638926
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1572228014
Short name T124
Test name
Test status
Simulation time 78045506811 ps
CPU time 628.93 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 05:06:28 PM PDT 24
Peak memory 211628 kb
Host smart-461aee72-c776-494a-9796-8be35c1f328c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1572228014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1572228014
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1954447417
Short name T273
Test name
Test status
Simulation time 1667815771 ps
CPU time 15.56 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 203644 kb
Host smart-430becbb-b9f5-4b63-9103-45c5d6ab5f5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954447417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1954447417
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.2592885210
Short name T350
Test name
Test status
Simulation time 316598773 ps
CPU time 14.47 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 203336 kb
Host smart-7ca4847d-6ed8-4db8-b5c9-fd3a84121b34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2592885210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2592885210
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.762869853
Short name T564
Test name
Test status
Simulation time 989838788 ps
CPU time 33.26 seconds
Started Jun 24 04:55:55 PM PDT 24
Finished Jun 24 04:56:30 PM PDT 24
Peak memory 204916 kb
Host smart-d73afccd-3fef-4aca-94ab-021b01400dd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=762869853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.762869853
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1301201071
Short name T360
Test name
Test status
Simulation time 37556434993 ps
CPU time 142.49 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:58:16 PM PDT 24
Peak memory 205148 kb
Host smart-8488e6d8-5418-40ab-859a-01589fc62a96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301201071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1301201071
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2780815119
Short name T227
Test name
Test status
Simulation time 6677286776 ps
CPU time 29.26 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:56:23 PM PDT 24
Peak memory 211880 kb
Host smart-634393e8-84b6-4c1e-b80a-4d8bba2aba3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2780815119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2780815119
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1972441242
Short name T737
Test name
Test status
Simulation time 155637570 ps
CPU time 16.78 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:18 PM PDT 24
Peak memory 211580 kb
Host smart-44b56170-f8b0-4cdb-af4c-5833733c0585
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972441242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1972441242
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.3863205221
Short name T371
Test name
Test status
Simulation time 238467262 ps
CPU time 6.69 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:56:00 PM PDT 24
Peak memory 204124 kb
Host smart-a56054c5-8332-4d00-94cb-52b6d34c573b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3863205221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3863205221
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3918988150
Short name T701
Test name
Test status
Simulation time 142851172 ps
CPU time 3.86 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:55:57 PM PDT 24
Peak memory 203320 kb
Host smart-a1e05b07-98b1-4d8e-a916-ab7403fc5cb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3918988150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3918988150
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3921015412
Short name T800
Test name
Test status
Simulation time 9280614184 ps
CPU time 39.34 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 04:56:31 PM PDT 24
Peak memory 203472 kb
Host smart-cb6d6ab5-8363-4051-bec4-ec34b364d1df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921015412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3921015412
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1997100912
Short name T792
Test name
Test status
Simulation time 2406471701 ps
CPU time 22 seconds
Started Jun 24 04:55:55 PM PDT 24
Finished Jun 24 04:56:18 PM PDT 24
Peak memory 203372 kb
Host smart-a38d6ff9-4934-480a-a2ae-859c6aafc847
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1997100912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1997100912
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.878265127
Short name T509
Test name
Test status
Simulation time 64811855 ps
CPU time 2.21 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:55:56 PM PDT 24
Peak memory 203384 kb
Host smart-7b122d4b-3bcd-490a-875b-beda05167b3a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878265127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.878265127
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1225324168
Short name T94
Test name
Test status
Simulation time 7131319495 ps
CPU time 244.67 seconds
Started Jun 24 04:55:50 PM PDT 24
Finished Jun 24 04:59:57 PM PDT 24
Peak memory 211660 kb
Host smart-ae6e04d0-7867-45dd-bc62-21b7788c49c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1225324168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1225324168
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3343373841
Short name T317
Test name
Test status
Simulation time 22197212060 ps
CPU time 203.44 seconds
Started Jun 24 04:55:52 PM PDT 24
Finished Jun 24 04:59:17 PM PDT 24
Peak memory 206828 kb
Host smart-6c77075e-7ec6-49ef-9f85-d961318f56ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3343373841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3343373841
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1394240156
Short name T617
Test name
Test status
Simulation time 38396006 ps
CPU time 17.28 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 205352 kb
Host smart-f87f0a5c-9a03-4f18-af88-e06cb0a14d11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394240156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.1394240156
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2760937793
Short name T688
Test name
Test status
Simulation time 19336772712 ps
CPU time 331.49 seconds
Started Jun 24 04:55:49 PM PDT 24
Finished Jun 24 05:01:22 PM PDT 24
Peak memory 221824 kb
Host smart-46f691eb-1b3b-4220-b180-43b0988bc8ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2760937793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.2760937793
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3142460431
Short name T398
Test name
Test status
Simulation time 969200724 ps
CPU time 23.04 seconds
Started Jun 24 04:55:51 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 204988 kb
Host smart-db9666b0-1bd2-4750-89b4-c13583be7a34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3142460431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3142460431
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1356745559
Short name T202
Test name
Test status
Simulation time 187920069 ps
CPU time 18.62 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:21 PM PDT 24
Peak memory 211600 kb
Host smart-01fbf214-4e73-4696-942a-9d778d19b5dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1356745559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1356745559
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.659504605
Short name T114
Test name
Test status
Simulation time 49102184740 ps
CPU time 221.55 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:59:40 PM PDT 24
Peak memory 211652 kb
Host smart-726ad4ab-34c1-4262-9848-75e9572643be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=659504605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo
w_rsp.659504605
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.379325624
Short name T148
Test name
Test status
Simulation time 904887887 ps
CPU time 28.33 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:29 PM PDT 24
Peak memory 203420 kb
Host smart-90e45f2c-cae0-4efc-94af-2082c7405145
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=379325624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.379325624
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3646631098
Short name T652
Test name
Test status
Simulation time 368828405 ps
CPU time 10.92 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:56:10 PM PDT 24
Peak memory 203432 kb
Host smart-97fa5276-ee14-4bd8-a86e-2767abdad117
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3646631098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3646631098
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2192454624
Short name T184
Test name
Test status
Simulation time 3568509486 ps
CPU time 27.67 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:56:27 PM PDT 24
Peak memory 211576 kb
Host smart-8d5e18e4-ac3b-4008-98e8-667a8f03ff2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2192454624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2192454624
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3206309916
Short name T678
Test name
Test status
Simulation time 104795956834 ps
CPU time 238.1 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 05:00:01 PM PDT 24
Peak memory 211636 kb
Host smart-ba80f4f9-1ec5-48f6-a3bc-cd77211a2b95
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206309916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3206309916
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4183449941
Short name T12
Test name
Test status
Simulation time 8945156403 ps
CPU time 25.14 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:28 PM PDT 24
Peak memory 203476 kb
Host smart-a0b32b5e-6689-4a14-9cab-974d0a6b99a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4183449941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4183449941
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.217272891
Short name T771
Test name
Test status
Simulation time 262085295 ps
CPU time 14.98 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 211572 kb
Host smart-5926a0ef-d1d4-4b7a-97be-2e1db227ccd5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217272891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.217272891
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.3886906233
Short name T859
Test name
Test status
Simulation time 2523475865 ps
CPU time 31.8 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:56:33 PM PDT 24
Peak memory 204120 kb
Host smart-54b268df-f747-4bb5-8cd7-04054380ddfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3886906233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3886906233
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1832232970
Short name T278
Test name
Test status
Simulation time 27966296 ps
CPU time 2.15 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:56:03 PM PDT 24
Peak memory 203304 kb
Host smart-2565a5e5-c2e8-4bae-a1ee-13cb5196642c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1832232970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1832232970
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2638341184
Short name T591
Test name
Test status
Simulation time 12774071751 ps
CPU time 47.74 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:56:48 PM PDT 24
Peak memory 203380 kb
Host smart-93afcfb7-af1e-4636-a458-5114e0e892dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2638341184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2638341184
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2672218054
Short name T241
Test name
Test status
Simulation time 73100695 ps
CPU time 2.36 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:56:01 PM PDT 24
Peak memory 203268 kb
Host smart-6f44c576-01d3-4f6a-a0ff-1d7315a2c5dd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672218054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2672218054
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1834694841
Short name T694
Test name
Test status
Simulation time 11776845841 ps
CPU time 170.41 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:58:53 PM PDT 24
Peak memory 210004 kb
Host smart-3d1198d1-6eb5-465e-b442-f9ced3c6a5ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1834694841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1834694841
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1454548307
Short name T871
Test name
Test status
Simulation time 2524222390 ps
CPU time 89.35 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:57:31 PM PDT 24
Peak memory 211564 kb
Host smart-7b57ab36-5771-4090-b2d3-43c6ca554b37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1454548307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1454548307
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.289973565
Short name T776
Test name
Test status
Simulation time 252764729 ps
CPU time 104.75 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:57:45 PM PDT 24
Peak memory 209528 kb
Host smart-340a9ef5-2620-46e4-b221-d2bcb5e98daf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=289973565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res
et_error.289973565
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.186429167
Short name T364
Test name
Test status
Simulation time 579426749 ps
CPU time 21.85 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:23 PM PDT 24
Peak memory 211832 kb
Host smart-faa9669c-9e24-4447-b2b3-b85d86926afb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=186429167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.186429167
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.824832987
Short name T640
Test name
Test status
Simulation time 37707195 ps
CPU time 5.21 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:07 PM PDT 24
Peak memory 203824 kb
Host smart-2451967b-506f-4810-bc68-9d702f0f1b97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=824832987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.824832987
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.542797785
Short name T770
Test name
Test status
Simulation time 30714138224 ps
CPU time 234.82 seconds
Started Jun 24 04:56:01 PM PDT 24
Finished Jun 24 04:59:58 PM PDT 24
Peak memory 211620 kb
Host smart-4ff9ff9b-d10e-4d3e-8d21-1dd672482cd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=542797785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo
w_rsp.542797785
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4046045584
Short name T318
Test name
Test status
Simulation time 907954452 ps
CPU time 7.41 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:09 PM PDT 24
Peak memory 203676 kb
Host smart-df830e50-6cfa-42ea-a7ea-159021efc5c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046045584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4046045584
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.3292989059
Short name T778
Test name
Test status
Simulation time 1333373202 ps
CPU time 29.93 seconds
Started Jun 24 04:55:57 PM PDT 24
Finished Jun 24 04:56:28 PM PDT 24
Peak memory 203300 kb
Host smart-fc020bae-b109-42cb-9ab6-a3b9b749584f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3292989059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3292989059
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.588442714
Short name T424
Test name
Test status
Simulation time 229420625 ps
CPU time 26.07 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:29 PM PDT 24
Peak memory 205000 kb
Host smart-a0f236a7-4db3-4657-aa87-35cb842f28fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=588442714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.588442714
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2522285157
Short name T107
Test name
Test status
Simulation time 87748655505 ps
CPU time 160.24 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:58:43 PM PDT 24
Peak memory 204768 kb
Host smart-8696aca6-9d13-4e89-8cf8-70b7b8e41770
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522285157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2522285157
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.4217326253
Short name T157
Test name
Test status
Simulation time 7288316639 ps
CPU time 43.16 seconds
Started Jun 24 04:56:06 PM PDT 24
Finished Jun 24 04:56:50 PM PDT 24
Peak memory 211588 kb
Host smart-411e474f-363f-48a7-8054-29093ffdf1d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4217326253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.4217326253
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.730266500
Short name T601
Test name
Test status
Simulation time 62860300 ps
CPU time 6.36 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:09 PM PDT 24
Peak memory 211572 kb
Host smart-08519a1d-f836-4e89-9afd-cfe6b6a8d7fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730266500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.730266500
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.1667548628
Short name T261
Test name
Test status
Simulation time 1554016347 ps
CPU time 35.72 seconds
Started Jun 24 04:56:01 PM PDT 24
Finished Jun 24 04:56:39 PM PDT 24
Peak memory 203468 kb
Host smart-76ea0348-4fa3-4395-ac74-8a9acd78621b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1667548628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1667548628
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.3285641454
Short name T590
Test name
Test status
Simulation time 41161994 ps
CPU time 2.21 seconds
Started Jun 24 04:56:01 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 203388 kb
Host smart-3a9ac536-e70c-4f73-82ac-759009d37ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3285641454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3285641454
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2532501552
Short name T177
Test name
Test status
Simulation time 6489043777 ps
CPU time 30.13 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:32 PM PDT 24
Peak memory 203712 kb
Host smart-8c5be070-eb16-4e74-863e-c9bae00555e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532501552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2532501552
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1607416776
Short name T383
Test name
Test status
Simulation time 4850958787 ps
CPU time 29.22 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:31 PM PDT 24
Peak memory 203452 kb
Host smart-bde090bf-aa10-4bed-bf83-91640a95bad9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1607416776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1607416776
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.624968870
Short name T286
Test name
Test status
Simulation time 35770435 ps
CPU time 2.69 seconds
Started Jun 24 04:56:02 PM PDT 24
Finished Jun 24 04:56:06 PM PDT 24
Peak memory 203376 kb
Host smart-1d556cb7-9d22-4e1a-8e4b-04db3bc2b2ee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624968870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.624968870
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1683995243
Short name T816
Test name
Test status
Simulation time 776023862 ps
CPU time 92.95 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:57:36 PM PDT 24
Peak memory 208812 kb
Host smart-6aca6bbf-34a5-4e9c-a280-087eaaf3d520
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683995243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1683995243
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2402982937
Short name T28
Test name
Test status
Simulation time 2026520146 ps
CPU time 51.47 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:54 PM PDT 24
Peak memory 204500 kb
Host smart-5d5edf44-47a8-4bdf-b670-9472db0fa754
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2402982937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2402982937
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1814441782
Short name T130
Test name
Test status
Simulation time 12459108880 ps
CPU time 324.47 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 05:01:25 PM PDT 24
Peak memory 209616 kb
Host smart-7f2449a5-0826-4791-a6a5-8c162394990f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1814441782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1814441782
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3031307427
Short name T99
Test name
Test status
Simulation time 620209212 ps
CPU time 151.06 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:58:33 PM PDT 24
Peak memory 210096 kb
Host smart-7cb757af-5591-4f49-bde5-1b9c648b5196
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3031307427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.3031307427
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.821417125
Short name T362
Test name
Test status
Simulation time 142400504 ps
CPU time 17.76 seconds
Started Jun 24 04:55:59 PM PDT 24
Finished Jun 24 04:56:19 PM PDT 24
Peak memory 205000 kb
Host smart-ce0c9c4a-ea6b-44fb-b4aa-fa62069dfe15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=821417125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.821417125
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.653425612
Short name T873
Test name
Test status
Simulation time 1290872529 ps
CPU time 34.9 seconds
Started Jun 24 04:56:05 PM PDT 24
Finished Jun 24 04:56:41 PM PDT 24
Peak memory 211536 kb
Host smart-49a69aa3-6a89-4635-965d-b64843b24d29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=653425612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.653425612
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1865878452
Short name T609
Test name
Test status
Simulation time 6754668825 ps
CPU time 57.78 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:57:10 PM PDT 24
Peak memory 211640 kb
Host smart-86db7163-8166-46c2-a013-17241a191277
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1865878452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.1865878452
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3632566975
Short name T535
Test name
Test status
Simulation time 384403414 ps
CPU time 12.92 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:56:25 PM PDT 24
Peak memory 203328 kb
Host smart-d102f823-0bcf-43b4-89bc-4a37717c4b17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3632566975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3632566975
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.4272944655
Short name T122
Test name
Test status
Simulation time 202806724 ps
CPU time 6.66 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 203424 kb
Host smart-7c02df82-6913-4f72-a4b6-7ada8e1f4f3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4272944655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4272944655
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.3344340189
Short name T895
Test name
Test status
Simulation time 66061398 ps
CPU time 6.6 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:09 PM PDT 24
Peak memory 211556 kb
Host smart-ad045400-5191-4c63-801c-3e9b53594255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3344340189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3344340189
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3463121406
Short name T512
Test name
Test status
Simulation time 214139968793 ps
CPU time 286.34 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 05:00:49 PM PDT 24
Peak memory 205692 kb
Host smart-15a13e36-bdd1-4b66-bf12-9a20e1f30037
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463121406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3463121406
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4247114667
Short name T504
Test name
Test status
Simulation time 6312818652 ps
CPU time 41.22 seconds
Started Jun 24 04:56:01 PM PDT 24
Finished Jun 24 04:56:45 PM PDT 24
Peak memory 204716 kb
Host smart-f93f815b-2d69-4761-980a-593f77b2adb2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4247114667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.4247114667
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3904923971
Short name T374
Test name
Test status
Simulation time 446071394 ps
CPU time 25.52 seconds
Started Jun 24 04:56:05 PM PDT 24
Finished Jun 24 04:56:31 PM PDT 24
Peak memory 205068 kb
Host smart-e1d837e1-b887-4bd3-8f0b-b924ee726c66
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904923971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3904923971
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.2726349988
Short name T413
Test name
Test status
Simulation time 6059168894 ps
CPU time 24 seconds
Started Jun 24 04:56:12 PM PDT 24
Finished Jun 24 04:56:39 PM PDT 24
Peak memory 211656 kb
Host smart-3f36aa5a-e278-4752-a5bf-bb6abb51dbcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2726349988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2726349988
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.2701580593
Short name T835
Test name
Test status
Simulation time 363187275 ps
CPU time 3.85 seconds
Started Jun 24 04:56:00 PM PDT 24
Finished Jun 24 04:56:07 PM PDT 24
Peak memory 203392 kb
Host smart-bebc3295-1044-4e9e-9c3f-af3faee4a932
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2701580593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2701580593
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.894974434
Short name T491
Test name
Test status
Simulation time 7325871998 ps
CPU time 37.12 seconds
Started Jun 24 04:56:02 PM PDT 24
Finished Jun 24 04:56:41 PM PDT 24
Peak memory 203436 kb
Host smart-b009b862-9790-44d9-b25e-7a0b3f8c84f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=894974434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.894974434
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.667384599
Short name T207
Test name
Test status
Simulation time 16785456581 ps
CPU time 34.13 seconds
Started Jun 24 04:55:58 PM PDT 24
Finished Jun 24 04:56:34 PM PDT 24
Peak memory 203448 kb
Host smart-dd9d9eb3-8285-4f2d-92d6-96d8841f6f5d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=667384599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.667384599
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.589594891
Short name T73
Test name
Test status
Simulation time 26958579 ps
CPU time 2.24 seconds
Started Jun 24 04:56:05 PM PDT 24
Finished Jun 24 04:56:08 PM PDT 24
Peak memory 203340 kb
Host smart-0f4fb882-3762-4cf1-aac8-c601dff9e5ab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589594891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.589594891
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1361132310
Short name T131
Test name
Test status
Simulation time 17501567272 ps
CPU time 214.78 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:59:43 PM PDT 24
Peak memory 209468 kb
Host smart-f4ed3b64-0ba2-4ff1-bf87-368d2fc06b6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1361132310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1361132310
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.965234082
Short name T117
Test name
Test status
Simulation time 1122264499 ps
CPU time 16.92 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:27 PM PDT 24
Peak memory 203420 kb
Host smart-b00581c4-c801-40f3-8311-04a55991e9e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=965234082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.965234082
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2158685055
Short name T74
Test name
Test status
Simulation time 1406751621 ps
CPU time 198.56 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:59:30 PM PDT 24
Peak memory 211556 kb
Host smart-ba757476-d2cf-4d8b-a894-64e0f5598700
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2158685055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.2158685055
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.296685897
Short name T743
Test name
Test status
Simulation time 2954075781 ps
CPU time 326.21 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 05:01:40 PM PDT 24
Peak memory 211660 kb
Host smart-9d5c3a50-113b-422c-8dfc-a705c5c880de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=296685897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res
et_error.296685897
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1552629539
Short name T661
Test name
Test status
Simulation time 1035673570 ps
CPU time 27.35 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:41 PM PDT 24
Peak memory 205172 kb
Host smart-40c54092-413b-4db9-9aae-e891317e8671
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1552629539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1552629539
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1815142427
Short name T689
Test name
Test status
Simulation time 2597251299 ps
CPU time 34.87 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:56:43 PM PDT 24
Peak memory 211636 kb
Host smart-497c054f-a4f6-42f5-a529-f366db517792
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1815142427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1815142427
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1108347981
Short name T576
Test name
Test status
Simulation time 56176166866 ps
CPU time 528.43 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 211568 kb
Host smart-1b7ed1d6-7d13-4ad5-9228-92584f38464e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1108347981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.1108347981
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4106568857
Short name T727
Test name
Test status
Simulation time 129905317 ps
CPU time 3.66 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:18 PM PDT 24
Peak memory 203412 kb
Host smart-35d2eb9f-6627-4d68-8e2e-e7a9386057b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4106568857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4106568857
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.3233476983
Short name T168
Test name
Test status
Simulation time 54843820 ps
CPU time 3.14 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 203668 kb
Host smart-5d8748c1-cfaf-43ee-9966-e183cb30de70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3233476983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3233476983
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.3782058490
Short name T315
Test name
Test status
Simulation time 547782843 ps
CPU time 11.38 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:26 PM PDT 24
Peak memory 211556 kb
Host smart-7df5cddc-9b1a-43e0-9da7-c107fbde5688
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3782058490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3782058490
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.4035753900
Short name T307
Test name
Test status
Simulation time 37815912248 ps
CPU time 98.25 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:57:49 PM PDT 24
Peak memory 211564 kb
Host smart-5242e88b-a1d5-482d-acf5-4c702c69e6bd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035753900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.4035753900
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2988780736
Short name T588
Test name
Test status
Simulation time 1538042966 ps
CPU time 12.54 seconds
Started Jun 24 04:56:10 PM PDT 24
Finished Jun 24 04:56:25 PM PDT 24
Peak memory 203964 kb
Host smart-ad8c9126-2fad-4f91-b706-df095b5a7df9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2988780736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2988780736
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2653657771
Short name T365
Test name
Test status
Simulation time 297805653 ps
CPU time 10.51 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:56:22 PM PDT 24
Peak memory 211764 kb
Host smart-1e8f9cdf-52f6-4094-a8d0-4aaa894003e3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653657771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2653657771
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.2801364451
Short name T275
Test name
Test status
Simulation time 191886183 ps
CPU time 4.47 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:15 PM PDT 24
Peak memory 203420 kb
Host smart-acf28892-be0a-4397-aa15-9f1c9f3d8134
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2801364451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2801364451
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.40856496
Short name T352
Test name
Test status
Simulation time 166386678 ps
CPU time 4.13 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203372 kb
Host smart-72c8c655-e229-4310-bf7e-fabb6c01b9e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40856496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.40856496
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2455944980
Short name T176
Test name
Test status
Simulation time 25826381149 ps
CPU time 41.35 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:51 PM PDT 24
Peak memory 203468 kb
Host smart-4cf69746-862e-480f-bd66-baa3bdeb2c39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455944980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2455944980
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.91675246
Short name T373
Test name
Test status
Simulation time 3710239463 ps
CPU time 21.76 seconds
Started Jun 24 04:56:12 PM PDT 24
Finished Jun 24 04:56:36 PM PDT 24
Peak memory 203448 kb
Host smart-0ea6fa73-b7f3-4b0e-a00f-7d39293b2ab1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=91675246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.91675246
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3822761961
Short name T762
Test name
Test status
Simulation time 27595920 ps
CPU time 2.47 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:11 PM PDT 24
Peak memory 203308 kb
Host smart-0f75342d-3e74-41f7-b188-4c20894d2cd2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822761961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3822761961
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2573798557
Short name T324
Test name
Test status
Simulation time 200645259 ps
CPU time 19.45 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:56:30 PM PDT 24
Peak memory 205840 kb
Host smart-74003205-c0b8-444e-a88e-4ed261fb8518
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2573798557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2573798557
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3224530777
Short name T856
Test name
Test status
Simulation time 2347468006 ps
CPU time 48.69 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:59 PM PDT 24
Peak memory 205404 kb
Host smart-597452f5-6f01-423f-9ab1-a728f3d5b132
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3224530777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3224530777
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4064353532
Short name T736
Test name
Test status
Simulation time 78343439 ps
CPU time 21.72 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:32 PM PDT 24
Peak memory 205640 kb
Host smart-1ca80472-401d-404d-9ab7-12893274dc13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4064353532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.4064353532
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2101575795
Short name T829
Test name
Test status
Simulation time 59279771 ps
CPU time 7.72 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:18 PM PDT 24
Peak memory 211472 kb
Host smart-a9cf5210-264f-4eec-b3b6-c787ee1634c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2101575795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2101575795
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3789352148
Short name T693
Test name
Test status
Simulation time 1735785419 ps
CPU time 57.12 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:57:07 PM PDT 24
Peak memory 211504 kb
Host smart-b62d01a1-9c24-4caa-892e-7c28d2d5c5e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3789352148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3789352148
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3732709187
Short name T226
Test name
Test status
Simulation time 73629463823 ps
CPU time 371.83 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 05:02:22 PM PDT 24
Peak memory 211652 kb
Host smart-c651b203-cf55-4360-85a5-73461b295d7d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3732709187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.3732709187
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.220983279
Short name T1
Test name
Test status
Simulation time 163256431 ps
CPU time 15.58 seconds
Started Jun 24 04:56:06 PM PDT 24
Finished Jun 24 04:56:22 PM PDT 24
Peak memory 204000 kb
Host smart-22563f47-e6f9-4669-8e70-b179fc701ced
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=220983279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.220983279
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.2413681292
Short name T892
Test name
Test status
Simulation time 23304282 ps
CPU time 1.82 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 203420 kb
Host smart-ee33cc0d-adbf-4f8f-a1e1-bedfca927da9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2413681292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2413681292
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.139260447
Short name T839
Test name
Test status
Simulation time 76991929 ps
CPU time 7.39 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:22 PM PDT 24
Peak memory 211580 kb
Host smart-60217365-3cce-439e-b542-18ab55b9ebb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=139260447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.139260447
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1456366680
Short name T724
Test name
Test status
Simulation time 41550331921 ps
CPU time 201.91 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:59:30 PM PDT 24
Peak memory 204968 kb
Host smart-5ae7c005-e08d-424b-93be-fa2c83e20fe4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456366680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1456366680
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.6535201
Short name T76
Test name
Test status
Simulation time 16783090994 ps
CPU time 100.15 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:57:50 PM PDT 24
Peak memory 204788 kb
Host smart-2918d8a6-4ee0-4e6c-9358-fee4b4d515bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=6535201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.6535201
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.220567805
Short name T375
Test name
Test status
Simulation time 257680575 ps
CPU time 21.96 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:35 PM PDT 24
Peak memory 211580 kb
Host smart-3c95ac88-c0ef-429c-9840-e7fdb41d1518
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220567805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.220567805
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.3674199633
Short name T764
Test name
Test status
Simulation time 4438719357 ps
CPU time 19.33 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:34 PM PDT 24
Peak memory 204500 kb
Host smart-89c48f89-09ae-4f1e-8ac7-267a1fec3533
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3674199633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3674199633
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.663070149
Short name T870
Test name
Test status
Simulation time 24700922 ps
CPU time 2.17 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:11 PM PDT 24
Peak memory 203392 kb
Host smart-9bf60313-8c0f-48f0-911f-5cfb31d272be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663070149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.663070149
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2853470206
Short name T784
Test name
Test status
Simulation time 5785402282 ps
CPU time 29.73 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:56:38 PM PDT 24
Peak memory 203388 kb
Host smart-caea96bd-f4f8-4b59-981d-d8a4215285ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853470206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2853470206
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.562209825
Short name T869
Test name
Test status
Simulation time 5355308157 ps
CPU time 25.11 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:56:36 PM PDT 24
Peak memory 203456 kb
Host smart-f26790a6-b64c-4822-aca4-beb4c6a0ee3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=562209825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.562209825
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4263714792
Short name T798
Test name
Test status
Simulation time 67659075 ps
CPU time 2.59 seconds
Started Jun 24 04:56:08 PM PDT 24
Finished Jun 24 04:56:13 PM PDT 24
Peak memory 203400 kb
Host smart-7b782a97-99c4-40f6-9390-827331792af5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263714792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.4263714792
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1752294877
Short name T71
Test name
Test status
Simulation time 895559536 ps
CPU time 78.9 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:57:28 PM PDT 24
Peak memory 208104 kb
Host smart-2cf94b31-70f4-49ae-9dfe-0e496f14110c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752294877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1752294877
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.841826624
Short name T347
Test name
Test status
Simulation time 12196315960 ps
CPU time 185.88 seconds
Started Jun 24 04:56:06 PM PDT 24
Finished Jun 24 04:59:13 PM PDT 24
Peak memory 207968 kb
Host smart-3d6c6555-f0b2-4410-9c74-4109482b9c6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=841826624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.841826624
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2888352817
Short name T817
Test name
Test status
Simulation time 5729865971 ps
CPU time 366.66 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 05:02:18 PM PDT 24
Peak memory 208924 kb
Host smart-8d5fc717-467a-48de-b07d-bb0c92285322
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2888352817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.2888352817
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2184240583
Short name T136
Test name
Test status
Simulation time 1774250148 ps
CPU time 187.01 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:59:16 PM PDT 24
Peak memory 210188 kb
Host smart-76e91698-3263-429c-bd12-896160009079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2184240583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.2184240583
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3158389045
Short name T894
Test name
Test status
Simulation time 281197486 ps
CPU time 8.85 seconds
Started Jun 24 04:56:06 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 204640 kb
Host smart-cb66afad-7bf4-4afc-ad2a-d8fd8463246e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3158389045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3158389045
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2064834065
Short name T64
Test name
Test status
Simulation time 785812087 ps
CPU time 47.01 seconds
Started Jun 24 04:56:18 PM PDT 24
Finished Jun 24 04:57:07 PM PDT 24
Peak memory 204864 kb
Host smart-bc4454a7-69c1-4422-a810-4160a909c4d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2064834065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2064834065
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1469024850
Short name T135
Test name
Test status
Simulation time 50893819742 ps
CPU time 325.18 seconds
Started Jun 24 04:56:14 PM PDT 24
Finished Jun 24 05:01:42 PM PDT 24
Peak memory 211624 kb
Host smart-0a0127ac-b45a-4c76-819c-5570740f44f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1469024850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.1469024850
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1650018559
Short name T808
Test name
Test status
Simulation time 107535797 ps
CPU time 14.7 seconds
Started Jun 24 04:56:17 PM PDT 24
Finished Jun 24 04:56:35 PM PDT 24
Peak memory 203400 kb
Host smart-5b07be5c-65f8-41d2-97d6-aced182f6c83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1650018559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1650018559
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.4063562174
Short name T488
Test name
Test status
Simulation time 2852407710 ps
CPU time 19.51 seconds
Started Jun 24 04:56:15 PM PDT 24
Finished Jun 24 04:56:38 PM PDT 24
Peak memory 203404 kb
Host smart-8c2ef1da-a777-4d1b-ab9c-0c23a429ea38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4063562174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4063562174
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.3597605520
Short name T631
Test name
Test status
Simulation time 180708242 ps
CPU time 20.97 seconds
Started Jun 24 04:56:17 PM PDT 24
Finished Jun 24 04:56:41 PM PDT 24
Peak memory 211768 kb
Host smart-f790762e-5414-461c-9a55-fcfa65be8224
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3597605520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3597605520
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2134261181
Short name T191
Test name
Test status
Simulation time 36185138438 ps
CPU time 89 seconds
Started Jun 24 04:56:14 PM PDT 24
Finished Jun 24 04:57:46 PM PDT 24
Peak memory 204840 kb
Host smart-48d02935-4258-40b9-8d7d-5398aaaf85d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134261181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2134261181
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1965281119
Short name T780
Test name
Test status
Simulation time 25416588699 ps
CPU time 106.52 seconds
Started Jun 24 04:56:18 PM PDT 24
Finished Jun 24 04:58:07 PM PDT 24
Peak memory 211676 kb
Host smart-626a1b66-f1e0-4c74-a4c2-ae0a54bd2ffd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1965281119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1965281119
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2934790825
Short name T637
Test name
Test status
Simulation time 315983240 ps
CPU time 29.5 seconds
Started Jun 24 04:56:17 PM PDT 24
Finished Jun 24 04:56:49 PM PDT 24
Peak memory 204372 kb
Host smart-f0a88e47-42ab-4626-93c8-22d23f69d91a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934790825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2934790825
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.2488378275
Short name T861
Test name
Test status
Simulation time 3671949089 ps
CPU time 31.92 seconds
Started Jun 24 04:56:13 PM PDT 24
Finished Jun 24 04:56:48 PM PDT 24
Peak memory 203456 kb
Host smart-2a0c0c38-a610-4f7d-b110-72656cb9ccac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2488378275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2488378275
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.2590040876
Short name T773
Test name
Test status
Simulation time 155003158 ps
CPU time 3.1 seconds
Started Jun 24 04:56:11 PM PDT 24
Finished Jun 24 04:56:17 PM PDT 24
Peak memory 203396 kb
Host smart-57890a3e-fbfd-4fda-8af2-039b0be2544c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2590040876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2590040876
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3017925641
Short name T453
Test name
Test status
Simulation time 11135290759 ps
CPU time 33.81 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:56:46 PM PDT 24
Peak memory 203440 kb
Host smart-09e028ae-7a2a-4688-a89f-569b0bdbbd03
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017925641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3017925641
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2365139937
Short name T604
Test name
Test status
Simulation time 6742119998 ps
CPU time 27.54 seconds
Started Jun 24 04:56:07 PM PDT 24
Finished Jun 24 04:56:37 PM PDT 24
Peak memory 203436 kb
Host smart-313b0385-479c-4c8b-962c-e536eb5da052
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2365139937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2365139937
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1576937053
Short name T451
Test name
Test status
Simulation time 126330357 ps
CPU time 2.42 seconds
Started Jun 24 04:56:09 PM PDT 24
Finished Jun 24 04:56:14 PM PDT 24
Peak memory 203380 kb
Host smart-7d25ae82-f7e9-4d1f-9f82-1b8c1be9d013
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576937053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1576937053
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2432536825
Short name T752
Test name
Test status
Simulation time 1118215761 ps
CPU time 29.7 seconds
Started Jun 24 04:56:18 PM PDT 24
Finished Jun 24 04:56:50 PM PDT 24
Peak memory 205512 kb
Host smart-335e3e44-2e73-424f-8124-2785e18b9de5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2432536825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2432536825
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1642366485
Short name T432
Test name
Test status
Simulation time 276891308 ps
CPU time 36.08 seconds
Started Jun 24 04:56:13 PM PDT 24
Finished Jun 24 04:56:52 PM PDT 24
Peak memory 203644 kb
Host smart-cd8f4d0d-b6d2-4cc4-91a8-5c736c01ec9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1642366485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1642366485
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1125846313
Short name T815
Test name
Test status
Simulation time 2439039382 ps
CPU time 348.74 seconds
Started Jun 24 04:56:15 PM PDT 24
Finished Jun 24 05:02:07 PM PDT 24
Peak memory 211000 kb
Host smart-9b1db693-89f4-4859-80da-df69219684fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1125846313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1125846313
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2323483628
Short name T15
Test name
Test status
Simulation time 448623534 ps
CPU time 128.43 seconds
Started Jun 24 04:56:17 PM PDT 24
Finished Jun 24 04:58:28 PM PDT 24
Peak memory 210280 kb
Host smart-7a9027e1-147c-438d-b667-64eb463a4053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2323483628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.2323483628
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2807324892
Short name T427
Test name
Test status
Simulation time 12159523 ps
CPU time 1.73 seconds
Started Jun 24 04:56:15 PM PDT 24
Finished Jun 24 04:56:20 PM PDT 24
Peak memory 203412 kb
Host smart-14d0c6f7-a1d7-4e81-9c50-3ed1b719672d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2807324892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2807324892
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2205367581
Short name T467
Test name
Test status
Simulation time 55275876 ps
CPU time 10.47 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:54:24 PM PDT 24
Peak memory 211512 kb
Host smart-9899a4eb-7048-421f-85ee-7ef08df3e889
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2205367581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2205367581
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1889754661
Short name T786
Test name
Test status
Simulation time 9965526974 ps
CPU time 84.08 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:55:40 PM PDT 24
Peak memory 204764 kb
Host smart-9b239e96-36d0-4ad3-9a10-20bce914b900
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1889754661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.1889754661
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4269550093
Short name T409
Test name
Test status
Simulation time 2187069724 ps
CPU time 31.49 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:50 PM PDT 24
Peak memory 211572 kb
Host smart-5befc61c-a16a-474e-af49-5d100bd83f8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4269550093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4269550093
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.4183337944
Short name T857
Test name
Test status
Simulation time 379527416 ps
CPU time 20.76 seconds
Started Jun 24 04:54:06 PM PDT 24
Finished Jun 24 04:54:31 PM PDT 24
Peak memory 203444 kb
Host smart-ebb64b75-70fe-4b1e-b070-d2aea47841c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4183337944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4183337944
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.1000876382
Short name T611
Test name
Test status
Simulation time 965630328 ps
CPU time 19.13 seconds
Started Jun 24 04:54:07 PM PDT 24
Finished Jun 24 04:54:31 PM PDT 24
Peak memory 211564 kb
Host smart-fb6b8e88-2735-43e2-bdfa-754b027cb7ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1000876382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1000876382
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3900339280
Short name T659
Test name
Test status
Simulation time 31480417569 ps
CPU time 140.09 seconds
Started Jun 24 04:54:24 PM PDT 24
Finished Jun 24 04:56:47 PM PDT 24
Peak memory 211568 kb
Host smart-d25906c5-dbbf-43db-ac31-686a775a6afe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900339280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3900339280
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1288220722
Short name T749
Test name
Test status
Simulation time 4566355321 ps
CPU time 28.75 seconds
Started Jun 24 04:54:01 PM PDT 24
Finished Jun 24 04:54:35 PM PDT 24
Peak memory 211548 kb
Host smart-f714ed2f-05e9-4027-a638-a0bffc6dd35a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1288220722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1288220722
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.4148616622
Short name T237
Test name
Test status
Simulation time 190181723 ps
CPU time 22.4 seconds
Started Jun 24 04:54:05 PM PDT 24
Finished Jun 24 04:54:32 PM PDT 24
Peak memory 204620 kb
Host smart-c2d068e6-9276-418d-ba0a-56e3c1d1c3df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148616622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4148616622
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.3162946543
Short name T682
Test name
Test status
Simulation time 1677913753 ps
CPU time 26 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:34 PM PDT 24
Peak memory 204036 kb
Host smart-6a230872-dc94-4dcf-9f51-7a6600612740
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3162946543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3162946543
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.2596504766
Short name T496
Test name
Test status
Simulation time 574512565 ps
CPU time 3.32 seconds
Started Jun 24 04:54:03 PM PDT 24
Finished Jun 24 04:54:12 PM PDT 24
Peak memory 203120 kb
Host smart-80005177-75f8-4b68-891e-99ecbcdf4693
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596504766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2596504766
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1729491009
Short name T322
Test name
Test status
Simulation time 4922937235 ps
CPU time 27.62 seconds
Started Jun 24 04:54:17 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203328 kb
Host smart-bf4ad23b-0e6f-4241-ad4a-bf54dce4e38e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729491009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1729491009
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.181820059
Short name T48
Test name
Test status
Simulation time 3843798156 ps
CPU time 24.28 seconds
Started Jun 24 04:54:17 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 203448 kb
Host smart-c08bc66c-9c43-45c9-800a-ffb4fb7d34f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=181820059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.181820059
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.72453410
Short name T696
Test name
Test status
Simulation time 48053297 ps
CPU time 2.15 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:35 PM PDT 24
Peak memory 203304 kb
Host smart-3c233823-9166-4da1-a6ef-969dcb9fc373
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72453410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.72453410
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.4196597647
Short name T174
Test name
Test status
Simulation time 907421110 ps
CPU time 32.23 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:54:49 PM PDT 24
Peak memory 205212 kb
Host smart-a2c1d6c4-5976-4388-9e56-51726f0faf97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4196597647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4196597647
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.672131948
Short name T853
Test name
Test status
Simulation time 35539923127 ps
CPU time 180.54 seconds
Started Jun 24 04:54:33 PM PDT 24
Finished Jun 24 04:57:37 PM PDT 24
Peak memory 208428 kb
Host smart-dbe0ac95-a129-461e-ab22-4115ff062e66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=672131948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.672131948
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.85487944
Short name T193
Test name
Test status
Simulation time 262325118 ps
CPU time 57.63 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:55:10 PM PDT 24
Peak memory 206996 kb
Host smart-6993d060-02ec-476f-a20b-e449d0bcda33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85487944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_r
eset.85487944
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4046171650
Short name T589
Test name
Test status
Simulation time 570583344 ps
CPU time 147.17 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:56:41 PM PDT 24
Peak memory 210696 kb
Host smart-08a7910c-a491-4d2e-97c4-b001bd140892
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046171650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.4046171650
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.43011
Short name T113
Test name
Test status
Simulation time 1375680612 ps
CPU time 21.73 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:54:35 PM PDT 24
Peak memory 204832 kb
Host smart-f4acd78d-d6ca-4ad8-982d-5227d1af01db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.43011
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2587291163
Short name T144
Test name
Test status
Simulation time 1290886545 ps
CPU time 8.1 seconds
Started Jun 24 04:54:07 PM PDT 24
Finished Jun 24 04:54:20 PM PDT 24
Peak memory 203336 kb
Host smart-9bb2d98b-69a8-43c1-b130-b2a8b4498dc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2587291163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2587291163
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2494747305
Short name T192
Test name
Test status
Simulation time 39121522560 ps
CPU time 170 seconds
Started Jun 24 04:54:20 PM PDT 24
Finished Jun 24 04:57:12 PM PDT 24
Peak memory 211580 kb
Host smart-35afc4d8-0e5d-4c20-9028-21eb80378fda
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2494747305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2494747305
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.278155988
Short name T554
Test name
Test status
Simulation time 740453986 ps
CPU time 27.13 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:42 PM PDT 24
Peak memory 203348 kb
Host smart-6b8a207e-bbcf-49a7-acf2-f3d0f37882b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=278155988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.278155988
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.2434781393
Short name T515
Test name
Test status
Simulation time 154423831 ps
CPU time 13.02 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:54:38 PM PDT 24
Peak memory 203344 kb
Host smart-15202f74-64ea-4e29-b0d2-2fa7eca50842
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2434781393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2434781393
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.2100194622
Short name T550
Test name
Test status
Simulation time 507154444 ps
CPU time 13.64 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:54:27 PM PDT 24
Peak memory 211852 kb
Host smart-b45fc0da-d09d-4021-b6e7-a07dc1a198ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2100194622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2100194622
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.151082767
Short name T203
Test name
Test status
Simulation time 64302373578 ps
CPU time 145.14 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:56:43 PM PDT 24
Peak memory 204860 kb
Host smart-e9c5475c-1372-4399-992d-35011d9fba26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=151082767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.151082767
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3127096072
Short name T120
Test name
Test status
Simulation time 35409536279 ps
CPU time 223.59 seconds
Started Jun 24 04:54:18 PM PDT 24
Finished Jun 24 04:58:05 PM PDT 24
Peak memory 211636 kb
Host smart-6f2b5e25-c6ea-4696-816b-3090bce65271
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3127096072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3127096072
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3293179730
Short name T222
Test name
Test status
Simulation time 218950098 ps
CPU time 25.74 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:54:54 PM PDT 24
Peak memory 205040 kb
Host smart-9560b2f3-8a5a-4ef1-bfbd-f65b50c72f85
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293179730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3293179730
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.2562890358
Short name T537
Test name
Test status
Simulation time 150087905 ps
CPU time 6.65 seconds
Started Jun 24 04:54:23 PM PDT 24
Finished Jun 24 04:54:33 PM PDT 24
Peak memory 203976 kb
Host smart-1bf311bd-050f-4496-a528-2a13898689f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562890358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2562890358
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.3908082055
Short name T893
Test name
Test status
Simulation time 662372378 ps
CPU time 3.41 seconds
Started Jun 24 04:54:15 PM PDT 24
Finished Jun 24 04:54:23 PM PDT 24
Peak memory 203392 kb
Host smart-f476b184-2c33-42e9-ac57-83e702a2f974
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3908082055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3908082055
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1165000099
Short name T721
Test name
Test status
Simulation time 21142578192 ps
CPU time 41.41 seconds
Started Jun 24 04:54:41 PM PDT 24
Finished Jun 24 04:55:29 PM PDT 24
Peak memory 203436 kb
Host smart-365ea196-4e92-4e28-b1a2-4b4d1d6e7038
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165000099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1165000099
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3253453145
Short name T547
Test name
Test status
Simulation time 22252857267 ps
CPU time 33.28 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:52 PM PDT 24
Peak memory 203440 kb
Host smart-ede35705-7cb6-4427-860a-7ad6c5d3b2bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3253453145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3253453145
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3631945518
Short name T827
Test name
Test status
Simulation time 25654755 ps
CPU time 2.16 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:54:20 PM PDT 24
Peak memory 203384 kb
Host smart-7d9197d9-adb9-4699-b61e-93488667da38
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631945518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3631945518
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.402756024
Short name T712
Test name
Test status
Simulation time 4171043647 ps
CPU time 132.56 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:56:27 PM PDT 24
Peak memory 206348 kb
Host smart-a6092cd3-1be7-4ef2-b063-81e620313678
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=402756024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.402756024
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1617192646
Short name T463
Test name
Test status
Simulation time 826347519 ps
CPU time 14.65 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:33 PM PDT 24
Peak memory 203400 kb
Host smart-18c75b0f-b321-4168-b7ba-98d882c1695f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1617192646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1617192646
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1972647899
Short name T480
Test name
Test status
Simulation time 1806181669 ps
CPU time 368.78 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 05:00:34 PM PDT 24
Peak memory 210820 kb
Host smart-405f09ff-ecbd-453e-8be0-d8b27bfa11fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1972647899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.1972647899
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.757009134
Short name T19
Test name
Test status
Simulation time 209865993 ps
CPU time 48.92 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 207848 kb
Host smart-394e6740-b769-4910-8b92-2a512240c639
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=757009134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese
t_error.757009134
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.486340861
Short name T594
Test name
Test status
Simulation time 640684797 ps
CPU time 18.95 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:54:37 PM PDT 24
Peak memory 204948 kb
Host smart-5cb02f02-21d3-4d23-b5b1-7003a22df3f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=486340861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.486340861
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2933401838
Short name T143
Test name
Test status
Simulation time 868706906 ps
CPU time 17.78 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:54:35 PM PDT 24
Peak memory 211540 kb
Host smart-f68eed40-242f-4860-8a42-ba168b9d0888
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2933401838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2933401838
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2218580479
Short name T757
Test name
Test status
Simulation time 69763559910 ps
CPU time 531.55 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 05:03:04 PM PDT 24
Peak memory 211532 kb
Host smart-4816bd24-3911-47bc-a61b-b4e0e3a3355f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2218580479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.2218580479
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2716338561
Short name T444
Test name
Test status
Simulation time 128103166 ps
CPU time 13.99 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:34 PM PDT 24
Peak memory 203416 kb
Host smart-adf4779a-c45b-4b34-8dad-8db9ec2bdcc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2716338561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2716338561
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.1416390263
Short name T11
Test name
Test status
Simulation time 189379591 ps
CPU time 17.83 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:54:31 PM PDT 24
Peak memory 203416 kb
Host smart-c43f9e96-ae5a-4768-95e9-3fe8796c3f2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416390263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1416390263
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.850661918
Short name T684
Test name
Test status
Simulation time 54118759 ps
CPU time 2.58 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:23 PM PDT 24
Peak memory 203320 kb
Host smart-b292e3ad-dee9-4fda-b7ff-5f3ff091d23c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=850661918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.850661918
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1153914156
Short name T843
Test name
Test status
Simulation time 35824268436 ps
CPU time 190.32 seconds
Started Jun 24 04:54:19 PM PDT 24
Finished Jun 24 04:57:32 PM PDT 24
Peak memory 205208 kb
Host smart-77428cc3-fe00-4b5c-af04-01e0c56fa8de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153914156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1153914156
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.807006228
Short name T818
Test name
Test status
Simulation time 14697216849 ps
CPU time 105.84 seconds
Started Jun 24 04:54:07 PM PDT 24
Finished Jun 24 04:55:58 PM PDT 24
Peak memory 211612 kb
Host smart-b72539ca-d71c-400c-9809-bbd2b6b7fdb6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=807006228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.807006228
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.899807790
Short name T414
Test name
Test status
Simulation time 215804952 ps
CPU time 8.7 seconds
Started Jun 24 04:54:25 PM PDT 24
Finished Jun 24 04:54:37 PM PDT 24
Peak memory 211584 kb
Host smart-968ff012-f8a5-4c93-a470-71c86db6306f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899807790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.899807790
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2017652393
Short name T466
Test name
Test status
Simulation time 5254020501 ps
CPU time 35.14 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:50 PM PDT 24
Peak memory 204496 kb
Host smart-7529fece-8b2c-42a3-8a1f-9bc3b9e8837c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2017652393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2017652393
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.3656608695
Short name T711
Test name
Test status
Simulation time 291381620 ps
CPU time 2.72 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:54:21 PM PDT 24
Peak memory 203388 kb
Host smart-0f8e8fe5-3b56-4566-a65c-ff25301d8782
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656608695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3656608695
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2298951302
Short name T53
Test name
Test status
Simulation time 6628092667 ps
CPU time 27.76 seconds
Started Jun 24 04:54:17 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203452 kb
Host smart-b1208e85-6ea9-40bb-99fe-a904f2eff0d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298951302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2298951302
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1832531429
Short name T745
Test name
Test status
Simulation time 10014751526 ps
CPU time 44.49 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:55:18 PM PDT 24
Peak memory 203364 kb
Host smart-45304000-8532-43d6-8b83-491f915d6ff0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1832531429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1832531429
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1675976537
Short name T139
Test name
Test status
Simulation time 77453625 ps
CPU time 2.58 seconds
Started Jun 24 04:54:32 PM PDT 24
Finished Jun 24 04:54:39 PM PDT 24
Peak memory 203296 kb
Host smart-24d1adc5-9de7-49be-b9fc-5dd84e2f4b4e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675976537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1675976537
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.1487258721
Short name T85
Test name
Test status
Simulation time 9785533155 ps
CPU time 74.5 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:55:34 PM PDT 24
Peak memory 211636 kb
Host smart-9c1a9678-8311-4887-9fe0-7e7876d815dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487258721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1487258721
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1976110324
Short name T304
Test name
Test status
Simulation time 9819668432 ps
CPU time 295.38 seconds
Started Jun 24 04:54:09 PM PDT 24
Finished Jun 24 04:59:09 PM PDT 24
Peak memory 210080 kb
Host smart-fee0997e-596a-488d-b859-6b602d6a06b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1976110324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1976110324
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1506229063
Short name T163
Test name
Test status
Simulation time 4137522822 ps
CPU time 289.23 seconds
Started Jun 24 04:54:36 PM PDT 24
Finished Jun 24 04:59:29 PM PDT 24
Peak memory 208348 kb
Host smart-7ea63c35-6be7-49f3-8d79-a95b829d2222
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1506229063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.1506229063
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1551880789
Short name T312
Test name
Test status
Simulation time 4073884037 ps
CPU time 319.68 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:59:37 PM PDT 24
Peak memory 219880 kb
Host smart-62038a11-4eea-4d07-8002-b72e86d4686c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1551880789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.1551880789
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.655779691
Short name T845
Test name
Test status
Simulation time 936299119 ps
CPU time 29.16 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 211576 kb
Host smart-66dbf5d5-755b-4940-a15a-55117f8d32a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=655779691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.655779691
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3734875974
Short name T700
Test name
Test status
Simulation time 626316084 ps
CPU time 22.27 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:39 PM PDT 24
Peak memory 204536 kb
Host smart-9bda41dd-50cf-425f-8208-9a1298e70478
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3734875974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3734875974
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2646851884
Short name T205
Test name
Test status
Simulation time 97753637729 ps
CPU time 364.36 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 05:00:22 PM PDT 24
Peak memory 211564 kb
Host smart-0a18ff65-cebd-43a3-b1fa-e0485988ea57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2646851884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.2646851884
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2486386892
Short name T166
Test name
Test status
Simulation time 107243039 ps
CPU time 17.2 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:32 PM PDT 24
Peak memory 204192 kb
Host smart-a4a4fae6-c270-446a-9396-4132d61ce030
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2486386892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2486386892
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.1598200292
Short name T102
Test name
Test status
Simulation time 1664865464 ps
CPU time 37.06 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:56 PM PDT 24
Peak memory 203420 kb
Host smart-66dca402-c2ae-4721-b0a1-60802aa3f4ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1598200292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1598200292
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.334653902
Short name T195
Test name
Test status
Simulation time 605196684 ps
CPU time 8.56 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:54:43 PM PDT 24
Peak memory 211560 kb
Host smart-6fdccda9-7fee-44f0-9262-82b519803d72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=334653902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.334653902
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1498417599
Short name T217
Test name
Test status
Simulation time 62645015875 ps
CPU time 185.96 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:57:21 PM PDT 24
Peak memory 204756 kb
Host smart-a742e421-60d3-48a0-9f6b-449f9e0c4717
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498417599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1498417599
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2079238378
Short name T597
Test name
Test status
Simulation time 1909290667 ps
CPU time 11.99 seconds
Started Jun 24 04:54:32 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203328 kb
Host smart-7a0fbfec-c23c-4e0e-a107-88c0b53276db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2079238378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2079238378
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2847491196
Short name T62
Test name
Test status
Simulation time 53671459 ps
CPU time 6.26 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:54:40 PM PDT 24
Peak memory 211560 kb
Host smart-11feced8-3919-4e50-be0a-118c34c4b6bc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847491196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2847491196
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.1564993282
Short name T218
Test name
Test status
Simulation time 1544760258 ps
CPU time 33.68 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:50 PM PDT 24
Peak memory 211332 kb
Host smart-c30898d5-c573-4aed-a495-4895e5477701
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1564993282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1564993282
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.3979542921
Short name T41
Test name
Test status
Simulation time 26701352 ps
CPU time 2.29 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:21 PM PDT 24
Peak memory 203308 kb
Host smart-34c7115f-782e-4ad5-9615-a9ba9f9476ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3979542921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3979542921
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2087922084
Short name T510
Test name
Test status
Simulation time 18862434250 ps
CPU time 39.05 seconds
Started Jun 24 04:54:17 PM PDT 24
Finished Jun 24 04:54:59 PM PDT 24
Peak memory 203456 kb
Host smart-26a69f45-958f-4343-a6ff-8e54e0ab3afe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087922084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2087922084
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2043215140
Short name T840
Test name
Test status
Simulation time 3890615942 ps
CPU time 30.38 seconds
Started Jun 24 04:54:27 PM PDT 24
Finished Jun 24 04:55:01 PM PDT 24
Peak memory 203376 kb
Host smart-6a848645-09f0-46fb-9324-ba70544e5444
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2043215140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2043215140
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3379624259
Short name T831
Test name
Test status
Simulation time 29454335 ps
CPU time 2.42 seconds
Started Jun 24 04:54:08 PM PDT 24
Finished Jun 24 04:54:15 PM PDT 24
Peak memory 203304 kb
Host smart-7f09baac-39ee-4726-9fe3-34907d5cf0c0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379624259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3379624259
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.651493042
Short name T369
Test name
Test status
Simulation time 838408054 ps
CPU time 59.9 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 207424 kb
Host smart-4aa62124-cd0c-4def-b4e9-efba30e08dd0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=651493042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.651493042
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1831301640
Short name T623
Test name
Test status
Simulation time 1457556235 ps
CPU time 40.6 seconds
Started Jun 24 04:54:35 PM PDT 24
Finished Jun 24 04:55:19 PM PDT 24
Peak memory 203760 kb
Host smart-681a66d1-e8a3-45e2-aec6-95b176724027
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1831301640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1831301640
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1491289019
Short name T639
Test name
Test status
Simulation time 111413021 ps
CPU time 74.91 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:55:32 PM PDT 24
Peak memory 208060 kb
Host smart-86807bb8-85ca-4918-8e0b-397e7d3dc04d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1491289019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.1491289019
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.615507582
Short name T643
Test name
Test status
Simulation time 391292005 ps
CPU time 9.43 seconds
Started Jun 24 04:54:30 PM PDT 24
Finished Jun 24 04:54:44 PM PDT 24
Peak memory 211576 kb
Host smart-efb95412-cf5c-4213-9a4a-4d904f0e33bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=615507582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.615507582
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3263822450
Short name T188
Test name
Test status
Simulation time 350034689 ps
CPU time 38.54 seconds
Started Jun 24 04:54:29 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 211604 kb
Host smart-f0360f19-f58e-462d-9425-e7cce56bfa22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3263822450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3263822450
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.445409044
Short name T544
Test name
Test status
Simulation time 61596918034 ps
CPU time 212.72 seconds
Started Jun 24 04:54:22 PM PDT 24
Finished Jun 24 04:57:58 PM PDT 24
Peak memory 211608 kb
Host smart-c75c0adc-8545-43f2-ba02-4d8a7a18093e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=445409044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow
_rsp.445409044
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3078997543
Short name T565
Test name
Test status
Simulation time 31891575 ps
CPU time 3.77 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 203764 kb
Host smart-6de23fb6-380b-4d1e-8545-6457cd346934
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3078997543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3078997543
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2881066348
Short name T740
Test name
Test status
Simulation time 1478913187 ps
CPU time 27.37 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:54:46 PM PDT 24
Peak memory 203356 kb
Host smart-8abb9b5e-5cd2-4e71-9b0e-a15c148a0c75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2881066348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2881066348
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.2253941282
Short name T665
Test name
Test status
Simulation time 250984505 ps
CPU time 15.49 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:30 PM PDT 24
Peak memory 204456 kb
Host smart-21e19d31-713f-48fe-85e5-736931ce94be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2253941282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2253941282
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.241306108
Short name T95
Test name
Test status
Simulation time 6699486799 ps
CPU time 24.36 seconds
Started Jun 24 04:54:16 PM PDT 24
Finished Jun 24 04:54:44 PM PDT 24
Peak memory 211616 kb
Host smart-5cb3bb2a-6591-48ee-880f-edca3fd22c98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=241306108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.241306108
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.672926002
Short name T287
Test name
Test status
Simulation time 5014523357 ps
CPU time 46.15 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:55:02 PM PDT 24
Peak memory 210724 kb
Host smart-e429a818-13fc-4cc8-8322-351776d72159
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=672926002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.672926002
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.4043357630
Short name T216
Test name
Test status
Simulation time 170653875 ps
CPU time 19.93 seconds
Started Jun 24 04:54:39 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 204936 kb
Host smart-00f68f70-62da-44ed-a868-f32eaf3313d0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043357630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.4043357630
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3585685066
Short name T263
Test name
Test status
Simulation time 1398738272 ps
CPU time 30.16 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203472 kb
Host smart-c557e2be-77ca-4838-a5b3-6d8ad37e78c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585685066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3585685066
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.19334419
Short name T838
Test name
Test status
Simulation time 145721115 ps
CPU time 3.12 seconds
Started Jun 24 04:54:14 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 203388 kb
Host smart-edd92482-0d0c-4b92-9ec3-bd12892c2c78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19334419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.19334419
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3835943266
Short name T546
Test name
Test status
Simulation time 6938279175 ps
CPU time 28.34 seconds
Started Jun 24 04:54:11 PM PDT 24
Finished Jun 24 04:54:45 PM PDT 24
Peak memory 202436 kb
Host smart-c93e0d92-561f-46dd-8689-4aa4b906c16f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835943266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3835943266
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.847181249
Short name T39
Test name
Test status
Simulation time 8528271978 ps
CPU time 26.17 seconds
Started Jun 24 04:54:19 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 203404 kb
Host smart-74b15dd3-0ec1-4e99-8359-a991e41e6920
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=847181249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.847181249
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1981291495
Short name T354
Test name
Test status
Simulation time 54504955 ps
CPU time 2.07 seconds
Started Jun 24 04:54:15 PM PDT 24
Finished Jun 24 04:54:22 PM PDT 24
Peak memory 203340 kb
Host smart-40c29a3d-dbc5-4955-b799-854324d7bb8a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981291495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1981291495
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.1485826740
Short name T189
Test name
Test status
Simulation time 3349987353 ps
CPU time 104.61 seconds
Started Jun 24 04:54:13 PM PDT 24
Finished Jun 24 04:56:03 PM PDT 24
Peak memory 208084 kb
Host smart-097ab34e-2c00-4e9d-bf65-75fbd02f2c23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1485826740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1485826740
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3041767246
Short name T677
Test name
Test status
Simulation time 860898897 ps
CPU time 76.61 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:55:33 PM PDT 24
Peak memory 208000 kb
Host smart-0a7ee15f-35d6-48df-96e6-0797fb18d6c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3041767246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3041767246
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1107380081
Short name T190
Test name
Test status
Simulation time 837033658 ps
CPU time 266.39 seconds
Started Jun 24 04:54:53 PM PDT 24
Finished Jun 24 04:59:26 PM PDT 24
Peak memory 208220 kb
Host smart-5b3335a3-5064-4d0a-9106-5e7238f301a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1107380081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.1107380081
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2262647409
Short name T381
Test name
Test status
Simulation time 1506805397 ps
CPU time 151.74 seconds
Started Jun 24 04:54:12 PM PDT 24
Finished Jun 24 04:56:49 PM PDT 24
Peak memory 210292 kb
Host smart-f8b41d80-ce76-4229-a46b-5d193f393e20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2262647409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2262647409
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.504657108
Short name T344
Test name
Test status
Simulation time 178005633 ps
CPU time 20.99 seconds
Started Jun 24 04:54:10 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 205016 kb
Host smart-8e115d44-0eb0-477e-9cdb-1c04b2cf1a7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=504657108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.504657108
Directory /workspace/9.xbar_unmapped_addr/latest
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