Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1789	1			T29	6		T21	10		T26	1
all_values[1]	1895	1			T29	15		T21	4		T203	2
all_values[2]	1752	1			T29	9		T21	4		T26	6
all_values[3]	1875	1			T29	14		T21	5		T203	1
all_values[4]	1857	1			T29	4		T21	7		T26	2
all_values[5]	1790	1			T29	10		T21	5		T26	3
all_values[6]	1833	1			T29	10		T21	9		T26	1
all_values[7]	1833	1			T29	6		T21	8		T203	2
all_values[8]	1854	1			T29	12		T21	4		T203	1
all_values[9]	1784	1			T29	11		T21	6		T203	2
all_values[10]	1853	1			T29	8		T21	7		T26	3
all_values[11]	1907	1			T29	12		T21	8		T26	1
all_values[12]	1802	1			T29	9		T21	4		T203	1
all_values[13]	1823	1			T29	7		T21	2		T203	1
all_values[14]	1843	1			T29	13		T21	6		T26	4
all_values[15]	1861	1			T29	1		T21	7		T26	3
all_values[16]	1808	1			T29	15		T21	8		T203	2
all_values[17]	1845	1			T29	7		T21	10		T27	2
all_values[18]	1869	1			T29	6		T21	4		T26	3
all_values[19]	1865	1			T29	9		T21	8		T27	3
all_values[20]	1765	1			T29	5		T21	7		T97	2
all_values[21]	1833	1			T29	9		T21	1		T203	1
all_values[22]	1802	1			T29	8		T21	5		T203	1
all_values[23]	1799	1			T29	9		T21	6		T203	1
all_values[24]	1869	1			T29	9		T21	4		T26	3
all_values[25]	1907	1			T29	6		T21	3		T203	1
all_values[26]	1836	1			T29	6		T21	5		T203	1
all_values[27]	1854	1			T29	8		T21	7		T26	1
all_values[28]	1858	1			T29	11		T21	6		T203	2
all_values[29]	1822	1			T29	12		T21	3		T203	1
all_values[30]	1857	1			T29	9		T21	6		T203	1
all_values[31]	1776	1			T29	9		T21	3		T203	1
all_values[32]	1789	1			T29	5		T21	7		T27	4
all_values[33]	1859	1			T29	6		T21	5		T26	5
all_values[34]	1865	1			T29	6		T21	7		T203	3
all_values[35]	1774	1			T29	7		T21	6		T203	1
all_values[36]	1928	1			T29	14		T21	10		T26	2
all_values[37]	1870	1			T29	8		T21	11		T26	2
all_values[38]	1838	1			T29	15		T21	9		T203	4
all_values[39]	1750	1			T29	7		T21	8		T203	2
all_values[40]	1849	1			T29	11		T21	2		T26	1
all_values[41]	1767	1			T29	7		T21	7		T27	5
all_values[42]	1842	1			T29	10		T21	5		T203	2
all_values[43]	1841	1			T29	8		T21	3		T26	2
all_values[44]	1866	1			T29	7		T21	11		T203	1
all_values[45]	1912	1			T29	11		T21	10		T203	1
all_values[46]	1895	1			T29	8		T21	1		T203	2
all_values[47]	1769	1			T29	11		T21	7		T26	1
all_values[48]	1852	1			T29	10		T21	7		T203	1
all_values[49]	1913	1			T29	14		T21	5		T203	1
all_values[50]	1853	1			T29	8		T21	9		T98	2
all_values[51]	1852	1			T29	8		T21	5		T203	1
all_values[52]	1776	1			T29	13		T21	11		T97	3
all_values[53]	1872	1			T29	8		T21	3		T26	2
all_values[54]	1779	1			T29	15		T21	6		T26	1
all_values[55]	1749	1			T29	8		T21	6		T26	1
all_values[56]	1823	1			T29	9		T21	5		T203	1
all_values[57]	1892	1			T29	12		T21	8		T203	1
all_values[58]	1855	1			T29	12		T21	7		T203	1
all_values[59]	1859	1			T29	12		T21	6		T203	1
all_values[60]	1779	1			T29	6		T21	9		T26	2
all_values[61]	1795	1			T29	2		T21	5		T203	1
all_values[62]	1815	1			T29	13		T21	7		T203	1
all_values[63]	1847	1			T29	7		T21	7		T203	2