Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1833	1			T11	35		T14	3		T15	5
all_values[1]	1886	1			T11	36		T14	4		T15	12
all_values[2]	1900	1			T11	41		T14	3		T15	10
all_values[3]	1827	1			T11	39		T14	4		T15	6
all_values[4]	1864	1			T11	30		T14	4		T15	9
all_values[5]	1886	1			T11	31		T14	3		T15	7
all_values[6]	1854	1			T11	36		T14	5		T15	11
all_values[7]	1828	1			T11	24		T14	5		T15	8
all_values[8]	1819	1			T11	29		T14	4		T15	10
all_values[9]	1807	1			T11	24		T14	3		T15	6
all_values[10]	1808	1			T11	26		T14	1		T15	5
all_values[11]	1851	1			T11	22		T14	4		T15	7
all_values[12]	1790	1			T11	42		T15	7		T60	1
all_values[13]	1872	1			T11	36		T14	4		T15	11
all_values[14]	1889	1			T11	40		T14	4		T15	4
all_values[15]	1838	1			T11	34		T14	5		T15	9
all_values[16]	1949	1			T11	32		T14	1		T15	2
all_values[17]	1841	1			T11	27		T15	10		T60	1
all_values[18]	1863	1			T11	43		T14	2		T15	7
all_values[19]	1849	1			T11	30		T14	6		T15	5
all_values[20]	1841	1			T11	34		T14	4		T15	10
all_values[21]	1796	1			T11	25		T14	2		T15	5
all_values[22]	1783	1			T11	34		T14	1		T15	8
all_values[23]	1842	1			T11	28		T14	2		T15	7
all_values[24]	1856	1			T11	30		T14	5		T15	7
all_values[25]	1824	1			T11	34		T14	4		T15	7
all_values[26]	1820	1			T11	46		T14	4		T15	4
all_values[27]	1826	1			T11	33		T14	3		T15	6
all_values[28]	1798	1			T11	29		T14	3		T15	8
all_values[29]	1855	1			T11	44		T14	2		T15	8
all_values[30]	1883	1			T11	37		T14	2		T15	10
all_values[31]	1827	1			T11	36		T14	3		T15	4
all_values[32]	1848	1			T11	29		T14	4		T15	6
all_values[33]	1821	1			T11	32		T14	5		T15	8
all_values[34]	1775	1			T11	34		T14	4		T15	3
all_values[35]	1818	1			T11	23		T14	8		T15	4
all_values[36]	1839	1			T11	28		T14	5		T15	7
all_values[37]	1856	1			T11	37		T14	2		T15	7
all_values[38]	1838	1			T11	30		T14	2		T15	6
all_values[39]	1826	1			T11	38		T14	3		T15	9
all_values[40]	1893	1			T11	30		T14	7		T15	6
all_values[41]	1801	1			T11	31		T14	4		T15	6
all_values[42]	1806	1			T11	36		T14	3		T15	8
all_values[43]	1881	1			T11	30		T14	1		T15	5
all_values[44]	1816	1			T11	32		T14	4		T15	9
all_values[45]	1847	1			T11	20		T14	1		T15	6
all_values[46]	1865	1			T11	29		T14	2		T15	5
all_values[47]	1896	1			T11	39		T14	8		T15	4
all_values[48]	1773	1			T11	35		T14	2		T15	1
all_values[49]	1869	1			T11	40		T14	2		T15	5
all_values[50]	1820	1			T11	25		T14	5		T15	11
all_values[51]	1851	1			T11	34		T14	3		T15	6
all_values[52]	1882	1			T11	29		T14	1		T15	8
all_values[53]	1825	1			T11	40		T14	6		T15	1
all_values[54]	1858	1			T11	36		T14	2		T15	4
all_values[55]	1884	1			T11	29		T14	8		T15	8
all_values[56]	1739	1			T11	29		T14	1		T15	5
all_values[57]	1915	1			T11	36		T14	6		T15	5
all_values[58]	1829	1			T11	36		T14	1		T15	9
all_values[59]	1879	1			T11	32		T14	4		T15	8
all_values[60]	1808	1			T11	37		T14	5		T15	6
all_values[61]	1825	1			T11	33		T14	4		T15	6
all_values[62]	1834	1			T11	36		T14	4		T15	8
all_values[63]	1802	1			T11	34		T14	2		T15	8