Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1805	1			T1	1		T14	6		T17	19
all_values[1]	1878	1			T1	2		T13	1		T14	10
all_values[2]	1822	1			T1	5		T13	3		T14	6
all_values[3]	1837	1			T1	3		T13	2		T14	6
all_values[4]	1906	1			T1	1		T13	5		T14	2
all_values[5]	1781	1			T1	3		T13	2		T14	4
all_values[6]	1781	1			T1	1		T13	4		T14	4
all_values[7]	1884	1			T1	2		T13	1		T14	5
all_values[8]	1917	1			T1	1		T13	3		T14	6
all_values[9]	1823	1			T1	3		T13	1		T14	4
all_values[10]	1831	1			T13	1		T14	4		T17	18
all_values[11]	1848	1			T1	4		T13	2		T14	6
all_values[12]	1819	1			T1	2		T13	2		T14	6
all_values[13]	1849	1			T1	3		T13	4		T14	8
all_values[14]	1839	1			T1	3		T13	3		T14	3
all_values[15]	1932	1			T1	1		T13	2		T14	7
all_values[16]	1838	1			T1	1		T13	3		T14	8
all_values[17]	1811	1			T1	3		T13	3		T14	5
all_values[18]	1865	1			T1	3		T13	4		T14	2
all_values[19]	1800	1			T13	2		T14	5		T17	20
all_values[20]	1860	1			T1	2		T14	1		T17	19
all_values[21]	1767	1			T1	7		T13	3		T14	1
all_values[22]	1718	1			T1	3		T13	2		T14	2
all_values[23]	1813	1			T1	3		T13	1		T14	9
all_values[24]	1753	1			T1	4		T13	4		T14	7
all_values[25]	1875	1			T13	1		T14	10		T17	22
all_values[26]	1805	1			T1	3		T13	1		T14	1
all_values[27]	1866	1			T1	1		T13	2		T14	3
all_values[28]	1847	1			T1	1		T13	3		T14	8
all_values[29]	1930	1			T1	2		T13	3		T14	7
all_values[30]	1825	1			T14	3		T17	18		T18	2
all_values[31]	1902	1			T1	1		T13	3		T14	5
all_values[32]	1865	1			T1	5		T14	2		T17	15
all_values[33]	1816	1			T1	2		T13	3		T14	6
all_values[34]	1892	1			T1	3		T13	5		T14	7
all_values[35]	1882	1			T1	2		T13	3		T14	6
all_values[36]	1824	1			T1	3		T13	3		T14	3
all_values[37]	1888	1			T1	1		T13	6		T14	8
all_values[38]	1846	1			T1	1		T14	2		T17	19
all_values[39]	1813	1			T1	1		T13	2		T14	5
all_values[40]	1791	1			T1	1		T13	3		T14	4
all_values[41]	1845	1			T1	5		T13	4		T14	3
all_values[42]	1770	1			T1	4		T13	7		T14	6
all_values[43]	1887	1			T1	6		T13	4		T14	8
all_values[44]	1845	1			T1	5		T13	2		T14	2
all_values[45]	1863	1			T1	2		T13	5		T14	7
all_values[46]	1976	1			T1	1		T13	1		T14	3
all_values[47]	1801	1			T1	2		T13	4		T14	11
all_values[48]	1836	1			T1	1		T13	2		T14	5
all_values[49]	1867	1			T1	1		T13	2		T14	5
all_values[50]	1796	1			T1	3		T13	3		T14	4
all_values[51]	1804	1			T1	5		T13	2		T14	7
all_values[52]	1849	1			T1	5		T13	6		T14	5
all_values[53]	1822	1			T1	2		T13	2		T14	4
all_values[54]	1957	1			T1	2		T13	2		T14	5
all_values[55]	1868	1			T1	3		T13	2		T14	6
all_values[56]	1856	1			T1	3		T13	4		T14	2
all_values[57]	1811	1			T1	2		T13	5		T14	6
all_values[58]	1822	1			T1	4		T13	1		T14	3
all_values[59]	1849	1			T1	1		T14	5		T17	23
all_values[60]	1845	1			T1	4		T13	2		T14	5
all_values[61]	1820	1			T1	2		T14	3		T15	2
all_values[62]	1899	1			T1	1		T13	5		T14	1
all_values[63]	1769	1			T1	2		T13	3		T14	5