Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1818	1			T2	6		T7	5		T15	5
all_values[1]	1819	1			T2	7		T7	7		T27	1
all_values[2]	1802	1			T2	6		T7	4		T27	2
all_values[3]	1865	1			T2	7		T7	9		T13	1
all_values[4]	1738	1			T2	9		T7	4		T13	1
all_values[5]	1828	1			T2	6		T7	10		T13	1
all_values[6]	1781	1			T2	8		T7	7		T13	1
all_values[7]	1786	1			T2	11		T7	4		T27	1
all_values[8]	1755	1			T2	12		T7	4		T13	2
all_values[9]	1847	1			T2	9		T7	4		T13	1
all_values[10]	1754	1			T2	10		T7	3		T13	2
all_values[11]	1886	1			T2	5		T7	8		T27	2
all_values[12]	1821	1			T2	9		T7	5		T13	1
all_values[13]	1793	1			T2	11		T7	6		T27	3
all_values[14]	1799	1			T2	13		T7	7		T27	3
all_values[15]	1757	1			T2	12		T7	9		T13	1
all_values[16]	1846	1			T2	6		T7	6		T13	1
all_values[17]	1831	1			T2	8		T7	5		T13	1
all_values[18]	1823	1			T2	10		T7	4		T13	2
all_values[19]	1817	1			T2	11		T7	6		T27	3
all_values[20]	1764	1			T2	8		T7	2		T27	1
all_values[21]	1913	1			T2	10		T7	10		T13	1
all_values[22]	1836	1			T2	5		T7	5		T13	1
all_values[23]	1834	1			T2	8		T7	7		T13	3
all_values[24]	1793	1			T2	8		T7	10		T13	1
all_values[25]	1793	1			T2	4		T7	6		T27	2
all_values[26]	1899	1			T2	4		T7	1		T13	2
all_values[27]	1800	1			T2	6		T7	8		T13	2
all_values[28]	1861	1			T2	3		T7	3		T13	2
all_values[29]	1844	1			T2	10		T7	5		T13	1
all_values[30]	1813	1			T2	6		T7	5		T13	3
all_values[31]	1826	1			T2	6		T7	3		T13	1
all_values[32]	1850	1			T2	10		T7	3		T13	2
all_values[33]	1882	1			T2	10		T7	5		T13	1
all_values[34]	1833	1			T2	11		T7	1		T13	2
all_values[35]	1788	1			T2	9		T7	5		T13	1
all_values[36]	1860	1			T2	4		T7	7		T13	1
all_values[37]	1806	1			T2	9		T7	6		T27	1
all_values[38]	1754	1			T2	7		T7	4		T13	1
all_values[39]	1892	1			T2	13		T7	3		T13	1
all_values[40]	1795	1			T2	8		T7	6		T13	1
all_values[41]	1809	1			T2	8		T7	5		T15	4
all_values[42]	1871	1			T2	13		T7	3		T27	2
all_values[43]	1825	1			T2	9		T7	6		T13	1
all_values[44]	1808	1			T2	10		T7	2		T13	1
all_values[45]	1796	1			T2	4		T7	4		T13	1
all_values[46]	1815	1			T2	8		T7	5		T15	3
all_values[47]	1804	1			T2	7		T7	2		T27	1
all_values[48]	1781	1			T2	5		T7	5		T13	1
all_values[49]	1815	1			T2	10		T7	1		T13	1
all_values[50]	1784	1			T2	10		T7	6		T13	2
all_values[51]	1856	1			T2	8		T7	7		T13	1
all_values[52]	1752	1			T2	6		T7	5		T27	2
all_values[53]	1740	1			T2	5		T7	2		T27	3
all_values[54]	1841	1			T2	6		T7	4		T15	4
all_values[55]	1834	1			T2	5		T7	4		T15	8
all_values[56]	1770	1			T2	12		T7	8		T13	1
all_values[57]	1807	1			T2	4		T7	6		T13	2
all_values[58]	1873	1			T2	6		T7	5		T27	4
all_values[59]	1859	1			T2	9		T7	8		T27	3
all_values[60]	1779	1			T2	6		T7	4		T13	1
all_values[61]	1837	1			T2	12		T7	3		T13	4
all_values[62]	1777	1			T2	4		T7	4		T27	1
all_values[63]	1892	1			T2	10		T7	4		T27	1