Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1648	1			T3	12		T7	2		T12	2
all_values[1]	1644	1			T3	11		T7	4		T9	2
all_values[2]	1649	1			T3	15		T7	6		T9	1
all_values[3]	1675	1			T3	10		T7	1		T9	3
all_values[4]	1641	1			T3	12		T9	5		T12	1
all_values[5]	1604	1			T3	14		T7	4		T9	1
all_values[6]	1669	1			T3	9		T9	6		T12	1
all_values[7]	1710	1			T3	12		T7	2		T9	4
all_values[8]	1619	1			T3	12		T7	2		T9	3
all_values[9]	1657	1			T3	17		T7	3		T9	4
all_values[10]	1666	1			T3	12		T7	1		T9	4
all_values[11]	1589	1			T3	10		T7	3		T14	22
all_values[12]	1639	1			T3	9		T7	2		T9	2
all_values[13]	1644	1			T3	13		T9	7		T12	2
all_values[14]	1657	1			T3	19		T7	2		T9	5
all_values[15]	1628	1			T3	12		T7	1		T9	3
all_values[16]	1662	1			T3	10		T7	1		T12	2
all_values[17]	1656	1			T3	12		T7	1		T9	2
all_values[18]	1686	1			T3	14		T7	1		T9	4
all_values[19]	1616	1			T3	9		T7	2		T9	3
all_values[20]	1686	1			T3	12		T9	2		T12	1
all_values[21]	1665	1			T3	16		T7	2		T9	3
all_values[22]	1715	1			T3	18		T9	4		T12	2
all_values[23]	1630	1			T3	12		T7	1		T9	4
all_values[24]	1665	1			T3	7		T7	2		T9	1
all_values[25]	1683	1			T3	12		T9	1		T12	1
all_values[26]	1691	1			T3	13		T7	1		T9	3
all_values[27]	1609	1			T3	9		T7	3		T9	2
all_values[28]	1656	1			T3	7		T7	2		T9	2
all_values[29]	1688	1			T3	13		T7	4		T9	2
all_values[30]	1684	1			T3	12		T7	2		T9	4
all_values[31]	1740	1			T3	20		T7	2		T9	4
all_values[32]	1534	1			T3	17		T9	1		T12	2
all_values[33]	1653	1			T3	18		T7	1		T9	4
all_values[34]	1737	1			T3	13		T7	3		T9	3
all_values[35]	1654	1			T3	16		T7	1		T9	1
all_values[36]	1642	1			T3	14		T9	2		T12	4
all_values[37]	1612	1			T3	9		T7	3		T9	2
all_values[38]	1643	1			T3	10		T7	2		T9	3
all_values[39]	1671	1			T3	14		T7	2		T9	3
all_values[40]	1699	1			T3	12		T7	2		T9	4
all_values[41]	1657	1			T3	13		T7	3		T9	2
all_values[42]	1661	1			T3	20		T7	3		T9	3
all_values[43]	1581	1			T3	3		T7	1		T9	2
all_values[44]	1640	1			T3	9		T7	3		T9	6
all_values[45]	1686	1			T3	10		T7	2		T9	4
all_values[46]	1682	1			T3	25		T7	3		T9	1
all_values[47]	1685	1			T3	18		T9	4		T12	2
all_values[48]	1688	1			T3	20		T7	3		T14	18
all_values[49]	1674	1			T3	15		T9	6		T14	28
all_values[50]	1684	1			T3	11		T7	1		T9	3
all_values[51]	1701	1			T3	15		T7	2		T9	4
all_values[52]	1642	1			T3	9		T9	2		T14	24
all_values[53]	1689	1			T3	19		T7	4		T9	5
all_values[54]	1736	1			T3	17		T9	2		T12	1
all_values[55]	1677	1			T3	12		T7	3		T9	3
all_values[56]	1675	1			T3	10		T7	3		T9	1
all_values[57]	1648	1			T3	18		T7	4		T9	3
all_values[58]	1630	1			T3	11		T7	2		T9	4
all_values[59]	1614	1			T3	18		T7	1		T9	4
all_values[60]	1691	1			T3	14		T7	1		T9	2
all_values[61]	1599	1			T3	16		T7	2		T9	2
all_values[62]	1699	1			T3	18		T7	4		T9	2
all_values[63]	1684	1			T3	14		T9	1		T12	2