Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1827	1			T3	4		T11	1		T21	2
all_values[1]	1871	1			T3	4		T11	1		T21	5
all_values[2]	1813	1			T3	3		T11	1		T21	6
all_values[3]	1714	1			T3	1		T21	7		T22	6
all_values[4]	1792	1			T3	5		T11	1		T21	6
all_values[5]	1835	1			T3	2		T21	4		T22	5
all_values[6]	1827	1			T3	2		T21	4		T22	8
all_values[7]	1817	1			T3	4		T21	10		T22	12
all_values[8]	1770	1			T3	6		T11	1		T21	4
all_values[9]	1794	1			T3	2		T11	1		T21	7
all_values[10]	1824	1			T3	1		T21	5		T22	10
all_values[11]	1833	1			T3	1		T11	2		T21	7
all_values[12]	1756	1			T3	2		T11	2		T21	10
all_values[13]	1869	1			T3	1		T21	4		T22	6
all_values[14]	1858	1			T3	6		T21	7		T22	6
all_values[15]	1829	1			T3	4		T21	8		T22	12
all_values[16]	1781	1			T3	1		T11	1		T21	4
all_values[17]	1732	1			T3	3		T21	5		T22	5
all_values[18]	1789	1			T21	7		T22	5		T30	9
all_values[19]	1839	1			T3	1		T11	1		T21	6
all_values[20]	1792	1			T3	4		T11	2		T21	4
all_values[21]	1904	1			T3	2		T11	1		T21	2
all_values[22]	1756	1			T3	2		T21	4		T22	10
all_values[23]	1819	1			T3	1		T21	4		T22	9
all_values[24]	1882	1			T3	1		T11	1		T21	6
all_values[25]	1770	1			T3	1		T21	7		T22	9
all_values[26]	1758	1			T3	3		T11	1		T21	7
all_values[27]	1853	1			T3	2		T11	2		T21	5
all_values[28]	1798	1			T3	3		T21	1		T22	8
all_values[29]	1801	1			T3	1		T11	2		T21	4
all_values[30]	1859	1			T3	2		T21	4		T22	5
all_values[31]	1849	1			T3	6		T21	9		T22	6
all_values[32]	1870	1			T21	5		T22	9		T30	14
all_values[33]	1800	1			T3	3		T11	1		T21	3
all_values[34]	1896	1			T3	4		T11	1		T21	3
all_values[35]	1757	1			T3	1		T21	6		T22	3
all_values[36]	1815	1			T3	2		T21	8		T22	4
all_values[37]	1826	1			T3	4		T21	3		T22	5
all_values[38]	1733	1			T3	1		T11	2		T21	5
all_values[39]	1828	1			T3	1		T11	2		T21	11
all_values[40]	1858	1			T3	3		T11	2		T21	3
all_values[41]	1829	1			T3	5		T11	1		T21	4
all_values[42]	1884	1			T3	2		T11	2		T21	2
all_values[43]	1743	1			T3	4		T21	7		T22	3
all_values[44]	1912	1			T3	1		T11	1		T21	7
all_values[45]	1828	1			T3	3		T21	7		T22	4
all_values[46]	1773	1			T3	2		T11	1		T21	4
all_values[47]	1773	1			T3	3		T11	1		T21	7
all_values[48]	1765	1			T3	1		T21	8		T22	8
all_values[49]	1874	1			T3	3		T11	1		T21	6
all_values[50]	1783	1			T11	1		T21	5		T22	5
all_values[51]	1712	1			T3	1		T11	1		T21	11
all_values[52]	1899	1			T3	4		T21	3		T22	10
all_values[53]	1740	1			T3	6		T21	5		T22	8
all_values[54]	1776	1			T3	2		T21	5		T22	4
all_values[55]	1816	1			T3	2		T11	3		T21	5
all_values[56]	1796	1			T3	1		T21	6		T22	7
all_values[57]	1865	1			T3	1		T11	1		T21	10
all_values[58]	1784	1			T3	2		T21	6		T22	7
all_values[59]	1877	1			T3	2		T21	4		T22	7
all_values[60]	1862	1			T3	5		T21	6		T22	5
all_values[61]	1833	1			T3	1		T21	4		T22	13
all_values[62]	1783	1			T3	3		T11	1		T21	5
all_values[63]	1874	1			T3	2		T21	4		T22	8