Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1643	1			T7	1		T9	6		T10	2
all_values[1]	1744	1			T7	3		T9	5		T10	1
all_values[2]	1714	1			T9	3		T10	2		T27	11
all_values[3]	1678	1			T9	4		T10	2		T15	3
all_values[4]	1752	1			T7	1		T9	3		T10	1
all_values[5]	1730	1			T7	1		T9	2		T10	1
all_values[6]	1752	1			T10	2		T15	2		T27	13
all_values[7]	1722	1			T7	3		T9	3		T10	3
all_values[8]	1777	1			T7	4		T9	3		T10	1
all_values[9]	1757	1			T7	2		T9	5		T15	1
all_values[10]	1780	1			T7	1		T9	2		T10	2
all_values[11]	1665	1			T9	3		T10	1		T15	2
all_values[12]	1672	1			T7	2		T9	1		T10	1
all_values[13]	1764	1			T7	1		T9	2		T15	2
all_values[14]	1784	1			T7	1		T9	1		T15	1
all_values[15]	1685	1			T7	1		T15	4		T27	22
all_values[16]	1717	1			T7	1		T9	2		T10	2
all_values[17]	1641	1			T7	1		T9	2		T15	4
all_values[18]	1674	1			T9	3		T10	2		T27	17
all_values[19]	1697	1			T7	2		T9	3		T15	2
all_values[20]	1742	1			T9	2		T10	1		T27	14
all_values[21]	1687	1			T7	3		T9	2		T10	1
all_values[22]	1750	1			T7	1		T9	4		T10	2
all_values[23]	1763	1			T9	5		T15	1		T27	14
all_values[24]	1668	1			T10	2		T15	1		T27	14
all_values[25]	1625	1			T7	4		T9	3		T10	1
all_values[26]	1730	1			T7	1		T27	16		T18	34
all_values[27]	1712	1			T9	2		T10	1		T15	3
all_values[28]	1681	1			T7	2		T9	7		T15	1
all_values[29]	1686	1			T9	1		T10	2		T15	2
all_values[30]	1742	1			T9	5		T15	2		T27	16
all_values[31]	1708	1			T7	1		T9	1		T27	12
all_values[32]	1649	1			T7	1		T9	6		T10	1
all_values[33]	1651	1			T9	3		T15	3		T27	10
all_values[34]	1713	1			T7	1		T9	4		T15	2
all_values[35]	1659	1			T9	4		T15	3		T27	12
all_values[36]	1704	1			T9	2		T10	1		T15	2
all_values[37]	1710	1			T7	1		T9	3		T15	2
all_values[38]	1707	1			T9	2		T15	1		T27	15
all_values[39]	1765	1			T7	1		T9	2		T27	13
all_values[40]	1749	1			T7	1		T9	5		T10	1
all_values[41]	1725	1			T7	1		T9	3		T15	1
all_values[42]	1770	1			T7	1		T9	2		T10	1
all_values[43]	1697	1			T7	1		T9	4		T10	2
all_values[44]	1713	1			T9	3		T15	2		T27	17
all_values[45]	1650	1			T9	3		T15	3		T27	13
all_values[46]	1730	1			T7	1		T9	4		T15	1
all_values[47]	1672	1			T9	3		T15	3		T27	14
all_values[48]	1713	1			T7	2		T9	5		T15	1
all_values[49]	1667	1			T9	3		T10	1		T15	4
all_values[50]	1721	1			T7	3		T9	6		T10	4
all_values[51]	1757	1			T7	3		T9	3		T10	2
all_values[52]	1725	1			T9	5		T15	3		T27	15
all_values[53]	1715	1			T7	3		T9	4		T10	1
all_values[54]	1754	1			T7	3		T9	1		T10	1
all_values[55]	1680	1			T7	4		T9	2		T10	1
all_values[56]	1743	1			T9	3		T10	1		T27	6
all_values[57]	1702	1			T9	5		T27	6		T18	31
all_values[58]	1703	1			T7	1		T9	1		T10	1
all_values[59]	1623	1			T10	1		T27	5		T18	26
all_values[60]	1670	1			T7	2		T9	6		T10	3
all_values[61]	1698	1			T7	1		T9	2		T15	2
all_values[62]	1766	1			T7	1		T9	3		T10	2
all_values[63]	1699	1			T9	6		T15	4		T27	11