Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1773	1			T17	12		T18	3		T19	3
all_values[1]	1735	1			T16	1		T17	7		T18	3
all_values[2]	1804	1			T16	1		T17	3		T18	2
all_values[3]	1716	1			T16	2		T17	4		T18	2
all_values[4]	1819	1			T17	7		T18	3		T19	5
all_values[5]	1771	1			T16	2		T17	4		T18	3
all_values[6]	1733	1			T16	1		T17	7		T18	2
all_values[7]	1727	1			T16	2		T17	3		T18	1
all_values[8]	1737	1			T17	2		T18	3		T19	3
all_values[9]	1735	1			T16	4		T17	5		T18	3
all_values[10]	1724	1			T17	5		T18	3		T19	1
all_values[11]	1744	1			T16	1		T17	5		T18	2
all_values[12]	1710	1			T17	3		T18	1		T19	5
all_values[13]	1839	1			T16	2		T17	4		T18	1
all_values[14]	1720	1			T16	2		T17	4		T19	4
all_values[15]	1777	1			T16	1		T17	5		T18	4
all_values[16]	1762	1			T17	3		T19	3		T20	36
all_values[17]	1726	1			T17	5		T19	2		T20	30
all_values[18]	1750	1			T16	1		T17	2		T18	4
all_values[19]	1791	1			T17	7		T18	2		T19	1
all_values[20]	1789	1			T16	3		T17	4		T18	4
all_values[21]	1747	1			T16	1		T17	4		T18	1
all_values[22]	1722	1			T16	1		T17	4		T18	2
all_values[23]	1717	1			T16	1		T17	5		T18	4
all_values[24]	1826	1			T16	1		T17	7		T19	2
all_values[25]	1670	1			T16	1		T17	3		T18	3
all_values[26]	1708	1			T16	1		T17	1		T18	3
all_values[27]	1789	1			T17	8		T18	4		T19	2
all_values[28]	1700	1			T16	1		T17	5		T18	1
all_values[29]	1742	1			T16	3		T17	7		T18	3
all_values[30]	1777	1			T17	2		T18	1		T19	6
all_values[31]	1731	1			T17	4		T18	2		T19	7
all_values[32]	1791	1			T16	1		T17	3		T18	4
all_values[33]	1740	1			T16	2		T17	4		T18	2
all_values[34]	1822	1			T16	3		T17	2		T18	5
all_values[35]	1789	1			T16	1		T17	9		T18	2
all_values[36]	1696	1			T16	1		T17	2		T18	1
all_values[37]	1767	1			T16	1		T17	3		T18	1
all_values[38]	1737	1			T16	1		T17	6		T18	1
all_values[39]	1761	1			T16	1		T17	5		T18	1
all_values[40]	1845	1			T16	1		T17	8		T18	4
all_values[41]	1786	1			T16	1		T17	5		T18	4
all_values[42]	1823	1			T17	6		T18	2		T19	6
all_values[43]	1747	1			T16	2		T17	3		T18	4
all_values[44]	1656	1			T17	10		T18	3		T19	4
all_values[45]	1728	1			T16	2		T17	6		T18	3
all_values[46]	1692	1			T16	1		T17	2		T18	1
all_values[47]	1686	1			T16	1		T17	7		T18	1
all_values[48]	1762	1			T16	2		T17	4		T18	2
all_values[49]	1703	1			T16	2		T17	4		T18	2
all_values[50]	1770	1			T16	1		T17	11		T18	1
all_values[51]	1726	1			T16	1		T17	8		T18	1
all_values[52]	1724	1			T16	1		T17	2		T19	2
all_values[53]	1708	1			T17	6		T19	4		T20	26
all_values[54]	1710	1			T17	3		T18	1		T19	2
all_values[55]	1754	1			T16	1		T17	9		T18	2
all_values[56]	1866	1			T16	1		T17	8		T19	4
all_values[57]	1735	1			T17	1		T18	2		T19	5
all_values[58]	1760	1			T17	6		T18	2		T19	8
all_values[59]	1773	1			T16	2		T17	3		T18	6
all_values[60]	1662	1			T16	4		T17	2		T18	2
all_values[61]	1760	1			T16	1		T17	3		T18	2
all_values[62]	1791	1			T16	1		T17	3		T18	4
all_values[63]	1790	1			T16	1		T17	5		T18	2