Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 519 1 T2 5 T3 1 T19 5
all_values[1] 495 1 T2 3 T13 1 T15 1
all_values[2] 510 1 T2 6 T8 2 T10 1
all_values[3] 503 1 T2 4 T3 1 T10 1
all_values[4] 491 1 T2 3 T8 1 T32 3
all_values[5] 485 1 T2 4 T10 1 T32 1
all_values[6] 486 1 T2 9 T8 2 T17 1
all_values[7] 465 1 T2 7 T8 1 T10 1
all_values[8] 458 1 T2 3 T3 1 T8 1
all_values[9] 497 1 T2 10 T8 1 T13 3
all_values[10] 512 1 T2 6 T10 1 T13 1
all_values[11] 461 1 T2 5 T3 1 T8 1
all_values[12] 477 1 T2 5 T3 1 T8 2
all_values[13] 524 1 T2 4 T8 3 T10 2
all_values[14] 513 1 T2 5 T3 1 T10 3
all_values[15] 468 1 T2 9 T10 1 T15 1
all_values[16] 473 1 T2 3 T3 2 T8 2
all_values[17] 485 1 T2 5 T3 1 T8 1
all_values[18] 512 1 T2 7 T10 2 T13 1
all_values[19] 484 1 T2 3 T3 1 T8 2
all_values[20] 544 1 T2 9 T8 1 T10 1
all_values[21] 514 1 T2 7 T10 1 T15 1
all_values[22] 498 1 T2 5 T3 1 T8 3
all_values[23] 450 1 T2 3 T3 1 T15 1

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