Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1672	1			T2	25		T10	2		T32	5
all_values[1]	1702	1			T2	35		T31	1		T32	3
all_values[2]	1665	1			T2	26		T10	2		T31	1
all_values[3]	1666	1			T2	30		T10	1		T32	4
all_values[4]	1739	1			T2	26		T10	2		T31	2
all_values[5]	1716	1			T2	33		T10	2		T31	3
all_values[6]	1699	1			T2	17		T10	1		T31	1
all_values[7]	1671	1			T2	30		T10	3		T31	1
all_values[8]	1699	1			T2	24		T10	6		T31	3
all_values[9]	1710	1			T2	26		T10	3		T32	3
all_values[10]	1707	1			T2	36		T31	1		T32	1
all_values[11]	1730	1			T2	27		T10	2		T31	1
all_values[12]	1682	1			T2	39		T10	2		T31	2
all_values[13]	1691	1			T2	20		T10	3		T32	2
all_values[14]	1670	1			T2	27		T10	3		T32	3
all_values[15]	1754	1			T2	32		T10	1		T31	1
all_values[16]	1702	1			T2	42		T10	1		T31	2
all_values[17]	1677	1			T2	25		T10	1		T31	1
all_values[18]	1719	1			T2	31		T32	5		T53	2
all_values[19]	1734	1			T2	24		T10	1		T31	2
all_values[20]	1705	1			T2	32		T31	2		T32	3
all_values[21]	1625	1			T2	45		T10	1		T31	1
all_values[22]	1731	1			T2	30		T10	1		T32	1
all_values[23]	1713	1			T2	37		T10	1		T32	1
all_values[24]	1716	1			T2	27		T10	3		T53	3
all_values[25]	1674	1			T2	41		T10	1		T31	3
all_values[26]	1698	1			T2	38		T10	2		T31	3
all_values[27]	1681	1			T2	28		T10	3		T32	4
all_values[28]	1757	1			T2	29		T31	2		T32	2
all_values[29]	1725	1			T2	31		T32	2		T19	12
all_values[30]	1772	1			T2	27		T10	2		T32	5
all_values[31]	1655	1			T2	26		T10	1		T31	1
all_values[32]	1768	1			T2	35		T10	1		T32	4
all_values[33]	1737	1			T2	35		T32	6		T53	3
all_values[34]	1786	1			T2	49		T10	4		T31	1
all_values[35]	1718	1			T2	25		T10	2		T31	1
all_values[36]	1667	1			T2	36		T10	2		T32	3
all_values[37]	1699	1			T2	26		T10	1		T32	5
all_values[38]	1769	1			T2	34		T10	3		T31	1
all_values[39]	1771	1			T2	23		T10	4		T31	1
all_values[40]	1738	1			T2	33		T10	1		T31	1
all_values[41]	1682	1			T2	25		T10	1		T31	4
all_values[42]	1662	1			T2	41		T10	3		T32	3
all_values[43]	1704	1			T2	27		T10	1		T31	2
all_values[44]	1812	1			T2	33		T10	1		T31	1
all_values[45]	1764	1			T2	19		T10	1		T31	1
all_values[46]	1692	1			T2	33		T10	2		T31	1
all_values[47]	1745	1			T2	37		T10	1		T31	1
all_values[48]	1753	1			T2	30		T10	2		T31	1
all_values[49]	1653	1			T2	40		T10	1		T32	2
all_values[50]	1669	1			T2	35		T10	5		T31	1
all_values[51]	1711	1			T2	19		T10	1		T31	2
all_values[52]	1710	1			T2	26		T10	2		T31	3
all_values[53]	1671	1			T2	40		T10	1		T31	2
all_values[54]	1690	1			T2	28		T10	2		T31	1
all_values[55]	1725	1			T2	29		T10	2		T31	2
all_values[56]	1735	1			T2	34		T10	3		T32	1
all_values[57]	1721	1			T2	41		T10	3		T32	2
all_values[58]	1679	1			T2	41		T10	3		T32	2
all_values[59]	1729	1			T2	26		T10	3		T31	1
all_values[60]	1742	1			T2	39		T10	3		T31	2
all_values[61]	1697	1			T2	34		T31	1		T32	4
all_values[62]	1707	1			T2	29		T32	7		T53	1
all_values[63]	1739	1			T2	40		T10	1		T31	1