Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1770	1			T12	35		T13	8		T17	4
all_values[1]	1747	1			T12	25		T13	10		T17	3
all_values[2]	1785	1			T12	29		T13	8		T17	3
all_values[3]	1688	1			T12	29		T13	12		T17	2
all_values[4]	1785	1			T12	39		T13	7		T62	4
all_values[5]	1769	1			T12	23		T13	5		T17	2
all_values[6]	1666	1			T12	22		T13	4		T17	2
all_values[7]	1762	1			T12	26		T13	5		T17	4
all_values[8]	1715	1			T12	30		T13	13		T17	1
all_values[9]	1719	1			T12	42		T13	5		T17	2
all_values[10]	1753	1			T12	28		T13	11		T17	3
all_values[11]	1779	1			T12	39		T13	6		T17	5
all_values[12]	1694	1			T12	27		T13	4		T17	2
all_values[13]	1751	1			T12	33		T13	9		T17	4
all_values[14]	1683	1			T12	26		T13	6		T17	3
all_values[15]	1687	1			T12	25		T13	6		T17	4
all_values[16]	1761	1			T12	33		T13	8		T18	1
all_values[17]	1749	1			T12	26		T13	9		T17	6
all_values[18]	1700	1			T12	27		T13	5		T17	5
all_values[19]	1796	1			T12	31		T13	5		T21	12
all_values[20]	1711	1			T12	27		T13	7		T17	2
all_values[21]	1743	1			T12	35		T13	9		T17	3
all_values[22]	1703	1			T12	27		T13	9		T17	1
all_values[23]	1730	1			T12	39		T13	6		T17	1
all_values[24]	1759	1			T12	28		T13	8		T17	2
all_values[25]	1706	1			T12	21		T13	9		T18	3
all_values[26]	1778	1			T12	45		T13	10		T17	2
all_values[27]	1735	1			T12	24		T13	4		T17	2
all_values[28]	1697	1			T12	35		T13	6		T17	1
all_values[29]	1672	1			T12	31		T13	9		T17	3
all_values[30]	1793	1			T12	27		T13	6		T17	3
all_values[31]	1728	1			T12	33		T13	8		T17	3
all_values[32]	1734	1			T12	31		T13	8		T17	5
all_values[33]	1702	1			T12	32		T13	10		T17	3
all_values[34]	1820	1			T12	33		T13	13		T17	2
all_values[35]	1727	1			T12	30		T13	9		T17	2
all_values[36]	1753	1			T12	24		T13	8		T62	6
all_values[37]	1727	1			T12	41		T13	10		T17	2
all_values[38]	1763	1			T12	27		T13	7		T17	5
all_values[39]	1748	1			T12	30		T13	8		T17	1
all_values[40]	1688	1			T12	22		T13	6		T17	1
all_values[41]	1792	1			T12	34		T13	7		T17	3
all_values[42]	1748	1			T12	27		T13	10		T17	2
all_values[43]	1724	1			T12	36		T13	8		T17	3
all_values[44]	1746	1			T12	26		T13	5		T17	2
all_values[45]	1836	1			T12	37		T13	10		T17	3
all_values[46]	1751	1			T12	32		T13	9		T17	1
all_values[47]	1744	1			T12	30		T13	4		T17	3
all_values[48]	1733	1			T12	36		T13	9		T17	1
all_values[49]	1704	1			T12	32		T13	11		T17	3
all_values[50]	1800	1			T12	42		T13	3		T17	5
all_values[51]	1809	1			T12	36		T13	11		T17	2
all_values[52]	1673	1			T12	35		T13	5		T17	7
all_values[53]	1713	1			T12	13		T13	12		T17	2
all_values[54]	1700	1			T12	29		T13	6		T17	3
all_values[55]	1793	1			T12	31		T13	11		T17	1
all_values[56]	1766	1			T12	34		T13	9		T17	3
all_values[57]	1693	1			T12	28		T13	7		T17	4
all_values[58]	1641	1			T12	21		T13	5		T18	1
all_values[59]	1785	1			T12	33		T13	6		T17	2
all_values[60]	1766	1			T12	25		T13	7		T17	5
all_values[61]	1785	1			T12	24		T13	7		T17	1
all_values[62]	1728	1			T12	24		T13	9		T17	2
all_values[63]	1735	1			T12	30		T13	10		T17	3