Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1585	1			T7	5		T11	26		T14	3
all_values[1]	1629	1			T3	1		T7	1		T11	22
all_values[2]	1668	1			T3	2		T7	4		T11	25
all_values[3]	1726	1			T3	2		T7	3		T11	24
all_values[4]	1700	1			T3	1		T7	3		T11	26
all_values[5]	1664	1			T3	1		T7	2		T11	22
all_values[6]	1753	1			T3	1		T7	2		T11	27
all_values[7]	1719	1			T3	1		T7	4		T11	21
all_values[8]	1633	1			T7	1		T11	27		T16	2
all_values[9]	1658	1			T3	4		T11	26		T14	1
all_values[10]	1662	1			T3	3		T7	4		T11	20
all_values[11]	1789	1			T3	1		T7	5		T11	22
all_values[12]	1680	1			T3	3		T7	4		T11	27
all_values[13]	1694	1			T3	1		T7	4		T11	35
all_values[14]	1670	1			T3	2		T7	2		T11	21
all_values[15]	1646	1			T3	3		T7	1		T11	23
all_values[16]	1659	1			T3	4		T7	4		T11	30
all_values[17]	1674	1			T3	2		T7	3		T11	29
all_values[18]	1661	1			T3	2		T7	6		T11	23
all_values[19]	1743	1			T3	1		T7	1		T11	27
all_values[20]	1725	1			T11	26		T16	3		T18	4
all_values[21]	1668	1			T3	1		T7	2		T11	19
all_values[22]	1698	1			T3	1		T7	3		T11	28
all_values[23]	1702	1			T7	5		T11	25		T14	3
all_values[24]	1675	1			T3	1		T7	1		T11	27
all_values[25]	1729	1			T7	2		T11	37		T14	1
all_values[26]	1657	1			T3	7		T7	2		T11	31
all_values[27]	1713	1			T3	2		T7	5		T11	32
all_values[28]	1626	1			T7	2		T11	22		T16	1
all_values[29]	1739	1			T3	1		T7	1		T11	33
all_values[30]	1662	1			T3	2		T7	3		T11	25
all_values[31]	1749	1			T3	3		T7	3		T11	21
all_values[32]	1617	1			T3	3		T7	4		T11	41
all_values[33]	1709	1			T3	1		T7	4		T11	28
all_values[34]	1603	1			T7	4		T11	24		T14	1
all_values[35]	1674	1			T3	1		T11	20		T14	1
all_values[36]	1734	1			T3	1		T7	4		T11	19
all_values[37]	1702	1			T3	2		T7	1		T11	26
all_values[38]	1695	1			T3	1		T7	5		T11	33
all_values[39]	1653	1			T3	1		T7	4		T11	20
all_values[40]	1733	1			T7	4		T11	28		T14	3
all_values[41]	1748	1			T3	3		T7	1		T11	20
all_values[42]	1667	1			T7	4		T11	27		T14	1
all_values[43]	1655	1			T3	2		T7	3		T11	28
all_values[44]	1684	1			T3	1		T7	2		T11	15
all_values[45]	1745	1			T3	1		T7	4		T11	30
all_values[46]	1699	1			T3	2		T7	6		T11	27
all_values[47]	1648	1			T3	2		T7	6		T11	35
all_values[48]	1702	1			T3	3		T7	1		T11	35
all_values[49]	1645	1			T7	2		T11	39		T14	4
all_values[50]	1658	1			T3	3		T7	4		T11	24
all_values[51]	1705	1			T3	3		T7	4		T11	28
all_values[52]	1691	1			T3	3		T7	3		T11	33
all_values[53]	1725	1			T3	1		T7	5		T11	19
all_values[54]	1758	1			T3	1		T7	3		T11	26
all_values[55]	1626	1			T7	3		T11	14		T14	2
all_values[56]	1674	1			T3	2		T7	3		T11	22
all_values[57]	1642	1			T7	2		T11	28		T14	4
all_values[58]	1607	1			T3	1		T7	2		T11	33
all_values[59]	1610	1			T7	1		T11	28		T16	5
all_values[60]	1693	1			T3	3		T7	1		T11	25
all_values[61]	1708	1			T3	2		T7	1		T11	14
all_values[62]	1677	1			T3	1		T7	2		T11	29
all_values[63]	1688	1			T7	3		T11	28		T14	1