Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1876	1			T1	2		T11	3		T13	8
all_values[1]	1791	1			T1	3		T11	2		T13	7
all_values[2]	1843	1			T1	1		T13	7		T14	31
all_values[3]	1831	1			T1	3		T11	3		T13	9
all_values[4]	1795	1			T1	2		T11	2		T13	9
all_values[5]	1845	1			T1	2		T11	3		T13	7
all_values[6]	1818	1			T1	3		T11	3		T13	7
all_values[7]	1809	1			T1	2		T13	7		T14	28
all_values[8]	1821	1			T1	2		T11	3		T13	9
all_values[9]	1822	1			T11	1		T13	13		T14	26
all_values[10]	1798	1			T1	4		T11	1		T13	7
all_values[11]	1932	1			T1	4		T11	3		T13	10
all_values[12]	1861	1			T1	6		T13	9		T14	23
all_values[13]	1800	1			T1	1		T11	1		T13	11
all_values[14]	1864	1			T1	1		T11	4		T13	5
all_values[15]	1840	1			T1	5		T11	1		T13	8
all_values[16]	1829	1			T1	4		T13	7		T14	31
all_values[17]	1783	1			T1	3		T11	1		T13	6
all_values[18]	1873	1			T1	4		T11	1		T13	9
all_values[19]	1827	1			T1	1		T11	1		T13	7
all_values[20]	1823	1			T1	2		T11	4		T13	8
all_values[21]	1801	1			T1	1		T11	4		T13	7
all_values[22]	1834	1			T1	2		T11	3		T13	10
all_values[23]	1894	1			T1	8		T11	2		T13	10
all_values[24]	1873	1			T1	2		T11	1		T13	8
all_values[25]	1859	1			T1	3		T11	3		T13	5
all_values[26]	1849	1			T1	3		T11	6		T13	13
all_values[27]	1857	1			T1	1		T11	1		T13	10
all_values[28]	1817	1			T1	2		T11	1		T13	8
all_values[29]	1808	1			T1	2		T11	1		T13	12
all_values[30]	1774	1			T1	2		T11	2		T13	8
all_values[31]	1886	1			T1	4		T11	2		T13	11
all_values[32]	1826	1			T1	3		T11	1		T13	6
all_values[33]	1850	1			T1	3		T11	1		T13	9
all_values[34]	1856	1			T1	3		T11	2		T13	15
all_values[35]	1878	1			T1	7		T11	2		T13	7
all_values[36]	1853	1			T1	4		T11	1		T13	14
all_values[37]	1841	1			T1	2		T13	12		T14	35
all_values[38]	1913	1			T1	2		T11	3		T13	8
all_values[39]	1819	1			T1	3		T11	4		T13	16
all_values[40]	1840	1			T1	6		T11	3		T13	6
all_values[41]	1822	1			T1	2		T11	4		T13	12
all_values[42]	1827	1			T1	4		T11	2		T13	13
all_values[43]	1821	1			T1	2		T11	1		T13	5
all_values[44]	1821	1			T1	2		T11	1		T13	15
all_values[45]	1858	1			T1	3		T11	3		T13	8
all_values[46]	1868	1			T1	1		T11	2		T13	11
all_values[47]	1941	1			T1	5		T11	2		T13	10
all_values[48]	1808	1			T1	4		T11	3		T13	8
all_values[49]	1850	1			T1	4		T11	1		T13	10
all_values[50]	1856	1			T1	1		T11	2		T13	12
all_values[51]	1850	1			T1	1		T11	1		T13	9
all_values[52]	1810	1			T1	3		T11	2		T13	6
all_values[53]	1858	1			T1	4		T11	5		T13	10
all_values[54]	1903	1			T1	6		T11	1		T13	9
all_values[55]	1848	1			T1	7		T11	6		T13	6
all_values[56]	1901	1			T1	2		T11	4		T13	5
all_values[57]	1819	1			T1	3		T11	1		T13	9
all_values[58]	1840	1			T1	3		T11	2		T13	9
all_values[59]	1802	1			T1	4		T11	2		T13	9
all_values[60]	1852	1			T1	1		T13	3		T14	35
all_values[61]	1853	1			T1	1		T13	11		T14	29
all_values[62]	1839	1			T1	3		T11	1		T13	9
all_values[63]	1834	1			T1	2		T11	5		T13	13