Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1809	1			T8	3		T40	2		T16	2
all_values[1]	1880	1			T1	1		T8	7		T40	2
all_values[2]	1813	1			T8	4		T40	2		T16	1
all_values[3]	1828	1			T1	1		T8	9		T16	7
all_values[4]	1891	1			T8	1		T40	5		T16	4
all_values[5]	1836	1			T8	7		T40	1		T16	4
all_values[6]	1862	1			T1	1		T8	2		T40	2
all_values[7]	1788	1			T8	4		T40	3		T16	3
all_values[8]	1781	1			T1	1		T8	2		T16	5
all_values[9]	1817	1			T1	1		T8	5		T40	2
all_values[10]	1791	1			T8	3		T40	2		T16	3
all_values[11]	1838	1			T8	8		T40	3		T16	3
all_values[12]	1808	1			T8	7		T40	1		T16	5
all_values[13]	1855	1			T8	4		T40	2		T16	3
all_values[14]	1790	1			T1	1		T8	3		T16	2
all_values[15]	1835	1			T8	3		T40	1		T16	2
all_values[16]	1875	1			T1	1		T8	5		T40	2
all_values[17]	1752	1			T1	1		T8	4		T40	4
all_values[18]	1755	1			T8	4		T40	6		T16	3
all_values[19]	1780	1			T8	4		T40	2		T16	3
all_values[20]	1852	1			T8	4		T40	3		T16	3
all_values[21]	1878	1			T1	2		T8	2		T40	2
all_values[22]	1803	1			T8	3		T40	1		T16	1
all_values[23]	1809	1			T1	1		T8	9		T40	1
all_values[24]	1781	1			T8	3		T40	5		T16	4
all_values[25]	1858	1			T1	1		T8	4		T40	1
all_values[26]	1855	1			T1	1		T8	4		T40	2
all_values[27]	1823	1			T8	2		T40	1		T16	2
all_values[28]	1770	1			T8	3		T40	3		T16	1
all_values[29]	1817	1			T8	2		T40	4		T16	2
all_values[30]	1866	1			T8	5		T40	3		T16	2
all_values[31]	1735	1			T1	1		T8	6		T40	2
all_values[32]	1857	1			T8	2		T40	2		T16	1
all_values[33]	1882	1			T1	1		T8	3		T40	5
all_values[34]	1885	1			T8	6		T40	2		T16	2
all_values[35]	1758	1			T8	3		T40	2		T17	3
all_values[36]	1892	1			T1	1		T8	4		T40	3
all_values[37]	1825	1			T8	5		T40	3		T16	3
all_values[38]	1859	1			T8	5		T40	4		T16	4
all_values[39]	1855	1			T1	2		T8	5		T16	2
all_values[40]	1854	1			T1	1		T8	2		T40	1
all_values[41]	1807	1			T1	1		T8	4		T40	3
all_values[42]	1849	1			T8	2		T40	2		T16	6
all_values[43]	1780	1			T1	1		T8	3		T40	6
all_values[44]	1771	1			T1	1		T8	3		T40	1
all_values[45]	1851	1			T8	6		T40	1		T16	7
all_values[46]	1801	1			T8	5		T40	1		T16	6
all_values[47]	1915	1			T8	3		T40	3		T16	1
all_values[48]	1744	1			T1	1		T8	1		T40	5
all_values[49]	1865	1			T8	4		T16	1		T17	6
all_values[50]	1854	1			T1	1		T8	7		T40	1
all_values[51]	1824	1			T8	6		T40	1		T16	5
all_values[52]	1798	1			T1	1		T8	4		T40	4
all_values[53]	1817	1			T1	1		T8	7		T40	3
all_values[54]	1787	1			T8	3		T40	3		T16	1
all_values[55]	1826	1			T1	1		T8	2		T40	4
all_values[56]	1817	1			T8	2		T40	1		T17	4
all_values[57]	1790	1			T8	5		T40	1		T16	5
all_values[58]	1832	1			T8	4		T40	2		T16	2
all_values[59]	1805	1			T1	3		T8	6		T40	4
all_values[60]	1757	1			T1	2		T8	5		T40	2
all_values[61]	1794	1			T8	4		T40	1		T16	2
all_values[62]	1845	1			T1	1		T8	3		T40	6
all_values[63]	1783	1			T1	1		T8	3		T40	5