Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 447 1 T2 4 T11 6 T14 6
all_values[1] 459 1 T2 3 T11 7 T14 12
all_values[2] 480 1 T2 2 T11 8 T12 1
all_values[3] 433 1 T2 2 T11 7 T12 1
all_values[4] 482 1 T2 4 T11 6 T12 3
all_values[5] 478 1 T2 2 T11 2 T12 2
all_values[6] 484 1 T2 3 T11 3 T14 9
all_values[7] 498 1 T2 2 T11 6 T12 1
all_values[8] 481 1 T2 3 T11 4 T14 10
all_values[9] 468 1 T2 5 T11 3 T14 6
all_values[10] 420 1 T2 2 T11 6 T14 8
all_values[11] 424 1 T2 5 T11 4 T14 9
all_values[12] 439 1 T2 5 T11 11 T14 6
all_values[13] 431 1 T2 4 T11 2 T14 6
all_values[14] 502 1 T2 4 T11 4 T12 4
all_values[15] 487 1 T2 2 T11 7 T14 7
all_values[16] 417 1 T2 2 T11 2 T14 8
all_values[17] 471 1 T2 5 T11 6 T14 5
all_values[18] 484 1 T2 2 T11 2 T12 3
all_values[19] 468 1 T2 4 T11 8 T12 1
all_values[20] 443 1 T2 4 T11 4 T14 10
all_values[21] 461 1 T2 3 T11 5 T12 1
all_values[22] 480 1 T2 3 T11 10 T12 1
all_values[23] 466 1 T2 2 T11 4 T14 8

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