Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1716	1			T2	22		T11	22		T14	30
all_values[1]	1766	1			T2	28		T11	25		T14	31
all_values[2]	1819	1			T2	25		T11	21		T14	33
all_values[3]	1770	1			T2	23		T11	25		T14	30
all_values[4]	1712	1			T2	34		T11	19		T14	43
all_values[5]	1766	1			T2	18		T11	26		T12	1
all_values[6]	1753	1			T2	23		T11	29		T12	1
all_values[7]	1688	1			T2	19		T11	25		T14	38
all_values[8]	1661	1			T2	27		T11	23		T14	39
all_values[9]	1798	1			T2	18		T11	15		T14	32
all_values[10]	1754	1			T2	26		T11	27		T14	33
all_values[11]	1672	1			T2	18		T11	18		T14	33
all_values[12]	1729	1			T2	25		T11	19		T12	2
all_values[13]	1718	1			T2	18		T11	29		T14	41
all_values[14]	1723	1			T2	22		T11	16		T14	33
all_values[15]	1737	1			T2	19		T11	21		T12	1
all_values[16]	1706	1			T2	29		T11	13		T12	1
all_values[17]	1754	1			T2	25		T11	16		T12	3
all_values[18]	1761	1			T2	22		T11	22		T14	34
all_values[19]	1770	1			T2	21		T11	30		T12	1
all_values[20]	1744	1			T2	18		T11	25		T14	40
all_values[21]	1751	1			T2	24		T11	19		T12	3
all_values[22]	1730	1			T2	26		T11	15		T12	1
all_values[23]	1807	1			T2	37		T11	25		T14	38
all_values[24]	1742	1			T2	35		T11	30		T12	1
all_values[25]	1719	1			T2	22		T11	22		T14	31
all_values[26]	1748	1			T2	23		T11	30		T14	47
all_values[27]	1649	1			T2	21		T11	30		T12	1
all_values[28]	1721	1			T2	24		T11	26		T14	33
all_values[29]	1623	1			T2	16		T11	21		T12	1
all_values[30]	1713	1			T2	21		T11	25		T14	38
all_values[31]	1781	1			T2	28		T11	20		T12	1
all_values[32]	1782	1			T2	22		T11	23		T14	30
all_values[33]	1761	1			T2	19		T11	20		T14	43
all_values[34]	1718	1			T2	20		T11	11		T12	1
all_values[35]	1768	1			T2	26		T11	15		T12	1
all_values[36]	1730	1			T2	22		T11	24		T14	38
all_values[37]	1746	1			T2	20		T11	19		T14	43
all_values[38]	1707	1			T2	25		T11	22		T14	39
all_values[39]	1734	1			T2	31		T11	22		T12	1
all_values[40]	1788	1			T2	25		T11	24		T14	46
all_values[41]	1780	1			T2	22		T11	23		T12	2
all_values[42]	1768	1			T2	25		T11	20		T12	1
all_values[43]	1667	1			T2	31		T11	13		T14	20
all_values[44]	1791	1			T2	23		T11	27		T14	33
all_values[45]	1727	1			T2	28		T11	22		T14	30
all_values[46]	1703	1			T2	20		T11	21		T14	37
all_values[47]	1705	1			T2	13		T11	20		T12	1
all_values[48]	1693	1			T2	19		T11	21		T12	1
all_values[49]	1780	1			T2	27		T11	22		T12	1
all_values[50]	1677	1			T2	12		T11	22		T12	1
all_values[51]	1722	1			T2	29		T11	19		T14	37
all_values[52]	1766	1			T2	23		T11	19		T14	41
all_values[53]	1660	1			T2	30		T11	31		T12	2
all_values[54]	1720	1			T2	25		T11	29		T12	1
all_values[55]	1738	1			T2	21		T11	26		T12	2
all_values[56]	1643	1			T2	15		T11	21		T12	1
all_values[57]	1714	1			T2	31		T11	23		T12	1
all_values[58]	1695	1			T2	28		T11	25		T14	34
all_values[59]	1727	1			T2	19		T11	18		T14	43
all_values[60]	1727	1			T2	29		T11	18		T14	30
all_values[61]	1826	1			T2	27		T11	27		T14	46
all_values[62]	1736	1			T2	22		T11	16		T14	45
all_values[63]	1729	1			T2	26		T11	18		T12	1