Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1820	1			T9	2		T10	3		T15	13
all_values[1]	1773	1			T9	1		T10	3		T15	10
all_values[2]	1833	1			T9	6		T10	1		T15	17
all_values[3]	1774	1			T9	6		T10	2		T15	12
all_values[4]	1807	1			T9	3		T10	3		T15	13
all_values[5]	1707	1			T9	6		T10	2		T15	12
all_values[6]	1747	1			T9	6		T10	1		T15	12
all_values[7]	1752	1			T9	3		T10	1		T15	8
all_values[8]	1787	1			T9	7		T15	13		T37	9
all_values[9]	1709	1			T9	8		T10	1		T15	12
all_values[10]	1849	1			T9	12		T10	1		T15	16
all_values[11]	1753	1			T9	7		T15	20		T37	11
all_values[12]	1696	1			T9	8		T10	1		T15	15
all_values[13]	1752	1			T9	3		T10	3		T15	14
all_values[14]	1754	1			T9	6		T15	11		T37	10
all_values[15]	1795	1			T9	6		T10	2		T15	10
all_values[16]	1752	1			T9	6		T10	4		T15	8
all_values[17]	1679	1			T9	7		T15	10		T37	7
all_values[18]	1791	1			T9	3		T10	2		T15	9
all_values[19]	1819	1			T9	6		T15	16		T37	6
all_values[20]	1717	1			T9	6		T10	1		T15	9
all_values[21]	1767	1			T9	10		T10	4		T15	11
all_values[22]	1874	1			T9	8		T10	3		T15	18
all_values[23]	1735	1			T9	5		T10	2		T15	24
all_values[24]	1778	1			T9	6		T15	14		T37	6
all_values[25]	1732	1			T9	5		T10	1		T15	11
all_values[26]	1719	1			T9	3		T10	1		T15	10
all_values[27]	1824	1			T9	6		T10	3		T15	16
all_values[28]	1701	1			T9	4		T10	3		T15	6
all_values[29]	1762	1			T9	5		T10	1		T15	19
all_values[30]	1834	1			T9	2		T10	4		T15	14
all_values[31]	1773	1			T9	4		T10	3		T15	5
all_values[32]	1809	1			T9	10		T15	19		T37	7
all_values[33]	1766	1			T9	5		T10	1		T15	14
all_values[34]	1776	1			T9	8		T10	4		T15	15
all_values[35]	1773	1			T9	13		T10	1		T15	20
all_values[36]	1746	1			T9	4		T10	1		T15	10
all_values[37]	1754	1			T9	4		T10	1		T15	16
all_values[38]	1711	1			T9	5		T10	1		T15	11
all_values[39]	1757	1			T9	4		T10	2		T15	17
all_values[40]	1802	1			T9	5		T15	9		T37	10
all_values[41]	1761	1			T9	8		T10	2		T15	13
all_values[42]	1758	1			T9	4		T10	2		T15	13
all_values[43]	1761	1			T9	12		T15	11		T37	8
all_values[44]	1729	1			T9	5		T10	1		T15	11
all_values[45]	1773	1			T9	7		T10	2		T15	22
all_values[46]	1802	1			T9	7		T15	16		T37	12
all_values[47]	1810	1			T9	4		T10	1		T15	7
all_values[48]	1731	1			T9	6		T10	1		T15	14
all_values[49]	1768	1			T9	8		T15	9		T37	6
all_values[50]	1760	1			T9	5		T10	1		T15	10
all_values[51]	1710	1			T9	4		T10	1		T15	9
all_values[52]	1841	1			T9	2		T10	1		T15	8
all_values[53]	1669	1			T9	6		T15	14		T37	9
all_values[54]	1708	1			T9	4		T10	2		T15	15
all_values[55]	1731	1			T9	2		T10	2		T15	12
all_values[56]	1780	1			T9	9		T10	1		T15	14
all_values[57]	1799	1			T9	5		T10	2		T15	13
all_values[58]	1737	1			T9	7		T10	1		T15	9
all_values[59]	1815	1			T9	8		T10	3		T15	10
all_values[60]	1811	1			T9	6		T15	13		T37	8
all_values[61]	1832	1			T9	12		T10	2		T15	15
all_values[62]	1805	1			T9	5		T10	1		T15	15
all_values[63]	1787	1			T9	5		T10	2		T15	17