Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1775	1			T1	1		T7	9		T9	2
all_values[1]	1850	1			T1	2		T7	3		T9	1
all_values[2]	1759	1			T7	10		T9	3		T11	3
all_values[3]	1831	1			T1	2		T7	5		T11	3
all_values[4]	1758	1			T1	4		T7	6		T9	2
all_values[5]	1761	1			T7	9		T9	3		T11	1
all_values[6]	1760	1			T1	5		T7	6		T9	3
all_values[7]	1723	1			T1	3		T7	6		T9	3
all_values[8]	1732	1			T1	1		T7	5		T9	2
all_values[9]	1774	1			T1	3		T7	9		T11	4
all_values[10]	1737	1			T1	1		T7	7		T11	3
all_values[11]	1776	1			T1	2		T7	7		T9	3
all_values[12]	1806	1			T1	1		T7	9		T9	1
all_values[13]	1813	1			T1	1		T7	2		T9	1
all_values[14]	1889	1			T1	3		T7	6		T9	2
all_values[15]	1830	1			T1	4		T7	4		T9	2
all_values[16]	1685	1			T1	2		T7	12		T9	1
all_values[17]	1768	1			T1	2		T7	4		T9	1
all_values[18]	1773	1			T1	2		T7	6		T11	5
all_values[19]	1757	1			T7	4		T9	2		T11	6
all_values[20]	1826	1			T1	2		T7	7		T9	1
all_values[21]	1812	1			T7	5		T9	1		T11	5
all_values[22]	1875	1			T1	3		T7	8		T9	3
all_values[23]	1857	1			T1	3		T7	8		T11	2
all_values[24]	1735	1			T7	7		T9	3		T14	2
all_values[25]	1810	1			T1	3		T7	5		T9	3
all_values[26]	1815	1			T1	2		T7	1		T9	2
all_values[27]	1787	1			T1	2		T7	3		T9	3
all_values[28]	1837	1			T1	3		T7	8		T9	1
all_values[29]	1747	1			T1	2		T7	3		T9	1
all_values[30]	1802	1			T1	1		T7	7		T11	1
all_values[31]	1763	1			T1	2		T7	9		T11	1
all_values[32]	1740	1			T1	2		T7	7		T9	1
all_values[33]	1734	1			T1	4		T7	7		T9	3
all_values[34]	1808	1			T1	2		T7	7		T11	1
all_values[35]	1734	1			T1	1		T7	8		T9	4
all_values[36]	1745	1			T1	2		T7	4		T11	6
all_values[37]	1789	1			T1	1		T7	7		T9	4
all_values[38]	1800	1			T1	4		T7	6		T9	2
all_values[39]	1777	1			T1	2		T7	5		T9	7
all_values[40]	1823	1			T1	1		T7	5		T9	4
all_values[41]	1780	1			T1	1		T7	2		T9	2
all_values[42]	1807	1			T1	1		T7	8		T9	1
all_values[43]	1795	1			T1	1		T7	7		T9	2
all_values[44]	1828	1			T1	2		T7	3		T9	1
all_values[45]	1780	1			T1	2		T7	12		T11	2
all_values[46]	1798	1			T1	4		T7	10		T9	1
all_values[47]	1812	1			T1	1		T7	6		T11	3
all_values[48]	1684	1			T1	2		T7	5		T9	1
all_values[49]	1760	1			T1	1		T7	7		T11	5
all_values[50]	1823	1			T1	5		T7	3		T9	6
all_values[51]	1730	1			T1	1		T7	5		T11	2
all_values[52]	1784	1			T1	2		T7	9		T9	1
all_values[53]	1885	1			T1	1		T7	10		T9	1
all_values[54]	1788	1			T1	2		T7	7		T9	1
all_values[55]	1770	1			T1	3		T7	7		T9	2
all_values[56]	1741	1			T1	7		T7	7		T9	2
all_values[57]	1823	1			T1	3		T7	8		T9	4
all_values[58]	1770	1			T1	2		T7	8		T9	2
all_values[59]	1721	1			T1	4		T7	11		T9	2
all_values[60]	1786	1			T1	4		T7	8		T9	2
all_values[61]	1853	1			T1	7		T7	11		T11	1
all_values[62]	1796	1			T1	1		T7	3		T11	2
all_values[63]	1740	1			T1	1		T7	6		T9	2