Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1789	1			T1	8		T15	2		T16	2
all_values[1]	1831	1			T1	3		T15	1		T16	2
all_values[2]	1756	1			T1	9		T15	2		T16	1
all_values[3]	1773	1			T1	6		T16	4		T19	22
all_values[4]	1850	1			T1	5		T15	1		T16	2
all_values[5]	1781	1			T1	11		T16	5		T19	27
all_values[6]	1712	1			T1	5		T15	1		T16	3
all_values[7]	1798	1			T1	8		T15	1		T16	2
all_values[8]	1754	1			T1	4		T16	5		T18	1
all_values[9]	1844	1			T1	4		T16	4		T18	1
all_values[10]	1848	1			T1	5		T16	3		T18	1
all_values[11]	1774	1			T1	3		T16	2		T18	1
all_values[12]	1803	1			T1	6		T15	1		T16	1
all_values[13]	1807	1			T1	8		T15	1		T16	3
all_values[14]	1790	1			T1	5		T15	2		T16	1
all_values[15]	1809	1			T1	13		T16	2		T18	1
all_values[16]	1725	1			T1	9		T15	2		T16	2
all_values[17]	1800	1			T1	5		T16	1		T18	3
all_values[18]	1839	1			T1	14		T15	1		T16	2
all_values[19]	1806	1			T1	8		T16	3		T18	2
all_values[20]	1824	1			T1	12		T15	1		T18	1
all_values[21]	1813	1			T1	4		T15	1		T16	3
all_values[22]	1743	1			T1	6		T15	1		T18	3
all_values[23]	1757	1			T1	9		T15	1		T16	2
all_values[24]	1758	1			T1	6		T15	1		T16	2
all_values[25]	1752	1			T1	11		T18	1		T19	17
all_values[26]	1792	1			T1	2		T16	2		T18	3
all_values[27]	1757	1			T1	7		T15	1		T16	4
all_values[28]	1746	1			T1	7		T15	2		T18	1
all_values[29]	1765	1			T1	11		T15	2		T16	2
all_values[30]	1756	1			T1	7		T16	2		T19	21
all_values[31]	1731	1			T1	8		T15	1		T16	1
all_values[32]	1789	1			T1	9		T16	7		T18	1
all_values[33]	1777	1			T1	6		T16	3		T18	2
all_values[34]	1754	1			T1	10		T16	3		T18	3
all_values[35]	1839	1			T1	4		T16	5		T18	1
all_values[36]	1776	1			T1	8		T15	1		T16	1
all_values[37]	1775	1			T1	8		T16	1		T18	1
all_values[38]	1797	1			T1	7		T15	2		T16	1
all_values[39]	1835	1			T1	5		T18	3		T19	16
all_values[40]	1721	1			T1	14		T15	1		T16	4
all_values[41]	1896	1			T1	12		T15	1		T16	3
all_values[42]	1803	1			T1	9		T16	2		T18	1
all_values[43]	1781	1			T1	8		T15	2		T16	5
all_values[44]	1779	1			T1	9		T15	1		T18	1
all_values[45]	1844	1			T1	5		T16	1		T18	1
all_values[46]	1806	1			T1	8		T16	2		T18	1
all_values[47]	1770	1			T1	8		T15	1		T16	1
all_values[48]	1821	1			T1	11		T16	2		T18	2
all_values[49]	1803	1			T1	9		T16	5		T18	2
all_values[50]	1829	1			T1	9		T16	4		T19	9
all_values[51]	1817	1			T1	10		T15	1		T16	5
all_values[52]	1742	1			T1	8		T15	3		T16	1
all_values[53]	1748	1			T1	8		T15	1		T16	2
all_values[54]	1819	1			T1	8		T15	1		T16	1
all_values[55]	1756	1			T1	6		T16	4		T18	3
all_values[56]	1687	1			T1	8		T15	1		T16	3
all_values[57]	1899	1			T1	9		T18	1		T19	15
all_values[58]	1729	1			T1	4		T19	9		T20	7
all_values[59]	1783	1			T1	10		T15	2		T16	2
all_values[60]	1694	1			T1	7		T15	1		T16	2
all_values[61]	1858	1			T1	9		T16	1		T18	2
all_values[62]	1791	1			T1	9		T15	1		T16	5
all_values[63]	1747	1			T1	8		T15	1		T16	4