Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.03 99.26 88.97 98.80 95.88 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T759 /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1186297313 Jul 12 05:57:08 PM PDT 24 Jul 12 05:59:13 PM PDT 24 22835118534 ps
T760 /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3807064748 Jul 12 05:57:06 PM PDT 24 Jul 12 05:57:59 PM PDT 24 9024178409 ps
T761 /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.609551592 Jul 12 05:55:39 PM PDT 24 Jul 12 05:55:42 PM PDT 24 27761513 ps
T762 /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1235033878 Jul 12 05:55:24 PM PDT 24 Jul 12 05:55:58 PM PDT 24 4636789051 ps
T763 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2288416589 Jul 12 05:55:32 PM PDT 24 Jul 12 06:04:16 PM PDT 24 101249965191 ps
T764 /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1056960540 Jul 12 05:57:44 PM PDT 24 Jul 12 05:58:22 PM PDT 24 7508100052 ps
T765 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3603050132 Jul 12 05:56:13 PM PDT 24 Jul 12 06:02:55 PM PDT 24 2496540983 ps
T766 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2811213151 Jul 12 05:56:11 PM PDT 24 Jul 12 05:56:17 PM PDT 24 226095763 ps
T767 /workspace/coverage/xbar_build_mode/8.xbar_error_random.424103627 Jul 12 05:55:27 PM PDT 24 Jul 12 05:55:37 PM PDT 24 237551145 ps
T768 /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.226498189 Jul 12 05:55:42 PM PDT 24 Jul 12 05:56:09 PM PDT 24 6115608414 ps
T769 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3801927994 Jul 12 05:57:57 PM PDT 24 Jul 12 06:07:28 PM PDT 24 231092518719 ps
T770 /workspace/coverage/xbar_build_mode/8.xbar_random.3017038888 Jul 12 05:55:33 PM PDT 24 Jul 12 05:56:20 PM PDT 24 7183664086 ps
T771 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4136138198 Jul 12 05:55:55 PM PDT 24 Jul 12 05:58:23 PM PDT 24 2607725475 ps
T772 /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3747388211 Jul 12 05:56:14 PM PDT 24 Jul 12 05:57:54 PM PDT 24 5001607537 ps
T773 /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3641802585 Jul 12 05:56:51 PM PDT 24 Jul 12 05:56:56 PM PDT 24 38753194 ps
T128 /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4059755173 Jul 12 05:56:27 PM PDT 24 Jul 12 05:56:49 PM PDT 24 200843726 ps
T774 /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2239697642 Jul 12 05:55:24 PM PDT 24 Jul 12 05:59:20 PM PDT 24 39939166407 ps
T775 /workspace/coverage/xbar_build_mode/2.xbar_smoke.1749449017 Jul 12 05:55:15 PM PDT 24 Jul 12 05:55:21 PM PDT 24 165498386 ps
T776 /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1895287226 Jul 12 05:58:21 PM PDT 24 Jul 12 06:01:02 PM PDT 24 3841212209 ps
T777 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3560499155 Jul 12 05:56:02 PM PDT 24 Jul 12 05:56:20 PM PDT 24 123468387 ps
T778 /workspace/coverage/xbar_build_mode/38.xbar_random.40198761 Jul 12 05:57:24 PM PDT 24 Jul 12 05:57:56 PM PDT 24 883408298 ps
T779 /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4008875312 Jul 12 05:56:26 PM PDT 24 Jul 12 05:57:06 PM PDT 24 23045690801 ps
T780 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3492976858 Jul 12 05:56:12 PM PDT 24 Jul 12 06:01:32 PM PDT 24 2979378532 ps
T781 /workspace/coverage/xbar_build_mode/39.xbar_random.70333654 Jul 12 05:57:31 PM PDT 24 Jul 12 05:57:56 PM PDT 24 92876504 ps
T782 /workspace/coverage/xbar_build_mode/11.xbar_smoke.1086854623 Jul 12 05:55:35 PM PDT 24 Jul 12 05:55:41 PM PDT 24 208891362 ps
T783 /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2659266484 Jul 12 05:56:12 PM PDT 24 Jul 12 05:56:49 PM PDT 24 9725592382 ps
T784 /workspace/coverage/xbar_build_mode/31.xbar_stress_all.25202948 Jul 12 05:56:56 PM PDT 24 Jul 12 05:59:14 PM PDT 24 3670049313 ps
T785 /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.816127527 Jul 12 05:56:24 PM PDT 24 Jul 12 05:56:33 PM PDT 24 219104079 ps
T786 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.806029732 Jul 12 05:55:43 PM PDT 24 Jul 12 05:56:28 PM PDT 24 107875313 ps
T233 /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1650724443 Jul 12 05:56:01 PM PDT 24 Jul 12 06:00:13 PM PDT 24 77954529888 ps
T787 /workspace/coverage/xbar_build_mode/39.xbar_smoke.3412695805 Jul 12 05:57:30 PM PDT 24 Jul 12 05:57:47 PM PDT 24 240080932 ps
T788 /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.4263127078 Jul 12 05:57:08 PM PDT 24 Jul 12 05:59:18 PM PDT 24 28113639376 ps
T789 /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2672353367 Jul 12 05:56:15 PM PDT 24 Jul 12 05:56:22 PM PDT 24 124297074 ps
T790 /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1674740902 Jul 12 05:55:47 PM PDT 24 Jul 12 05:57:41 PM PDT 24 1331867737 ps
T791 /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1842802802 Jul 12 05:55:35 PM PDT 24 Jul 12 06:01:20 PM PDT 24 242246278566 ps
T792 /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.803003116 Jul 12 05:56:09 PM PDT 24 Jul 12 05:56:17 PM PDT 24 154881615 ps
T793 /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1381960272 Jul 12 05:57:36 PM PDT 24 Jul 12 05:58:22 PM PDT 24 10104710569 ps
T794 /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1544685282 Jul 12 05:55:44 PM PDT 24 Jul 12 05:58:09 PM PDT 24 66610055285 ps
T795 /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.385423893 Jul 12 05:56:41 PM PDT 24 Jul 12 05:57:14 PM PDT 24 6414821053 ps
T796 /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3058866538 Jul 12 05:56:43 PM PDT 24 Jul 12 05:57:50 PM PDT 24 17240304833 ps
T129 /workspace/coverage/xbar_build_mode/38.xbar_stress_all.468091143 Jul 12 05:57:30 PM PDT 24 Jul 12 06:03:16 PM PDT 24 16624348263 ps
T797 /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3359578499 Jul 12 05:57:36 PM PDT 24 Jul 12 05:59:56 PM PDT 24 1077578553 ps
T798 /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.567035469 Jul 12 05:56:52 PM PDT 24 Jul 12 05:57:27 PM PDT 24 7636969278 ps
T799 /workspace/coverage/xbar_build_mode/24.xbar_random.2590490051 Jul 12 05:56:27 PM PDT 24 Jul 12 05:56:58 PM PDT 24 335347360 ps
T800 /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3880201859 Jul 12 05:55:58 PM PDT 24 Jul 12 05:57:37 PM PDT 24 13856303504 ps
T801 /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.132365622 Jul 12 05:56:23 PM PDT 24 Jul 12 06:06:01 PM PDT 24 77757406653 ps
T802 /workspace/coverage/xbar_build_mode/28.xbar_same_source.2148318962 Jul 12 05:56:41 PM PDT 24 Jul 12 05:57:19 PM PDT 24 1540663900 ps
T120 /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.885264766 Jul 12 05:56:56 PM PDT 24 Jul 12 05:57:56 PM PDT 24 8430121960 ps
T803 /workspace/coverage/xbar_build_mode/32.xbar_smoke.3934377162 Jul 12 05:56:58 PM PDT 24 Jul 12 05:57:03 PM PDT 24 372946552 ps
T804 /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2523595139 Jul 12 05:55:31 PM PDT 24 Jul 12 05:56:06 PM PDT 24 4188910936 ps
T805 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2606295356 Jul 12 06:16:34 PM PDT 24 Jul 12 06:19:35 PM PDT 24 54974494170 ps
T806 /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1651364075 Jul 12 05:57:35 PM PDT 24 Jul 12 05:59:50 PM PDT 24 9385932481 ps
T807 /workspace/coverage/xbar_build_mode/41.xbar_same_source.3746254184 Jul 12 05:57:41 PM PDT 24 Jul 12 05:58:22 PM PDT 24 2211063464 ps
T808 /workspace/coverage/xbar_build_mode/20.xbar_same_source.4010086807 Jul 12 05:56:16 PM PDT 24 Jul 12 05:56:46 PM PDT 24 7365836440 ps
T809 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2064273476 Jul 12 05:55:20 PM PDT 24 Jul 12 05:55:41 PM PDT 24 319123493 ps
T810 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.842055756 Jul 12 05:55:32 PM PDT 24 Jul 12 05:55:43 PM PDT 24 121493727 ps
T811 /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.170700486 Jul 12 05:57:29 PM PDT 24 Jul 12 05:58:23 PM PDT 24 4451611399 ps
T812 /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1126872770 Jul 12 05:55:19 PM PDT 24 Jul 12 05:55:23 PM PDT 24 27576516 ps
T813 /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.449725855 Jul 12 05:55:17 PM PDT 24 Jul 12 05:55:21 PM PDT 24 68665115 ps
T814 /workspace/coverage/xbar_build_mode/14.xbar_smoke.2591661180 Jul 12 05:55:42 PM PDT 24 Jul 12 05:55:48 PM PDT 24 109756080 ps
T815 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2356937940 Jul 12 05:57:37 PM PDT 24 Jul 12 05:58:27 PM PDT 24 2287472674 ps
T816 /workspace/coverage/xbar_build_mode/2.xbar_error_random.1305716389 Jul 12 05:55:14 PM PDT 24 Jul 12 05:55:23 PM PDT 24 250936286 ps
T817 /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.437224049 Jul 12 05:55:43 PM PDT 24 Jul 12 05:55:47 PM PDT 24 26949108 ps
T818 /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1033847449 Jul 12 05:55:32 PM PDT 24 Jul 12 05:57:04 PM PDT 24 5409105862 ps
T254 /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2506547749 Jul 12 05:56:28 PM PDT 24 Jul 12 05:56:58 PM PDT 24 9746888051 ps
T819 /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.242357001 Jul 12 05:57:10 PM PDT 24 Jul 12 05:57:13 PM PDT 24 29154221 ps
T820 /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2465028780 Jul 12 05:57:19 PM PDT 24 Jul 12 05:59:01 PM PDT 24 559642315 ps
T821 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1563289306 Jul 12 05:57:13 PM PDT 24 Jul 12 06:09:50 PM PDT 24 281006853731 ps
T822 /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1512125324 Jul 12 05:57:21 PM PDT 24 Jul 12 06:01:01 PM PDT 24 94235862679 ps
T823 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2055273914 Jul 12 05:55:19 PM PDT 24 Jul 12 05:55:24 PM PDT 24 110330437 ps
T824 /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.202446148 Jul 12 05:56:56 PM PDT 24 Jul 12 05:57:01 PM PDT 24 67838408 ps
T825 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.572800578 Jul 12 05:56:34 PM PDT 24 Jul 12 06:01:28 PM PDT 24 34324192807 ps
T826 /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3495617788 Jul 12 05:55:16 PM PDT 24 Jul 12 05:58:16 PM PDT 24 83311149406 ps
T827 /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2522185287 Jul 12 05:57:57 PM PDT 24 Jul 12 05:58:11 PM PDT 24 48882321 ps
T828 /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3638933880 Jul 12 05:55:31 PM PDT 24 Jul 12 05:58:57 PM PDT 24 2961484265 ps
T829 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1196725477 Jul 12 05:56:35 PM PDT 24 Jul 12 05:57:07 PM PDT 24 1808551678 ps
T830 /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3170314359 Jul 12 05:55:19 PM PDT 24 Jul 12 05:55:30 PM PDT 24 65402431 ps
T831 /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3842435186 Jul 12 05:55:32 PM PDT 24 Jul 12 05:55:51 PM PDT 24 1199031511 ps
T832 /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.4249810229 Jul 12 05:56:54 PM PDT 24 Jul 12 05:56:58 PM PDT 24 21488511 ps
T833 /workspace/coverage/xbar_build_mode/3.xbar_error_random.1097695103 Jul 12 05:55:23 PM PDT 24 Jul 12 05:55:36 PM PDT 24 169521967 ps
T834 /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2718459415 Jul 12 05:56:26 PM PDT 24 Jul 12 05:59:17 PM PDT 24 1962345204 ps
T835 /workspace/coverage/xbar_build_mode/14.xbar_error_random.856592084 Jul 12 05:55:41 PM PDT 24 Jul 12 05:56:15 PM PDT 24 2677166033 ps
T836 /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.853212950 Jul 12 05:57:39 PM PDT 24 Jul 12 05:58:10 PM PDT 24 194133752 ps
T837 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1863547409 Jul 12 05:56:53 PM PDT 24 Jul 12 05:57:49 PM PDT 24 1438167969 ps
T838 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1262337634 Jul 12 05:58:15 PM PDT 24 Jul 12 05:59:43 PM PDT 24 89635547 ps
T839 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3033029561 Jul 12 05:55:59 PM PDT 24 Jul 12 05:56:33 PM PDT 24 351530001 ps
T840 /workspace/coverage/xbar_build_mode/12.xbar_same_source.2486586765 Jul 12 05:55:40 PM PDT 24 Jul 12 05:56:01 PM PDT 24 1749344760 ps
T841 /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2804151025 Jul 12 05:55:27 PM PDT 24 Jul 12 05:56:06 PM PDT 24 14353918493 ps
T842 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3623759137 Jul 12 05:57:31 PM PDT 24 Jul 12 05:57:47 PM PDT 24 45354327 ps
T843 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1359757485 Jul 12 05:56:37 PM PDT 24 Jul 12 05:56:52 PM PDT 24 42964929 ps
T844 /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3893501285 Jul 12 05:55:15 PM PDT 24 Jul 12 05:55:33 PM PDT 24 536174772 ps
T845 /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2471082088 Jul 12 05:55:20 PM PDT 24 Jul 12 05:56:33 PM PDT 24 2075069842 ps
T846 /workspace/coverage/xbar_build_mode/32.xbar_error_random.640630881 Jul 12 05:57:07 PM PDT 24 Jul 12 05:57:16 PM PDT 24 185430732 ps
T847 /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4084266642 Jul 12 05:55:13 PM PDT 24 Jul 12 05:55:32 PM PDT 24 3856525138 ps
T848 /workspace/coverage/xbar_build_mode/22.xbar_same_source.1146069039 Jul 12 05:56:21 PM PDT 24 Jul 12 05:56:28 PM PDT 24 257747108 ps
T849 /workspace/coverage/xbar_build_mode/12.xbar_random.710667051 Jul 12 05:55:39 PM PDT 24 Jul 12 05:56:01 PM PDT 24 684371778 ps
T850 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.949501247 Jul 12 05:55:36 PM PDT 24 Jul 12 05:56:34 PM PDT 24 232253594 ps
T851 /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3494306220 Jul 12 05:56:52 PM PDT 24 Jul 12 05:56:56 PM PDT 24 33030405 ps
T852 /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1477957536 Jul 12 05:55:14 PM PDT 24 Jul 12 05:55:44 PM PDT 24 4531152857 ps
T853 /workspace/coverage/xbar_build_mode/7.xbar_smoke.18805668 Jul 12 05:55:26 PM PDT 24 Jul 12 05:55:31 PM PDT 24 204537808 ps
T854 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3232722581 Jul 12 05:58:16 PM PDT 24 Jul 12 06:01:06 PM PDT 24 4183755868 ps
T855 /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3678746615 Jul 12 05:57:24 PM PDT 24 Jul 12 05:57:39 PM PDT 24 85397856 ps
T856 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2428698513 Jul 12 05:57:09 PM PDT 24 Jul 12 05:57:43 PM PDT 24 1050490251 ps
T857 /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.535087688 Jul 12 05:55:42 PM PDT 24 Jul 12 05:56:25 PM PDT 24 17097631709 ps
T121 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1642303508 Jul 12 05:55:14 PM PDT 24 Jul 12 06:03:38 PM PDT 24 8080247762 ps
T858 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2363257097 Jul 12 05:57:40 PM PDT 24 Jul 12 05:58:18 PM PDT 24 10340874741 ps
T859 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4293100392 Jul 12 05:57:51 PM PDT 24 Jul 12 06:09:30 PM PDT 24 83323879991 ps
T860 /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.207756332 Jul 12 05:55:29 PM PDT 24 Jul 12 05:55:35 PM PDT 24 35101075 ps
T861 /workspace/coverage/xbar_build_mode/44.xbar_stress_all.976482722 Jul 12 05:57:57 PM PDT 24 Jul 12 05:59:25 PM PDT 24 3550063434 ps
T862 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1802962561 Jul 12 05:57:49 PM PDT 24 Jul 12 05:58:33 PM PDT 24 4645649631 ps
T863 /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.367186585 Jul 12 05:57:26 PM PDT 24 Jul 12 05:58:02 PM PDT 24 3346824334 ps
T864 /workspace/coverage/xbar_build_mode/17.xbar_error_random.3299306963 Jul 12 05:56:03 PM PDT 24 Jul 12 05:56:19 PM PDT 24 1405188053 ps
T865 /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2480886940 Jul 12 05:55:15 PM PDT 24 Jul 12 05:56:45 PM PDT 24 2087877184 ps
T866 /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2051333751 Jul 12 05:56:35 PM PDT 24 Jul 12 06:02:21 PM PDT 24 13683842306 ps
T867 /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.38204165 Jul 12 05:57:37 PM PDT 24 Jul 12 05:57:59 PM PDT 24 54018123 ps
T868 /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.261269837 Jul 12 05:57:41 PM PDT 24 Jul 12 05:58:12 PM PDT 24 267513510 ps
T869 /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1592329929 Jul 12 05:58:11 PM PDT 24 Jul 12 06:01:45 PM PDT 24 27828203873 ps
T870 /workspace/coverage/xbar_build_mode/15.xbar_random.2909517048 Jul 12 05:55:42 PM PDT 24 Jul 12 05:56:11 PM PDT 24 1100248602 ps
T871 /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2411663824 Jul 12 05:55:27 PM PDT 24 Jul 12 05:55:30 PM PDT 24 30532310 ps
T872 /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1597587114 Jul 12 05:57:13 PM PDT 24 Jul 12 05:57:52 PM PDT 24 14402190596 ps
T873 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1766414825 Jul 12 05:55:13 PM PDT 24 Jul 12 05:56:32 PM PDT 24 880002367 ps
T874 /workspace/coverage/xbar_build_mode/24.xbar_smoke.1481756476 Jul 12 05:56:27 PM PDT 24 Jul 12 05:56:33 PM PDT 24 177608813 ps
T875 /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2298371441 Jul 12 05:56:41 PM PDT 24 Jul 12 05:56:50 PM PDT 24 52940432 ps
T122 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.25450758 Jul 12 05:57:45 PM PDT 24 Jul 12 06:06:44 PM PDT 24 155471173318 ps
T876 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3326331645 Jul 12 05:56:57 PM PDT 24 Jul 12 06:00:05 PM PDT 24 380524997 ps
T877 /workspace/coverage/xbar_build_mode/18.xbar_smoke.656413286 Jul 12 05:56:08 PM PDT 24 Jul 12 05:56:10 PM PDT 24 32050006 ps
T878 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1685762631 Jul 12 05:57:19 PM PDT 24 Jul 12 05:57:56 PM PDT 24 4183761869 ps
T879 /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2500223454 Jul 12 05:57:52 PM PDT 24 Jul 12 06:00:41 PM PDT 24 36336548842 ps
T880 /workspace/coverage/xbar_build_mode/45.xbar_smoke.318977519 Jul 12 05:57:54 PM PDT 24 Jul 12 05:58:08 PM PDT 24 219402970 ps
T881 /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3567208660 Jul 12 05:56:33 PM PDT 24 Jul 12 05:57:01 PM PDT 24 4201738096 ps
T882 /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3609412888 Jul 12 05:57:04 PM PDT 24 Jul 12 05:57:34 PM PDT 24 4828294721 ps
T883 /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1147536337 Jul 12 05:55:30 PM PDT 24 Jul 12 05:55:34 PM PDT 24 26307095 ps
T884 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3329681145 Jul 12 05:58:14 PM PDT 24 Jul 12 06:03:32 PM PDT 24 11161013505 ps
T885 /workspace/coverage/xbar_build_mode/47.xbar_random.1051882058 Jul 12 05:58:05 PM PDT 24 Jul 12 05:58:48 PM PDT 24 666429213 ps
T886 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1961502259 Jul 12 05:58:16 PM PDT 24 Jul 12 05:59:17 PM PDT 24 7440709791 ps
T887 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3044074735 Jul 12 05:57:38 PM PDT 24 Jul 12 06:00:09 PM PDT 24 409530716 ps
T888 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2575689551 Jul 12 05:55:18 PM PDT 24 Jul 12 05:56:08 PM PDT 24 134610180 ps
T889 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3684223627 Jul 12 05:57:08 PM PDT 24 Jul 12 05:57:49 PM PDT 24 178009900 ps
T890 /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2365965400 Jul 12 05:55:33 PM PDT 24 Jul 12 05:55:57 PM PDT 24 520219343 ps
T891 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1017693996 Jul 12 05:56:08 PM PDT 24 Jul 12 05:56:36 PM PDT 24 86007565 ps
T892 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4268666246 Jul 12 05:58:24 PM PDT 24 Jul 12 05:59:54 PM PDT 24 3687467565 ps
T893 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1302483158 Jul 12 05:55:17 PM PDT 24 Jul 12 05:57:18 PM PDT 24 2048234303 ps
T894 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3337483415 Jul 12 05:57:23 PM PDT 24 Jul 12 05:59:11 PM PDT 24 34232714085 ps
T895 /workspace/coverage/xbar_build_mode/4.xbar_smoke.3161436259 Jul 12 05:59:57 PM PDT 24 Jul 12 06:00:04 PM PDT 24 847350027 ps
T130 /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1571571087 Jul 12 05:56:36 PM PDT 24 Jul 12 05:57:03 PM PDT 24 6667098964 ps
T896 /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3121866051 Jul 12 05:56:33 PM PDT 24 Jul 12 05:56:58 PM PDT 24 6030632168 ps
T897 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.377627486 Jul 12 05:58:01 PM PDT 24 Jul 12 06:07:03 PM PDT 24 129232626480 ps
T898 /workspace/coverage/xbar_build_mode/11.xbar_error_random.308238709 Jul 12 05:55:37 PM PDT 24 Jul 12 05:55:50 PM PDT 24 318780517 ps
T899 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2447856604 Jul 12 05:58:05 PM PDT 24 Jul 12 05:58:57 PM PDT 24 3517347916 ps
T900 /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3729143338 Jul 12 05:56:02 PM PDT 24 Jul 12 05:56:26 PM PDT 24 167694964 ps

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1429397321
Short name T1
Test name
Test status
Simulation time 28623258828 ps
CPU time 255.96 seconds
Started Jul 12 05:57:12 PM PDT 24
Finished Jul 12 06:01:29 PM PDT 24
Peak memory 210456 kb
Host smart-2266fbf2-dbe5-4cde-b31f-e678066dee1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1429397321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1429397321
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.593969916
Short name T88
Test name
Test status
Simulation time 51348017811 ps
CPU time 501.23 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 06:04:07 PM PDT 24
Peak memory 211816 kb
Host smart-58297ddd-b045-4a79-881c-2a29bc0f9fb9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=593969916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo
w_rsp.593969916
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3563372421
Short name T13
Test name
Test status
Simulation time 220081775047 ps
CPU time 499.81 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 06:03:54 PM PDT 24
Peak memory 211688 kb
Host smart-92d760ca-2b46-4526-947d-6dcf800c28d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3563372421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.3563372421
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4210520043
Short name T4
Test name
Test status
Simulation time 1610626477 ps
CPU time 267.48 seconds
Started Jul 12 05:55:44 PM PDT 24
Finished Jul 12 06:00:13 PM PDT 24
Peak memory 219908 kb
Host smart-fe2d02e0-9cab-49a6-8958-5e663cd38dc9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4210520043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.4210520043
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1027463193
Short name T90
Test name
Test status
Simulation time 38690733461 ps
CPU time 364.41 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 06:03:13 PM PDT 24
Peak memory 206880 kb
Host smart-b2672934-ba7c-419c-bbef-3eeb0bc4be00
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1027463193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.1027463193
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2253109953
Short name T200
Test name
Test status
Simulation time 71829161814 ps
CPU time 479.59 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 06:03:39 PM PDT 24
Peak memory 211680 kb
Host smart-1c43011b-064e-4b28-aecb-2ece4402cbc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2253109953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.2253109953
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2104122815
Short name T27
Test name
Test status
Simulation time 13960191157 ps
CPU time 584.81 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 06:05:45 PM PDT 24
Peak memory 219996 kb
Host smart-abf0010e-beae-41d9-9a4e-13fd61e22cc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2104122815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.2104122815
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.424698243
Short name T20
Test name
Test status
Simulation time 235665890 ps
CPU time 123.05 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 05:59:47 PM PDT 24
Peak memory 208504 kb
Host smart-7cb8c9da-9dcb-4bbe-8683-1d5c1f694ccf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=424698243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand
_reset.424698243
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3371684694
Short name T156
Test name
Test status
Simulation time 15107770529 ps
CPU time 31.82 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:54 PM PDT 24
Peak memory 203532 kb
Host smart-3061bcff-267b-4214-95b2-7571188f16a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371684694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3371684694
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3827408491
Short name T164
Test name
Test status
Simulation time 26664677938 ps
CPU time 91.45 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:56:59 PM PDT 24
Peak memory 211716 kb
Host smart-c700b021-8e0e-4401-be2f-cc76cdbcd13c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3827408491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.3827408491
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1173436356
Short name T78
Test name
Test status
Simulation time 4718171915 ps
CPU time 238.95 seconds
Started Jul 12 05:55:39 PM PDT 24
Finished Jul 12 05:59:39 PM PDT 24
Peak memory 208520 kb
Host smart-ca01a221-4713-40c9-9d7a-688056a24324
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1173436356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.1173436356
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2334511826
Short name T25
Test name
Test status
Simulation time 17166612004 ps
CPU time 582.26 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 06:05:18 PM PDT 24
Peak memory 220276 kb
Host smart-6343b3eb-aabb-41c4-b023-b054438e7732
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2334511826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.2334511826
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2904156772
Short name T113
Test name
Test status
Simulation time 79143708394 ps
CPU time 640.43 seconds
Started Jul 12 05:56:45 PM PDT 24
Finished Jul 12 06:07:26 PM PDT 24
Peak memory 211644 kb
Host smart-ace57517-b94e-4208-b47f-db626162160f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2904156772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2904156772
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1447043411
Short name T260
Test name
Test status
Simulation time 5562208485 ps
CPU time 357.89 seconds
Started Jul 12 05:57:45 PM PDT 24
Finished Jul 12 06:03:54 PM PDT 24
Peak memory 219980 kb
Host smart-d490cdc0-76e3-40b8-a265-da47fb6cf0d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1447043411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.1447043411
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.986671317
Short name T108
Test name
Test status
Simulation time 3831151015 ps
CPU time 177.28 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:58:28 PM PDT 24
Peak memory 208328 kb
Host smart-a66429b8-45df-4a70-acbb-1d11227f56eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=986671317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_
reset.986671317
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2623118819
Short name T123
Test name
Test status
Simulation time 39701753551 ps
CPU time 347.2 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 06:01:32 PM PDT 24
Peak memory 211744 kb
Host smart-189a4111-1fcf-437a-b04b-115840a26a7a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2623118819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2623118819
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2608923740
Short name T494
Test name
Test status
Simulation time 470513032 ps
CPU time 151.2 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:57:53 PM PDT 24
Peak memory 211016 kb
Host smart-19f2fc74-0119-49a4-9a71-6fadb67ff046
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2608923740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.2608923740
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3523759488
Short name T31
Test name
Test status
Simulation time 140950407 ps
CPU time 50.03 seconds
Started Jul 12 05:55:39 PM PDT 24
Finished Jul 12 05:56:30 PM PDT 24
Peak memory 206360 kb
Host smart-25677a22-a7d1-471c-9d66-541bf6411c5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3523759488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3523759488
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.828425838
Short name T29
Test name
Test status
Simulation time 6277571910 ps
CPU time 326.71 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 06:01:42 PM PDT 24
Peak memory 219896 kb
Host smart-6e65b47b-e253-4693-8060-8168c8f032d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=828425838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res
et_error.828425838
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1426510292
Short name T30
Test name
Test status
Simulation time 413390767 ps
CPU time 168.64 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 209120 kb
Host smart-9c0eface-cff7-4a5f-b5b4-d03a4767954b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1426510292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.1426510292
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3227499010
Short name T28
Test name
Test status
Simulation time 373969803 ps
CPU time 124.87 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 210124 kb
Host smart-aecf3657-8c9c-4c63-b883-c4835ff42bda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3227499010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.3227499010
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3067009604
Short name T140
Test name
Test status
Simulation time 5059297283 ps
CPU time 113.14 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 208400 kb
Host smart-f26d2eb9-6a81-448f-a836-a32cc479a14c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3067009604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.3067009604
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1480968977
Short name T107
Test name
Test status
Simulation time 97652333553 ps
CPU time 686.01 seconds
Started Jul 12 05:55:12 PM PDT 24
Finished Jul 12 06:06:39 PM PDT 24
Peak memory 206172 kb
Host smart-c2e9791d-c277-4f44-8674-85f71d8f35a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1480968977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1480968977
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.998619926
Short name T474
Test name
Test status
Simulation time 572196500 ps
CPU time 26.8 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:45 PM PDT 24
Peak memory 211676 kb
Host smart-9ceba407-6a2d-4565-8d43-7fe542a690e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998619926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.998619926
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4001713968
Short name T484
Test name
Test status
Simulation time 85309242401 ps
CPU time 469.01 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 06:03:11 PM PDT 24
Peak memory 211712 kb
Host smart-c6639c2f-e459-4cf3-a1a9-daf2bb529f9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4001713968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.4001713968
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.551374745
Short name T361
Test name
Test status
Simulation time 46001993 ps
CPU time 2.37 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:16 PM PDT 24
Peak memory 203500 kb
Host smart-5661d1e5-12bb-4a0d-9096-dc92d3b78a6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551374745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.551374745
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.1114427966
Short name T351
Test name
Test status
Simulation time 542712693 ps
CPU time 16.43 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 203520 kb
Host smart-7f695a70-2fb5-4f0e-8a87-eb9eb6aa84db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1114427966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1114427966
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.1930086246
Short name T706
Test name
Test status
Simulation time 758935019 ps
CPU time 22.03 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:55:38 PM PDT 24
Peak memory 211656 kb
Host smart-4128051d-3f4e-4cc5-bc65-acef46038326
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1930086246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1930086246
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.831522165
Short name T535
Test name
Test status
Simulation time 10627193712 ps
CPU time 61.6 seconds
Started Jul 12 05:55:12 PM PDT 24
Finished Jul 12 05:56:14 PM PDT 24
Peak memory 204748 kb
Host smart-628361ae-a723-41c0-952e-01d5a8dbdda1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=831522165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.831522165
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.859971018
Short name T673
Test name
Test status
Simulation time 9133198067 ps
CPU time 41 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 211704 kb
Host smart-291eed18-9474-46de-8b1d-cd0b94ef06ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=859971018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.859971018
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2153978612
Short name T725
Test name
Test status
Simulation time 525103332 ps
CPU time 27.25 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 211504 kb
Host smart-1608d720-4530-4670-8b52-1b345e20b9d8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153978612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2153978612
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.119375945
Short name T362
Test name
Test status
Simulation time 81287597 ps
CPU time 6.6 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:25 PM PDT 24
Peak memory 203536 kb
Host smart-73f9b19c-6636-4c7a-95bb-71453cb7ae17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=119375945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.119375945
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2456232226
Short name T2
Test name
Test status
Simulation time 395504644 ps
CPU time 3.52 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 203468 kb
Host smart-b08d8fd7-7fe7-4fcf-8c6e-190ac2fe71fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2456232226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2456232226
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2201380877
Short name T647
Test name
Test status
Simulation time 19558741935 ps
CPU time 36.98 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:39 PM PDT 24
Peak memory 203444 kb
Host smart-1b00abf8-0d63-4fcc-9388-7516686a60d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201380877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2201380877
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.810711226
Short name T54
Test name
Test status
Simulation time 5434559774 ps
CPU time 26.07 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:28 PM PDT 24
Peak memory 203516 kb
Host smart-cfd1dd6d-467f-46ca-8e34-2c422d9f45a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=810711226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.810711226
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1982551330
Short name T394
Test name
Test status
Simulation time 46204951 ps
CPU time 2.56 seconds
Started Jul 12 05:55:00 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 203480 kb
Host smart-d4df6c9d-422a-4eac-ba2a-35c00ed84da3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982551330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1982551330
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2480886940
Short name T865
Test name
Test status
Simulation time 2087877184 ps
CPU time 87.95 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:56:45 PM PDT 24
Peak memory 206624 kb
Host smart-8bc30aa8-f3f5-4592-8847-887de75713a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2480886940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2480886940
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3884634371
Short name T340
Test name
Test status
Simulation time 792238930 ps
CPU time 82.67 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:56:40 PM PDT 24
Peak memory 207372 kb
Host smart-134dadff-dc9c-42ba-97c8-5eccaafbfa33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3884634371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3884634371
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2360059399
Short name T660
Test name
Test status
Simulation time 284400534 ps
CPU time 84.93 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 209356 kb
Host smart-24adc27b-67d7-432f-ae22-64b0cf1a48c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2360059399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.2360059399
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2484224405
Short name T734
Test name
Test status
Simulation time 120657556 ps
CPU time 15.21 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 211632 kb
Host smart-90a8d474-6e80-4c01-b8f8-8b72f644dcb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2484224405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2484224405
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1281278172
Short name T695
Test name
Test status
Simulation time 123391259 ps
CPU time 17.81 seconds
Started Jul 12 05:55:12 PM PDT 24
Finished Jul 12 05:55:31 PM PDT 24
Peak memory 204540 kb
Host smart-c664cc4a-2e75-474e-8c58-1605590004a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1281278172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1281278172
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.964699040
Short name T386
Test name
Test status
Simulation time 80792765 ps
CPU time 9.04 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:27 PM PDT 24
Peak memory 203528 kb
Host smart-ead28aea-64a5-47f8-8d0b-ba7f744ef17e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964699040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.964699040
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.387094453
Short name T526
Test name
Test status
Simulation time 461064453 ps
CPU time 12.16 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:25 PM PDT 24
Peak memory 203452 kb
Host smart-c320ea9f-522c-4cf3-8d90-ea03be13eafc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=387094453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.387094453
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.4028519362
Short name T384
Test name
Test status
Simulation time 654255458 ps
CPU time 7.95 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:27 PM PDT 24
Peak memory 211644 kb
Host smart-b73db9fc-cb25-4b54-b070-2f9661cdf461
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4028519362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.4028519362
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3495617788
Short name T826
Test name
Test status
Simulation time 83311149406 ps
CPU time 177.05 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 205368 kb
Host smart-ff094ee9-eca3-4c52-98d4-9336dd6b1f76
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495617788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3495617788
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1714300010
Short name T664
Test name
Test status
Simulation time 84691916647 ps
CPU time 179.46 seconds
Started Jul 12 05:55:12 PM PDT 24
Finished Jul 12 05:58:12 PM PDT 24
Peak memory 204980 kb
Host smart-549342c2-31ef-4765-9a64-dc89446218fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1714300010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1714300010
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1645709585
Short name T541
Test name
Test status
Simulation time 738589293 ps
CPU time 24.51 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:38 PM PDT 24
Peak memory 204540 kb
Host smart-f406cf9a-19e3-4f09-979f-5542813dd8d0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645709585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1645709585
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.160713195
Short name T589
Test name
Test status
Simulation time 1388719358 ps
CPU time 21.45 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:55:38 PM PDT 24
Peak memory 203488 kb
Host smart-81fb0e29-5136-47f9-b1c1-844153f4e767
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=160713195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.160713195
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.3231979303
Short name T742
Test name
Test status
Simulation time 28236605 ps
CPU time 2.39 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:22 PM PDT 24
Peak memory 203448 kb
Host smart-ebfb5771-cea3-40aa-9ed4-96cc97835a4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3231979303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3231979303
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2036769098
Short name T755
Test name
Test status
Simulation time 7009881618 ps
CPU time 29.05 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 203484 kb
Host smart-546da4b8-c50b-4b4c-9f45-69fc4cf30799
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036769098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2036769098
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.4169418388
Short name T347
Test name
Test status
Simulation time 2392295273 ps
CPU time 22.49 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:55:40 PM PDT 24
Peak memory 203548 kb
Host smart-184dbc11-54b1-443f-992e-d3a087e31fe6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4169418388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.4169418388
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1953417490
Short name T671
Test name
Test status
Simulation time 28745627 ps
CPU time 2.15 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 203452 kb
Host smart-2b369ae9-7b1e-4dc7-bc13-539558741790
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953417490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1953417490
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2037754991
Short name T727
Test name
Test status
Simulation time 2390993485 ps
CPU time 51.79 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:56:07 PM PDT 24
Peak memory 206912 kb
Host smart-4cec701c-b5f1-4983-82fc-c86a34db49cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2037754991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2037754991
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.791412633
Short name T627
Test name
Test status
Simulation time 6422621274 ps
CPU time 120.72 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:57:19 PM PDT 24
Peak memory 206476 kb
Host smart-9fda9efa-3132-40f8-a632-cf6f405f0efb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=791412633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.791412633
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.952585686
Short name T524
Test name
Test status
Simulation time 1427744760 ps
CPU time 97.04 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:56:57 PM PDT 24
Peak memory 207732 kb
Host smart-773a7c6e-fe98-4f9d-bc0a-009c399ef1bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952585686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_
reset.952585686
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3170314359
Short name T830
Test name
Test status
Simulation time 65402431 ps
CPU time 8.37 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:55:30 PM PDT 24
Peak memory 211636 kb
Host smart-3cca1bf0-614c-465c-b46f-40517752db1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3170314359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3170314359
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1795387512
Short name T406
Test name
Test status
Simulation time 71715260 ps
CPU time 8.89 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:55:45 PM PDT 24
Peak memory 211596 kb
Host smart-20b4c290-5402-4d41-bd37-f3c31b6b16f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1795387512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1795387512
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2288416589
Short name T763
Test name
Test status
Simulation time 101249965191 ps
CPU time 521.28 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 06:04:16 PM PDT 24
Peak memory 211716 kb
Host smart-6a7f5e2f-a940-4313-9349-1e08b07b3fa3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2288416589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.2288416589
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3842435186
Short name T831
Test name
Test status
Simulation time 1199031511 ps
CPU time 15.97 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:55:51 PM PDT 24
Peak memory 203488 kb
Host smart-f5090e93-396e-4776-90bc-d6bedad95b8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3842435186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3842435186
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.1394349524
Short name T722
Test name
Test status
Simulation time 821726053 ps
CPU time 17.28 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:55:54 PM PDT 24
Peak memory 203468 kb
Host smart-479baa45-29dc-4065-aa5f-9bfc58b7a78d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394349524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1394349524
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.457398917
Short name T613
Test name
Test status
Simulation time 243999770 ps
CPU time 22.54 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:55:57 PM PDT 24
Peak memory 211664 kb
Host smart-08b474d7-26a3-449b-a53f-cd9751a5ee0e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457398917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.457398917
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1337244202
Short name T92
Test name
Test status
Simulation time 52230388883 ps
CPU time 218.44 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:59:13 PM PDT 24
Peak memory 211600 kb
Host smart-746bcb97-a2b3-4134-807e-8f65e642e6a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337244202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1337244202
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.594918868
Short name T51
Test name
Test status
Simulation time 29442797856 ps
CPU time 162.46 seconds
Started Jul 12 05:55:40 PM PDT 24
Finished Jul 12 05:58:24 PM PDT 24
Peak memory 205052 kb
Host smart-7ddbc647-946d-460f-a05c-871de806457c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=594918868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.594918868
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2365965400
Short name T890
Test name
Test status
Simulation time 520219343 ps
CPU time 20.72 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:55:57 PM PDT 24
Peak memory 211676 kb
Host smart-5ce6738f-1e31-4cd8-8cf6-42c8cf55e691
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365965400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2365965400
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2891072765
Short name T350
Test name
Test status
Simulation time 88947931 ps
CPU time 2.72 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:55:36 PM PDT 24
Peak memory 203472 kb
Host smart-2e74ed44-0dbe-4d69-8231-fd19fa9ecc11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2891072765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2891072765
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.3381867302
Short name T205
Test name
Test status
Simulation time 351170202 ps
CPU time 3.28 seconds
Started Jul 12 05:55:30 PM PDT 24
Finished Jul 12 05:55:35 PM PDT 24
Peak memory 203476 kb
Host smart-82fc7851-feaa-42df-b0be-1eefc912964f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3381867302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3381867302
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3579215501
Short name T167
Test name
Test status
Simulation time 11578642952 ps
CPU time 34.26 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:56:10 PM PDT 24
Peak memory 203520 kb
Host smart-f31406df-27ee-4963-8e1f-9632215f834f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579215501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3579215501
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3251189144
Short name T48
Test name
Test status
Simulation time 2550035147 ps
CPU time 21.97 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 203544 kb
Host smart-040ad3a3-5122-4d6b-9cc4-14b44a8884a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3251189144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3251189144
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.890475933
Short name T321
Test name
Test status
Simulation time 37009467 ps
CPU time 2.35 seconds
Started Jul 12 05:55:30 PM PDT 24
Finished Jul 12 05:55:35 PM PDT 24
Peak memory 203472 kb
Host smart-cfdc8fd0-ab6d-4981-83a8-243d318d9979
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890475933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.890475933
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1033847449
Short name T818
Test name
Test status
Simulation time 5409105862 ps
CPU time 88.82 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:57:04 PM PDT 24
Peak memory 206528 kb
Host smart-08736641-e442-4f85-889d-37571ce25a88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1033847449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1033847449
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3288276657
Short name T100
Test name
Test status
Simulation time 5794149 ps
CPU time 0.75 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:55:37 PM PDT 24
Peak memory 195220 kb
Host smart-40b7bfb9-f4cd-42b3-b913-f7c674e9cb17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3288276657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3288276657
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3298758509
Short name T302
Test name
Test status
Simulation time 138531476 ps
CPU time 68.97 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 208596 kb
Host smart-df7ac11d-081a-484e-9164-b683a395c249
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3298758509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.3298758509
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.517085663
Short name T274
Test name
Test status
Simulation time 222610147 ps
CPU time 15.23 seconds
Started Jul 12 05:55:30 PM PDT 24
Finished Jul 12 05:55:47 PM PDT 24
Peak memory 205040 kb
Host smart-5506c989-c381-4e15-b789-8c0300c2406b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=517085663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.517085663
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1536411826
Short name T112
Test name
Test status
Simulation time 2033396564 ps
CPU time 36.39 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 204760 kb
Host smart-3ed59e13-6652-4e32-bcb0-71ae0442ef47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1536411826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1536411826
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3882177358
Short name T109
Test name
Test status
Simulation time 161689604131 ps
CPU time 618.11 seconds
Started Jul 12 05:55:40 PM PDT 24
Finished Jul 12 06:05:59 PM PDT 24
Peak memory 207608 kb
Host smart-fead1299-8e39-40ec-aa5b-260f326bfffa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3882177358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.3882177358
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3178595546
Short name T677
Test name
Test status
Simulation time 22020725 ps
CPU time 2.87 seconds
Started Jul 12 05:55:40 PM PDT 24
Finished Jul 12 05:55:44 PM PDT 24
Peak memory 203440 kb
Host smart-3d054cd8-a779-453a-b5fe-0530b2991782
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3178595546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3178595546
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.308238709
Short name T898
Test name
Test status
Simulation time 318780517 ps
CPU time 11.31 seconds
Started Jul 12 05:55:37 PM PDT 24
Finished Jul 12 05:55:50 PM PDT 24
Peak memory 203524 kb
Host smart-c3c72d89-26f3-4b71-8c6b-57b0adef78e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=308238709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.308238709
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1422493140
Short name T358
Test name
Test status
Simulation time 190486486 ps
CPU time 6.06 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:55:42 PM PDT 24
Peak memory 203556 kb
Host smart-0e3c8cef-c7f3-410f-9389-2d06b41dd94d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1422493140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1422493140
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2548486417
Short name T46
Test name
Test status
Simulation time 15383027029 ps
CPU time 64.34 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 204788 kb
Host smart-57edda21-18f5-4eba-aab8-a9e76a3d3628
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548486417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2548486417
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.2443110492
Short name T219
Test name
Test status
Simulation time 38432395752 ps
CPU time 196.82 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:58:53 PM PDT 24
Peak memory 211700 kb
Host smart-be5e60ce-2200-4804-a4a2-7f66322d7657
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2443110492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2443110492
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4245552613
Short name T568
Test name
Test status
Simulation time 366494278 ps
CPU time 18.22 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:55:55 PM PDT 24
Peak memory 211628 kb
Host smart-a4de0830-e8f0-492f-b74d-bda2107fbb0b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245552613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4245552613
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.2342901996
Short name T426
Test name
Test status
Simulation time 697547300 ps
CPU time 20.17 seconds
Started Jul 12 05:55:44 PM PDT 24
Finished Jul 12 05:56:06 PM PDT 24
Peak memory 203600 kb
Host smart-ddfca499-2489-4e36-887d-3aeacb9296b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2342901996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2342901996
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.1086854623
Short name T782
Test name
Test status
Simulation time 208891362 ps
CPU time 3.69 seconds
Started Jul 12 05:55:35 PM PDT 24
Finished Jul 12 05:55:41 PM PDT 24
Peak memory 203440 kb
Host smart-21d5f98b-2149-472e-bcaf-c91691c06b8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1086854623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1086854623
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.920420992
Short name T719
Test name
Test status
Simulation time 5404550300 ps
CPU time 33.93 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 203496 kb
Host smart-7e710eec-14ec-4cf8-b9e5-27a010137697
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=920420992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.920420992
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2523595139
Short name T804
Test name
Test status
Simulation time 4188910936 ps
CPU time 33.2 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:56:06 PM PDT 24
Peak memory 203544 kb
Host smart-76f7877c-584b-425f-838d-3953fe38f123
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2523595139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2523595139
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2477846447
Short name T619
Test name
Test status
Simulation time 31196665 ps
CPU time 2.51 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:55:38 PM PDT 24
Peak memory 203472 kb
Host smart-b319d08e-dbbc-4cc4-82eb-5d99db414a81
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477846447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2477846447
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.244436134
Short name T201
Test name
Test status
Simulation time 10420390015 ps
CPU time 68.3 seconds
Started Jul 12 05:55:40 PM PDT 24
Finished Jul 12 05:56:49 PM PDT 24
Peak memory 205920 kb
Host smart-d48c7f7f-2c50-4b1f-b0a1-c432c701c311
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=244436134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.244436134
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1262288696
Short name T147
Test name
Test status
Simulation time 7424339102 ps
CPU time 163.08 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 05:58:22 PM PDT 24
Peak memory 211928 kb
Host smart-36771eae-cc46-4cab-90d8-5b24e4444c4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262288696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1262288696
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.949501247
Short name T850
Test name
Test status
Simulation time 232253594 ps
CPU time 55.68 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 206980 kb
Host smart-8fe15602-5156-4dbc-9ce5-fd1028111c7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=949501247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand
_reset.949501247
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.982786074
Short name T343
Test name
Test status
Simulation time 276350041 ps
CPU time 82.22 seconds
Started Jul 12 05:55:39 PM PDT 24
Finished Jul 12 05:57:02 PM PDT 24
Peak memory 208844 kb
Host smart-2bcb4d95-71de-463a-9c6e-092fd6a46efc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=982786074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res
et_error.982786074
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.902084148
Short name T583
Test name
Test status
Simulation time 50935756 ps
CPU time 9.31 seconds
Started Jul 12 05:55:37 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 211624 kb
Host smart-863ca0a4-ea77-449d-aa99-678c22de2ca5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=902084148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.902084148
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3114303330
Short name T496
Test name
Test status
Simulation time 355046091 ps
CPU time 18.01 seconds
Started Jul 12 05:55:39 PM PDT 24
Finished Jul 12 05:55:58 PM PDT 24
Peak memory 211696 kb
Host smart-58a5dde8-a80d-4a59-b18a-0380dfb86f49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3114303330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3114303330
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3502841108
Short name T696
Test name
Test status
Simulation time 278671976 ps
CPU time 10.85 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 203464 kb
Host smart-05819ef0-f8f7-4a9d-9e6a-42e8b6c40fd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3502841108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3502841108
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.2021542787
Short name T641
Test name
Test status
Simulation time 90443338 ps
CPU time 3.75 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 05:55:42 PM PDT 24
Peak memory 203488 kb
Host smart-555ea710-a43c-4c7f-bfd1-cd7e21c2d45b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2021542787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2021542787
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.710667051
Short name T849
Test name
Test status
Simulation time 684371778 ps
CPU time 20.69 seconds
Started Jul 12 05:55:39 PM PDT 24
Finished Jul 12 05:56:01 PM PDT 24
Peak memory 204776 kb
Host smart-7cee5b04-6a6a-420b-ac18-3e3861e3c09c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=710667051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.710667051
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2011406249
Short name T242
Test name
Test status
Simulation time 13085444534 ps
CPU time 37.43 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:56:20 PM PDT 24
Peak memory 211692 kb
Host smart-772b31a6-bbd0-4b76-9086-f4497470c029
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011406249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2011406249
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1248445062
Short name T743
Test name
Test status
Simulation time 32558070913 ps
CPU time 243.29 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 211684 kb
Host smart-e83544fd-74f7-4f9f-a212-0cd8f8b0ea39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1248445062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1248445062
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2285013143
Short name T726
Test name
Test status
Simulation time 119701668 ps
CPU time 16.64 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:00 PM PDT 24
Peak memory 204692 kb
Host smart-e21632c2-612b-4b95-9b3b-3d3dacc9c780
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285013143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2285013143
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.2486586765
Short name T840
Test name
Test status
Simulation time 1749344760 ps
CPU time 19.97 seconds
Started Jul 12 05:55:40 PM PDT 24
Finished Jul 12 05:56:01 PM PDT 24
Peak memory 203492 kb
Host smart-85b49b99-0f0d-465d-b192-1198b267fa43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2486586765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2486586765
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.3369298642
Short name T432
Test name
Test status
Simulation time 148058668 ps
CPU time 2.26 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 05:55:41 PM PDT 24
Peak memory 203428 kb
Host smart-624cb33d-9394-48ef-b1ac-66920ee7fa3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3369298642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3369298642
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3647012170
Short name T44
Test name
Test status
Simulation time 15615739230 ps
CPU time 33.44 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:17 PM PDT 24
Peak memory 203500 kb
Host smart-f1a897f6-5cb6-44ce-bde4-ea9e4d8e0e47
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647012170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3647012170
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1263577478
Short name T50
Test name
Test status
Simulation time 5496031594 ps
CPU time 24.48 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 05:56:04 PM PDT 24
Peak memory 203532 kb
Host smart-039d712d-b10e-442e-93c6-a211f70f0dee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1263577478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1263577478
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.609551592
Short name T761
Test name
Test status
Simulation time 27761513 ps
CPU time 2.23 seconds
Started Jul 12 05:55:39 PM PDT 24
Finished Jul 12 05:55:42 PM PDT 24
Peak memory 203468 kb
Host smart-ec6ffd39-22c1-435f-8fb9-63625a56076e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609551592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.609551592
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2854441680
Short name T549
Test name
Test status
Simulation time 171328394 ps
CPU time 22.21 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:06 PM PDT 24
Peak memory 205460 kb
Host smart-08090b25-9c93-47ab-b01c-82b490977af9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2854441680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2854441680
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2280230790
Short name T670
Test name
Test status
Simulation time 7559171953 ps
CPU time 62.07 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 211704 kb
Host smart-3b5d0897-d02b-4f03-8131-c0425521de97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2280230790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2280230790
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.431298934
Short name T101
Test name
Test status
Simulation time 23923340 ps
CPU time 1.95 seconds
Started Jul 12 05:55:37 PM PDT 24
Finished Jul 12 05:55:41 PM PDT 24
Peak memory 203452 kb
Host smart-61c11009-710a-4ba4-adcf-99f56a64ea74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=431298934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.431298934
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1042926884
Short name T225
Test name
Test status
Simulation time 255403719 ps
CPU time 9.38 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:55:51 PM PDT 24
Peak memory 204232 kb
Host smart-8fed0cb3-8747-4dd0-88c4-4a5498b4d78d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1042926884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1042926884
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.74568244
Short name T286
Test name
Test status
Simulation time 312378282 ps
CPU time 10.87 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:55:56 PM PDT 24
Peak memory 203468 kb
Host smart-764e9b95-c163-4e99-8280-c6dcb9036ccc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74568244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.74568244
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.1183789572
Short name T679
Test name
Test status
Simulation time 2173726298 ps
CPU time 29.85 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:56:08 PM PDT 24
Peak memory 203572 kb
Host smart-2c2a0194-dbda-4a68-8495-6da7f87483d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1183789572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1183789572
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.469857464
Short name T188
Test name
Test status
Simulation time 1080829513 ps
CPU time 36.25 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 211668 kb
Host smart-4a5b12ec-2428-43ed-b510-e5107f9216b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=469857464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.469857464
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2113131447
Short name T375
Test name
Test status
Simulation time 9582980606 ps
CPU time 35.66 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:56:14 PM PDT 24
Peak memory 204676 kb
Host smart-6e2b97c2-4b02-48ff-b5f6-ab20734993c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113131447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2113131447
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1544685282
Short name T794
Test name
Test status
Simulation time 66610055285 ps
CPU time 142.81 seconds
Started Jul 12 05:55:44 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 211788 kb
Host smart-6c0ad4eb-bd9c-4742-a999-f5e66e11ac26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1544685282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1544685282
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2745549335
Short name T566
Test name
Test status
Simulation time 553850235 ps
CPU time 21.14 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:55:58 PM PDT 24
Peak memory 211652 kb
Host smart-4cada7fa-627c-4114-830f-4d2efee324ed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745549335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2745549335
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.31225810
Short name T249
Test name
Test status
Simulation time 451346985 ps
CPU time 10 seconds
Started Jul 12 05:55:38 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 203468 kb
Host smart-253bd38f-3d0d-4b90-9178-7a3b5c53f201
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31225810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.31225810
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.4113787971
Short name T438
Test name
Test status
Simulation time 21616784 ps
CPU time 2.17 seconds
Started Jul 12 05:55:36 PM PDT 24
Finished Jul 12 05:55:40 PM PDT 24
Peak memory 203480 kb
Host smart-66ae40d6-8053-47c0-bfcb-fdac49ce5dfa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4113787971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4113787971
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.4036750160
Short name T560
Test name
Test status
Simulation time 6813945143 ps
CPU time 34.37 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:56:16 PM PDT 24
Peak memory 203488 kb
Host smart-f1332cef-ada7-4710-a097-54f36fd73093
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036750160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4036750160
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3780417332
Short name T299
Test name
Test status
Simulation time 3584257759 ps
CPU time 24.29 seconds
Started Jul 12 05:55:35 PM PDT 24
Finished Jul 12 05:56:02 PM PDT 24
Peak memory 203440 kb
Host smart-43b731a5-c275-4c1a-9380-2efa5d8e031c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3780417332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3780417332
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.499797458
Short name T301
Test name
Test status
Simulation time 40702106 ps
CPU time 2.4 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:55:44 PM PDT 24
Peak memory 203416 kb
Host smart-61909aa9-e0d7-473a-a82f-b4f1a3599f73
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499797458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.499797458
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1758001471
Short name T18
Test name
Test status
Simulation time 3080431212 ps
CPU time 212.79 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:59:18 PM PDT 24
Peak memory 211716 kb
Host smart-34487497-84fe-472d-89fd-b27b2aa7c001
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1758001471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1758001471
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4227747088
Short name T547
Test name
Test status
Simulation time 885880034 ps
CPU time 23.53 seconds
Started Jul 12 05:55:45 PM PDT 24
Finished Jul 12 05:56:10 PM PDT 24
Peak memory 205272 kb
Host smart-4f89dca1-21f3-4eb2-a097-8ccc39b90bec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4227747088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4227747088
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.976781083
Short name T215
Test name
Test status
Simulation time 796456716 ps
CPU time 205.07 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 208820 kb
Host smart-dcdaa9c4-923f-43ff-84c4-05a1e6103b42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976781083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand
_reset.976781083
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2053082290
Short name T214
Test name
Test status
Simulation time 160980191 ps
CPU time 14.45 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:55:57 PM PDT 24
Peak memory 211688 kb
Host smart-58c8ee7f-9aea-4ffe-89d9-7a5551686a1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2053082290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2053082290
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3992922384
Short name T192
Test name
Test status
Simulation time 444595458 ps
CPU time 7.13 seconds
Started Jul 12 05:55:44 PM PDT 24
Finished Jul 12 05:55:53 PM PDT 24
Peak memory 203512 kb
Host smart-4337180d-43ae-4055-9103-59e3b804a3b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3992922384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3992922384
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3460978268
Short name T576
Test name
Test status
Simulation time 612856415 ps
CPU time 21.55 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:56:07 PM PDT 24
Peak memory 204128 kb
Host smart-542e352c-6787-483a-b79d-873169a857b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3460978268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3460978268
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.856592084
Short name T835
Test name
Test status
Simulation time 2677166033 ps
CPU time 33.24 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 203568 kb
Host smart-3ee46d34-7c5f-4f79-a37e-c94f28054d93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856592084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.856592084
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.457545819
Short name T220
Test name
Test status
Simulation time 2270434091 ps
CPU time 24.15 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:09 PM PDT 24
Peak memory 204816 kb
Host smart-4a244408-256a-4c45-8153-5676f9989db6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=457545819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.457545819
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2087379651
Short name T596
Test name
Test status
Simulation time 6236881937 ps
CPU time 29.63 seconds
Started Jul 12 05:55:41 PM PDT 24
Finished Jul 12 05:56:11 PM PDT 24
Peak memory 211692 kb
Host smart-f36a867b-eef2-4d50-9987-ea3613ef6111
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087379651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2087379651
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1931306542
Short name T721
Test name
Test status
Simulation time 30343367319 ps
CPU time 199.61 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:59:04 PM PDT 24
Peak memory 211692 kb
Host smart-71298a23-52e8-473f-98f3-ad0a93f560c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1931306542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1931306542
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.702832917
Short name T204
Test name
Test status
Simulation time 273022638 ps
CPU time 23.26 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:56:08 PM PDT 24
Peak memory 211552 kb
Host smart-1f048990-290c-4335-9d38-0808863c726f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702832917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.702832917
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1978032708
Short name T640
Test name
Test status
Simulation time 948746427 ps
CPU time 10.25 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:55:55 PM PDT 24
Peak memory 203532 kb
Host smart-bf857dd5-7874-4959-a648-2cf8a5ab17fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1978032708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1978032708
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.2591661180
Short name T814
Test name
Test status
Simulation time 109756080 ps
CPU time 3.05 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 203468 kb
Host smart-e966114e-5356-4f5d-a69d-c29465aeefd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2591661180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2591661180
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3472560925
Short name T325
Test name
Test status
Simulation time 23507656622 ps
CPU time 43.7 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:28 PM PDT 24
Peak memory 203544 kb
Host smart-a126e918-e7ce-4983-8b7e-9103ec5b0522
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472560925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3472560925
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.226498189
Short name T768
Test name
Test status
Simulation time 6115608414 ps
CPU time 25 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:09 PM PDT 24
Peak memory 203524 kb
Host smart-d24682be-527f-4946-8937-e563d5dd958a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=226498189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.226498189
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.437224049
Short name T817
Test name
Test status
Simulation time 26949108 ps
CPU time 2.1 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:55:47 PM PDT 24
Peak memory 203472 kb
Host smart-c0fa7f8e-6372-4ff6-b4ef-1c29ee8f3ea7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437224049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.437224049
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2319713065
Short name T338
Test name
Test status
Simulation time 596638297 ps
CPU time 43.85 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:56:29 PM PDT 24
Peak memory 206128 kb
Host smart-b50b7555-116a-4257-b74e-45e6e3da2500
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2319713065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2319713065
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2709766116
Short name T276
Test name
Test status
Simulation time 9498698693 ps
CPU time 68.86 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:53 PM PDT 24
Peak memory 204784 kb
Host smart-b48f1603-e580-4dfb-9ae3-861aa9a403dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2709766116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2709766116
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.806029732
Short name T786
Test name
Test status
Simulation time 107875313 ps
CPU time 42.87 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:56:28 PM PDT 24
Peak memory 206708 kb
Host smart-93d74ca7-1616-4e42-bf1a-5bbf00aad05e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=806029732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand
_reset.806029732
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.4044543774
Short name T297
Test name
Test status
Simulation time 2354719159 ps
CPU time 199.74 seconds
Started Jul 12 05:55:43 PM PDT 24
Finished Jul 12 05:59:05 PM PDT 24
Peak memory 210664 kb
Host smart-279ee36f-2e95-4f75-a4e4-71f1dd3fbd39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4044543774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.4044543774
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.589901626
Short name T178
Test name
Test status
Simulation time 887125047 ps
CPU time 19.77 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:04 PM PDT 24
Peak memory 204784 kb
Host smart-8bc3d085-9bb0-4ba4-bac1-0928a5016876
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=589901626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.589901626
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1902278875
Short name T552
Test name
Test status
Simulation time 1454269437 ps
CPU time 38.47 seconds
Started Jul 12 05:55:51 PM PDT 24
Finished Jul 12 05:56:30 PM PDT 24
Peak memory 211684 kb
Host smart-777eca98-e4c6-4a85-bcc4-31bacf184d49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1902278875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1902278875
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.604701234
Short name T94
Test name
Test status
Simulation time 88206375722 ps
CPU time 550.94 seconds
Started Jul 12 05:55:46 PM PDT 24
Finished Jul 12 06:04:58 PM PDT 24
Peak memory 211728 kb
Host smart-cab84649-ca28-4cc0-80c8-c8409e306647
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=604701234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo
w_rsp.604701234
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2136068652
Short name T326
Test name
Test status
Simulation time 155863252 ps
CPU time 5.97 seconds
Started Jul 12 05:55:46 PM PDT 24
Finished Jul 12 05:55:53 PM PDT 24
Peak memory 203456 kb
Host smart-108c7209-2eb8-4ef5-b319-4823be91ccff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2136068652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2136068652
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.149836820
Short name T491
Test name
Test status
Simulation time 133030768 ps
CPU time 14.95 seconds
Started Jul 12 05:55:49 PM PDT 24
Finished Jul 12 05:56:04 PM PDT 24
Peak memory 203504 kb
Host smart-98670cf6-c381-4f9c-9ca5-f8c206c7865b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=149836820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.149836820
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.2909517048
Short name T870
Test name
Test status
Simulation time 1100248602 ps
CPU time 26.44 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:11 PM PDT 24
Peak memory 211592 kb
Host smart-9728c8b2-676a-4112-858c-802c1f55a807
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2909517048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2909517048
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2298180637
Short name T221
Test name
Test status
Simulation time 59983404975 ps
CPU time 278.28 seconds
Started Jul 12 05:55:46 PM PDT 24
Finished Jul 12 06:00:25 PM PDT 24
Peak memory 211756 kb
Host smart-8722434e-8102-4562-8131-bac4bfce1cd4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298180637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2298180637
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3466892003
Short name T39
Test name
Test status
Simulation time 15302581746 ps
CPU time 101.61 seconds
Started Jul 12 05:55:49 PM PDT 24
Finished Jul 12 05:57:31 PM PDT 24
Peak memory 211740 kb
Host smart-cf4ca0f9-526e-4914-9530-bb0fd3f9c6f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3466892003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3466892003
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2605573795
Short name T68
Test name
Test status
Simulation time 74549710 ps
CPU time 3.16 seconds
Started Jul 12 05:55:47 PM PDT 24
Finished Jul 12 05:55:50 PM PDT 24
Peak memory 203496 kb
Host smart-44e755b8-d58e-41ba-ae6d-54752eee5c6f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605573795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2605573795
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.2232174575
Short name T532
Test name
Test status
Simulation time 429241833 ps
CPU time 10.36 seconds
Started Jul 12 05:55:50 PM PDT 24
Finished Jul 12 05:56:01 PM PDT 24
Peak memory 204120 kb
Host smart-1f3e5c83-a3b8-41a7-9057-751e8d4785f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2232174575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2232174575
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3288567069
Short name T367
Test name
Test status
Simulation time 38311361 ps
CPU time 2.36 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:55:46 PM PDT 24
Peak memory 203468 kb
Host smart-45a151f4-560d-4030-9f03-86554ba19b0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3288567069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3288567069
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.232301738
Short name T14
Test name
Test status
Simulation time 22623879454 ps
CPU time 41.12 seconds
Started Jul 12 05:55:44 PM PDT 24
Finished Jul 12 05:56:27 PM PDT 24
Peak memory 203480 kb
Host smart-23ccd949-69e3-4abd-8dd2-f965a956f01b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=232301738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.232301738
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.535087688
Short name T857
Test name
Test status
Simulation time 17097631709 ps
CPU time 40.93 seconds
Started Jul 12 05:55:42 PM PDT 24
Finished Jul 12 05:56:25 PM PDT 24
Peak memory 203544 kb
Host smart-2330ec55-bf6e-45b4-96e4-d8e9a5ef9efa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=535087688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.535087688
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2172048079
Short name T703
Test name
Test status
Simulation time 37311225 ps
CPU time 2.34 seconds
Started Jul 12 05:55:45 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 203540 kb
Host smart-5ffd9bd0-5c49-4c52-b0d1-92786279e8c0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172048079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2172048079
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1674740902
Short name T790
Test name
Test status
Simulation time 1331867737 ps
CPU time 113.51 seconds
Started Jul 12 05:55:47 PM PDT 24
Finished Jul 12 05:57:41 PM PDT 24
Peak memory 209152 kb
Host smart-6676cfb9-115d-4ee1-8527-0ca09f566125
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1674740902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1674740902
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3056902659
Short name T371
Test name
Test status
Simulation time 7762545591 ps
CPU time 119.69 seconds
Started Jul 12 05:55:53 PM PDT 24
Finished Jul 12 05:57:53 PM PDT 24
Peak memory 211720 kb
Host smart-a3018c36-97a6-4cd4-a3e3-04104d618388
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3056902659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3056902659
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3576017143
Short name T252
Test name
Test status
Simulation time 159008833 ps
CPU time 37.61 seconds
Started Jul 12 05:55:54 PM PDT 24
Finished Jul 12 05:56:32 PM PDT 24
Peak memory 206672 kb
Host smart-346191c2-d2b8-422f-9334-7923ceb285e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3576017143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.3576017143
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4136138198
Short name T771
Test name
Test status
Simulation time 2607725475 ps
CPU time 146.75 seconds
Started Jul 12 05:55:55 PM PDT 24
Finished Jul 12 05:58:23 PM PDT 24
Peak memory 210280 kb
Host smart-3935666c-e3b1-47a7-ae84-dfbad2afded2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4136138198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.4136138198
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.649035495
Short name T457
Test name
Test status
Simulation time 196707437 ps
CPU time 6.33 seconds
Started Jul 12 05:55:46 PM PDT 24
Finished Jul 12 05:55:53 PM PDT 24
Peak memory 211620 kb
Host smart-1e28d178-0f95-40c2-86a4-68985e14b2c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=649035495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.649035495
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3033029561
Short name T839
Test name
Test status
Simulation time 351530001 ps
CPU time 32.53 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 211640 kb
Host smart-3c40dc41-a4de-4366-80ef-65a6c1297a99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3033029561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3033029561
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1776504725
Short name T84
Test name
Test status
Simulation time 54009701185 ps
CPU time 328.33 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 06:01:27 PM PDT 24
Peak memory 211716 kb
Host smart-00dae8f1-8e1e-40e6-a480-cab6fa7b8ac4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1776504725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.1776504725
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3560499155
Short name T777
Test name
Test status
Simulation time 123468387 ps
CPU time 16.97 seconds
Started Jul 12 05:56:02 PM PDT 24
Finished Jul 12 05:56:20 PM PDT 24
Peak memory 203572 kb
Host smart-4829c5d0-f78b-40c8-b16b-60581bf171c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3560499155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3560499155
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.3908027156
Short name T21
Test name
Test status
Simulation time 184193085 ps
CPU time 24.35 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 05:56:23 PM PDT 24
Peak memory 203448 kb
Host smart-1e7d08b7-ad42-4659-ac95-91332c8f0b03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3908027156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3908027156
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.3009235344
Short name T611
Test name
Test status
Simulation time 36779183 ps
CPU time 2.4 seconds
Started Jul 12 05:56:00 PM PDT 24
Finished Jul 12 05:56:03 PM PDT 24
Peak memory 203836 kb
Host smart-b2225913-0c5f-4ba1-abc8-2e68923e9eeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3009235344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3009235344
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.709942752
Short name T529
Test name
Test status
Simulation time 18361916878 ps
CPU time 102.83 seconds
Started Jul 12 05:56:01 PM PDT 24
Finished Jul 12 05:57:44 PM PDT 24
Peak memory 211700 kb
Host smart-cf2eea30-21e4-49f1-925f-2eb5e7f4dbe6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=709942752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.709942752
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2275446568
Short name T289
Test name
Test status
Simulation time 46783596905 ps
CPU time 224.88 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 05:59:45 PM PDT 24
Peak memory 211692 kb
Host smart-032c86c7-2e57-4e34-af48-2895be8a6991
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2275446568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2275446568
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.965166474
Short name T651
Test name
Test status
Simulation time 197756219 ps
CPU time 18.28 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 05:56:17 PM PDT 24
Peak memory 211656 kb
Host smart-b34fa438-2d88-4ffb-961a-ab118a08f021
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965166474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.965166474
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.3621968133
Short name T451
Test name
Test status
Simulation time 365796054 ps
CPU time 16.69 seconds
Started Jul 12 05:55:57 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 203576 kb
Host smart-d19cd100-ee4d-47b7-8319-5bc172861996
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3621968133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3621968133
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.1960586171
Short name T125
Test name
Test status
Simulation time 143810192 ps
CPU time 3.46 seconds
Started Jul 12 05:55:52 PM PDT 24
Finished Jul 12 05:55:56 PM PDT 24
Peak memory 203476 kb
Host smart-482d6884-8e80-44cc-95e9-372918b9df49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960586171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1960586171
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2929748949
Short name T235
Test name
Test status
Simulation time 5451495528 ps
CPU time 30.75 seconds
Started Jul 12 05:55:56 PM PDT 24
Finished Jul 12 05:56:28 PM PDT 24
Peak memory 203520 kb
Host smart-6771c7f6-c00a-4d13-9768-b057ac869a5d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929748949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2929748949
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.505835557
Short name T335
Test name
Test status
Simulation time 2805632582 ps
CPU time 26.56 seconds
Started Jul 12 05:56:03 PM PDT 24
Finished Jul 12 05:56:30 PM PDT 24
Peak memory 203516 kb
Host smart-85362654-8a27-4798-ab6e-7a9556f27b27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=505835557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.505835557
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1650103583
Short name T449
Test name
Test status
Simulation time 35738268 ps
CPU time 2.26 seconds
Started Jul 12 05:55:51 PM PDT 24
Finished Jul 12 05:55:54 PM PDT 24
Peak memory 203488 kb
Host smart-1572bc8b-17ba-4425-a841-a8777130bf5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650103583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1650103583
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1072754162
Short name T47
Test name
Test status
Simulation time 1494438194 ps
CPU time 119.36 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:57:59 PM PDT 24
Peak memory 207852 kb
Host smart-434d802a-2005-4e3f-a613-9d1318a60d02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1072754162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1072754162
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.176779105
Short name T344
Test name
Test status
Simulation time 1877332359 ps
CPU time 175.18 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:58:55 PM PDT 24
Peak memory 210040 kb
Host smart-116d2038-598a-4f90-94bf-9647f59edca3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=176779105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.176779105
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.678431457
Short name T436
Test name
Test status
Simulation time 185256564 ps
CPU time 61.16 seconds
Started Jul 12 05:56:01 PM PDT 24
Finished Jul 12 05:57:03 PM PDT 24
Peak memory 207344 kb
Host smart-e19cb912-f879-4559-a733-278266bbca95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=678431457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand
_reset.678431457
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2665931227
Short name T417
Test name
Test status
Simulation time 216810955 ps
CPU time 15.1 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 211612 kb
Host smart-55d4d5ed-ae9b-400e-9d2c-80ca0a331ea8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2665931227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2665931227
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3585042496
Short name T75
Test name
Test status
Simulation time 1240879389 ps
CPU time 28.17 seconds
Started Jul 12 05:56:02 PM PDT 24
Finished Jul 12 05:56:31 PM PDT 24
Peak memory 211652 kb
Host smart-43a80710-fb6a-4f10-8db8-cbb38283f202
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585042496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3585042496
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2885929327
Short name T198
Test name
Test status
Simulation time 184454577529 ps
CPU time 417.6 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 06:03:02 PM PDT 24
Peak memory 211740 kb
Host smart-a1658940-045e-4b74-a051-c92bf458d594
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2885929327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.2885929327
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1735163666
Short name T586
Test name
Test status
Simulation time 1690078639 ps
CPU time 14.99 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:56:19 PM PDT 24
Peak memory 203484 kb
Host smart-a4a2a57f-2674-4bdd-99b8-162391d4ede5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1735163666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1735163666
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.3299306963
Short name T864
Test name
Test status
Simulation time 1405188053 ps
CPU time 15.73 seconds
Started Jul 12 05:56:03 PM PDT 24
Finished Jul 12 05:56:19 PM PDT 24
Peak memory 203460 kb
Host smart-c3595b1b-ac03-44e7-93cf-eaf79fd28481
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3299306963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3299306963
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.2037865623
Short name T76
Test name
Test status
Simulation time 552178854 ps
CPU time 9.77 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:56:10 PM PDT 24
Peak memory 204568 kb
Host smart-3dff8ee2-6c49-4b84-99e2-0c8103e56f99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2037865623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2037865623
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2696302822
Short name T41
Test name
Test status
Simulation time 17956143688 ps
CPU time 81.84 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 05:57:22 PM PDT 24
Peak memory 211644 kb
Host smart-124b0ba5-1dd3-43f7-b6e7-21ca3ebc2350
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696302822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2696302822
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3880201859
Short name T800
Test name
Test status
Simulation time 13856303504 ps
CPU time 97.36 seconds
Started Jul 12 05:55:58 PM PDT 24
Finished Jul 12 05:57:37 PM PDT 24
Peak memory 211712 kb
Host smart-18d42ab7-e0b5-44c9-9bb3-75feee04a6af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3880201859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3880201859
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3729143338
Short name T900
Test name
Test status
Simulation time 167694964 ps
CPU time 23.36 seconds
Started Jul 12 05:56:02 PM PDT 24
Finished Jul 12 05:56:26 PM PDT 24
Peak memory 211692 kb
Host smart-7cc8c19f-78ee-49ad-9f3d-8efa4842f174
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729143338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3729143338
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.491339120
Short name T363
Test name
Test status
Simulation time 9183983012 ps
CPU time 37.62 seconds
Started Jul 12 05:56:03 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 204584 kb
Host smart-ebeb6fff-a338-4626-a57c-10ce961096ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=491339120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.491339120
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.3607434393
Short name T556
Test name
Test status
Simulation time 45957568 ps
CPU time 2.23 seconds
Started Jul 12 05:55:56 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 203448 kb
Host smart-ed78bd4c-b205-489c-8bfa-6b683ffc0c22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3607434393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3607434393
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1758067734
Short name T663
Test name
Test status
Simulation time 15326757370 ps
CPU time 38.97 seconds
Started Jul 12 05:56:02 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 203528 kb
Host smart-c97a1581-ddb3-4211-8a11-47e21e00e7c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758067734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1758067734
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.180199501
Short name T5
Test name
Test status
Simulation time 3284655351 ps
CPU time 26.96 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:56:27 PM PDT 24
Peak memory 203488 kb
Host smart-0e671312-7978-467d-b41c-86e6d26dc39d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=180199501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.180199501
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2130309683
Short name T166
Test name
Test status
Simulation time 44721573 ps
CPU time 2.31 seconds
Started Jul 12 05:55:59 PM PDT 24
Finished Jul 12 05:56:02 PM PDT 24
Peak memory 203472 kb
Host smart-4cd247c2-bbda-4586-9ddd-749f4a2bbad9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130309683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2130309683
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.532648623
Short name T605
Test name
Test status
Simulation time 1169448387 ps
CPU time 39.65 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 05:56:54 PM PDT 24
Peak memory 205048 kb
Host smart-e329ec41-1c8c-4695-93e8-acaf8765d695
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=532648623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.532648623
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.590781885
Short name T513
Test name
Test status
Simulation time 6795775408 ps
CPU time 71.54 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:57:16 PM PDT 24
Peak memory 205928 kb
Host smart-810bf842-bad2-42ac-b28c-7dbacb8ce9e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=590781885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.590781885
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3603050132
Short name T765
Test name
Test status
Simulation time 2496540983 ps
CPU time 400.96 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 06:02:55 PM PDT 24
Peak memory 211712 kb
Host smart-9d6add6b-38ee-4473-9462-a88db292e67f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3603050132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.3603050132
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2306844493
Short name T261
Test name
Test status
Simulation time 172498742 ps
CPU time 37.95 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 05:56:53 PM PDT 24
Peak memory 206360 kb
Host smart-6224b808-d489-400d-a895-92035c51fef6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2306844493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2306844493
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3141050700
Short name T17
Test name
Test status
Simulation time 406388135 ps
CPU time 16.49 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:25 PM PDT 24
Peak memory 205020 kb
Host smart-bd11e47d-5c3c-453c-96af-15afcefeb427
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3141050700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3141050700
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1958112070
Short name T142
Test name
Test status
Simulation time 252545155 ps
CPU time 11.66 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:56:16 PM PDT 24
Peak memory 211664 kb
Host smart-4a38a861-4465-463b-a660-bdd4cc5dd450
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1958112070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1958112070
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3806627077
Short name T470
Test name
Test status
Simulation time 140382424648 ps
CPU time 526.5 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 06:05:00 PM PDT 24
Peak memory 211672 kb
Host smart-253ee8fb-3b0e-47cd-8bb6-068f78fbf8d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3806627077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.3806627077
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2397082929
Short name T413
Test name
Test status
Simulation time 202990008 ps
CPU time 6.52 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:20 PM PDT 24
Peak memory 203564 kb
Host smart-bcbb2cde-7257-4404-8e04-794fb67cd11d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2397082929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2397082929
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.670506866
Short name T415
Test name
Test status
Simulation time 892344698 ps
CPU time 21.08 seconds
Started Jul 12 05:56:05 PM PDT 24
Finished Jul 12 05:56:27 PM PDT 24
Peak memory 203492 kb
Host smart-2cf539ee-2da5-4515-88b3-3248f05559be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=670506866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.670506866
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1680785720
Short name T83
Test name
Test status
Simulation time 664388436 ps
CPU time 10.03 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:56:14 PM PDT 24
Peak memory 211656 kb
Host smart-70a5b9c3-728c-43c0-8def-55c3ac7401c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1680785720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1680785720
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.710431382
Short name T293
Test name
Test status
Simulation time 108591865545 ps
CPU time 222.42 seconds
Started Jul 12 05:56:03 PM PDT 24
Finished Jul 12 05:59:46 PM PDT 24
Peak memory 211696 kb
Host smart-582738f8-3344-40e4-a232-2a13a0a0366f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=710431382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.710431382
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1650724443
Short name T233
Test name
Test status
Simulation time 77954529888 ps
CPU time 251.37 seconds
Started Jul 12 05:56:01 PM PDT 24
Finished Jul 12 06:00:13 PM PDT 24
Peak memory 211716 kb
Host smart-2f35bb83-ac70-4b75-bdfc-1eea555458a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1650724443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1650724443
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.4152636905
Short name T395
Test name
Test status
Simulation time 700912818 ps
CPU time 15.31 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:56:19 PM PDT 24
Peak memory 211624 kb
Host smart-ba71792d-0ab0-49a2-b15f-f91904aaa778
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152636905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.4152636905
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.424653053
Short name T683
Test name
Test status
Simulation time 33050870 ps
CPU time 2.93 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:17 PM PDT 24
Peak memory 203464 kb
Host smart-dd441bc4-fdc2-4c49-9626-04cefb38a19e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=424653053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.424653053
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.656413286
Short name T877
Test name
Test status
Simulation time 32050006 ps
CPU time 1.94 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:10 PM PDT 24
Peak memory 203420 kb
Host smart-4631d7dd-03e1-4a01-99e5-557d92b219b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=656413286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.656413286
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.935283818
Short name T288
Test name
Test status
Simulation time 13353090787 ps
CPU time 31.58 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:56:36 PM PDT 24
Peak memory 203520 kb
Host smart-335516ae-e4e6-4596-afa6-302f9db07ba5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=935283818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.935283818
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4114444761
Short name T518
Test name
Test status
Simulation time 8859960789 ps
CPU time 26.21 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 203492 kb
Host smart-83c7ff14-4bf9-4ae1-8577-1e4c4efd8bd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4114444761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4114444761
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.103014764
Short name T486
Test name
Test status
Simulation time 47199380 ps
CPU time 2.34 seconds
Started Jul 12 05:56:04 PM PDT 24
Finished Jul 12 05:56:07 PM PDT 24
Peak memory 203500 kb
Host smart-34b89619-431d-4f68-bc0e-7bcb6582929b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103014764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.103014764
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1672282808
Short name T514
Test name
Test status
Simulation time 2047576804 ps
CPU time 209.99 seconds
Started Jul 12 05:56:06 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 210464 kb
Host smart-32fba1a6-8d46-4f87-a877-c2d460961e78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1672282808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1672282808
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.629276421
Short name T718
Test name
Test status
Simulation time 6924023198 ps
CPU time 135.3 seconds
Started Jul 12 05:56:07 PM PDT 24
Finished Jul 12 05:58:23 PM PDT 24
Peak memory 209008 kb
Host smart-f77d02a9-ddbe-4189-8f3a-ff7415bf2282
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=629276421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.629276421
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.640271621
Short name T124
Test name
Test status
Simulation time 3888377086 ps
CPU time 145.21 seconds
Started Jul 12 05:56:10 PM PDT 24
Finished Jul 12 05:58:36 PM PDT 24
Peak memory 209028 kb
Host smart-e4756516-4aa3-4d12-b7bc-51834721c3d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=640271621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand
_reset.640271621
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2216279219
Short name T708
Test name
Test status
Simulation time 14668885420 ps
CPU time 579.6 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 06:05:48 PM PDT 24
Peak memory 219804 kb
Host smart-a9540ee7-2b04-4860-b251-4db2c59745f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2216279219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2216279219
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3607895279
Short name T400
Test name
Test status
Simulation time 301424141 ps
CPU time 23.53 seconds
Started Jul 12 05:56:10 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 211604 kb
Host smart-10deca69-682a-4021-b5c0-bb1d727df3c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3607895279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3607895279
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1283270648
Short name T151
Test name
Test status
Simulation time 1815857323 ps
CPU time 69.2 seconds
Started Jul 12 05:56:10 PM PDT 24
Finished Jul 12 05:57:20 PM PDT 24
Peak memory 211684 kb
Host smart-18a23f27-3363-499d-bc76-c4e06e8d2901
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1283270648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1283270648
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3067805769
Short name T181
Test name
Test status
Simulation time 7449274684 ps
CPU time 71.58 seconds
Started Jul 12 05:56:11 PM PDT 24
Finished Jul 12 05:57:23 PM PDT 24
Peak memory 211716 kb
Host smart-14071d7b-c8e7-4688-b043-4b9029572730
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3067805769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.3067805769
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.803003116
Short name T792
Test name
Test status
Simulation time 154881615 ps
CPU time 7.24 seconds
Started Jul 12 05:56:09 PM PDT 24
Finished Jul 12 05:56:17 PM PDT 24
Peak memory 203504 kb
Host smart-8264a79c-4577-4d37-9623-0b3c5b1f9003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=803003116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.803003116
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.2294540996
Short name T687
Test name
Test status
Simulation time 1374339147 ps
CPU time 29.86 seconds
Started Jul 12 05:56:11 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 203516 kb
Host smart-1e2fec07-ae23-4c5e-82a6-7baedf9c7dda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2294540996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2294540996
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.3973303341
Short name T11
Test name
Test status
Simulation time 656243862 ps
CPU time 24.41 seconds
Started Jul 12 05:56:09 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 211644 kb
Host smart-67c87033-7bbb-499d-9728-d2dd5e522273
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3973303341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3973303341
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1214038145
Short name T643
Test name
Test status
Simulation time 47821867805 ps
CPU time 122.42 seconds
Started Jul 12 05:56:11 PM PDT 24
Finished Jul 12 05:58:14 PM PDT 24
Peak memory 211720 kb
Host smart-4040e414-ac00-46f1-be70-913501cce42a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214038145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1214038145
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.361829025
Short name T511
Test name
Test status
Simulation time 15686925234 ps
CPU time 114.35 seconds
Started Jul 12 05:56:09 PM PDT 24
Finished Jul 12 05:58:03 PM PDT 24
Peak memory 211732 kb
Host smart-abd26cba-405b-4ee0-85ab-091876c39ea6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=361829025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.361829025
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.513566576
Short name T461
Test name
Test status
Simulation time 144835417 ps
CPU time 18.9 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:28 PM PDT 24
Peak memory 211684 kb
Host smart-626a8869-5d29-4571-9a31-dc88fb9d00c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513566576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.513566576
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.438491509
Short name T516
Test name
Test status
Simulation time 607767119 ps
CPU time 8.75 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:18 PM PDT 24
Peak memory 203496 kb
Host smart-1c1ecb26-0ae1-4bf5-bcd5-8ae4ccd91019
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=438491509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.438491509
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2879049080
Short name T373
Test name
Test status
Simulation time 794605898 ps
CPU time 3.71 seconds
Started Jul 12 05:56:10 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 203424 kb
Host smart-56166ed8-ea18-45bf-b822-f5209b3cc28a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2879049080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2879049080
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2988981855
Short name T480
Test name
Test status
Simulation time 8257078428 ps
CPU time 31.01 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:40 PM PDT 24
Peak memory 203556 kb
Host smart-7bbe5774-8c9b-4f4f-ab63-09f73cf2e913
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988981855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2988981855
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2659266484
Short name T783
Test name
Test status
Simulation time 9725592382 ps
CPU time 36.12 seconds
Started Jul 12 05:56:12 PM PDT 24
Finished Jul 12 05:56:49 PM PDT 24
Peak memory 203484 kb
Host smart-48d278bb-2f40-4603-b37c-7cb2ad6f0477
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2659266484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2659266484
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3760802996
Short name T608
Test name
Test status
Simulation time 33845393 ps
CPU time 1.98 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:11 PM PDT 24
Peak memory 203456 kb
Host smart-867c80f2-d9a7-499f-b3ba-03b764d4ba26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760802996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3760802996
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1402854724
Short name T443
Test name
Test status
Simulation time 1425053046 ps
CPU time 27.63 seconds
Started Jul 12 05:56:07 PM PDT 24
Finished Jul 12 05:56:36 PM PDT 24
Peak memory 205088 kb
Host smart-e7efeb08-14ec-42b2-b692-9f7eadb130db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1402854724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1402854724
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3658023935
Short name T738
Test name
Test status
Simulation time 3815924557 ps
CPU time 74.06 seconds
Started Jul 12 05:56:09 PM PDT 24
Finished Jul 12 05:57:24 PM PDT 24
Peak memory 205968 kb
Host smart-f045848b-05c4-4776-a52a-083a30c9b1f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3658023935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3658023935
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3492976858
Short name T780
Test name
Test status
Simulation time 2979378532 ps
CPU time 319.31 seconds
Started Jul 12 05:56:12 PM PDT 24
Finished Jul 12 06:01:32 PM PDT 24
Peak memory 210572 kb
Host smart-dd23d9f3-43ef-49e2-aa99-ee4f06e85c36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3492976858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.3492976858
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1017693996
Short name T891
Test name
Test status
Simulation time 86007565 ps
CPU time 27.42 seconds
Started Jul 12 05:56:08 PM PDT 24
Finished Jul 12 05:56:36 PM PDT 24
Peak memory 205492 kb
Host smart-6a606e39-b6d4-4cfa-937b-f33c07509fb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1017693996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1017693996
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2811213151
Short name T766
Test name
Test status
Simulation time 226095763 ps
CPU time 5.21 seconds
Started Jul 12 05:56:11 PM PDT 24
Finished Jul 12 05:56:17 PM PDT 24
Peak memory 211668 kb
Host smart-4612e87d-7a1e-4af1-90cd-dcc7d43c64c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2811213151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2811213151
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3577779303
Short name T348
Test name
Test status
Simulation time 455642318 ps
CPU time 17.5 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 211700 kb
Host smart-84d27491-db8d-4ef9-ac58-69e6f967f152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3577779303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3577779303
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.616843127
Short name T688
Test name
Test status
Simulation time 63575061366 ps
CPU time 299.33 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 06:00:17 PM PDT 24
Peak memory 211708 kb
Host smart-b01a6754-680f-4058-acd3-d2fde9398ea3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=616843127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow
_rsp.616843127
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1969441270
Short name T521
Test name
Test status
Simulation time 527528696 ps
CPU time 20.75 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:55:38 PM PDT 24
Peak memory 203484 kb
Host smart-c2b8192a-77d9-4980-ac2a-97a7c1c018f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969441270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1969441270
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.1305716389
Short name T816
Test name
Test status
Simulation time 250936286 ps
CPU time 8.33 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:55:23 PM PDT 24
Peak memory 203440 kb
Host smart-604e35b9-ba0e-4c15-b944-c69e540b7fb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1305716389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1305716389
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.3485866982
Short name T67
Test name
Test status
Simulation time 24166304 ps
CPU time 3.38 seconds
Started Jul 12 05:55:18 PM PDT 24
Finished Jul 12 05:55:24 PM PDT 24
Peak memory 203468 kb
Host smart-79c6df5a-0eb5-4a5d-ae6f-2373735a7617
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3485866982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3485866982
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1278659972
Short name T190
Test name
Test status
Simulation time 62855155123 ps
CPU time 231.23 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 211696 kb
Host smart-d700ab43-82c4-49b2-9ab8-0b5c2f2e4962
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278659972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1278659972
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3642802553
Short name T153
Test name
Test status
Simulation time 47650889024 ps
CPU time 263.55 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:59:39 PM PDT 24
Peak memory 211732 kb
Host smart-f1b8ce68-ebd5-45f7-ab0e-566d29b9122d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3642802553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3642802553
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.726586850
Short name T333
Test name
Test status
Simulation time 58212677 ps
CPU time 7.35 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:55:29 PM PDT 24
Peak memory 204588 kb
Host smart-9cca566c-26da-48c9-a229-40e15c26dfe8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726586850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.726586850
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.2365594085
Short name T382
Test name
Test status
Simulation time 572946919 ps
CPU time 15.28 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:30 PM PDT 24
Peak memory 203560 kb
Host smart-8112be19-2ac6-4a86-84e7-eb2afb1f751d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365594085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2365594085
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.1749449017
Short name T775
Test name
Test status
Simulation time 165498386 ps
CPU time 4.05 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 203500 kb
Host smart-72990ff1-0377-4534-af3e-dd8ea2becee5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1749449017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1749449017
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.224627905
Short name T69
Test name
Test status
Simulation time 8641110399 ps
CPU time 32.55 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:55 PM PDT 24
Peak memory 203500 kb
Host smart-d649aca6-1e52-4d34-92db-0ebbbd4a5981
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=224627905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.224627905
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4084266642
Short name T847
Test name
Test status
Simulation time 3856525138 ps
CPU time 18.9 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:32 PM PDT 24
Peak memory 203520 kb
Host smart-453d3e18-521e-4d9c-8a7e-197adf484162
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4084266642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4084266642
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2055273914
Short name T823
Test name
Test status
Simulation time 110330437 ps
CPU time 2.11 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:55:24 PM PDT 24
Peak memory 203288 kb
Host smart-b18de60a-d528-4b81-bf14-1b64d9c7192b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055273914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2055273914
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2666009947
Short name T699
Test name
Test status
Simulation time 1507905736 ps
CPU time 124.99 seconds
Started Jul 12 05:55:18 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 211696 kb
Host smart-a3b27dce-6f37-4770-bd72-6660265b83e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2666009947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2666009947
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3934735622
Short name T562
Test name
Test status
Simulation time 6253459558 ps
CPU time 124.82 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 207676 kb
Host smart-1dd84ad6-a3c2-4b64-aaab-08d7e7517e9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934735622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3934735622
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1642303508
Short name T121
Test name
Test status
Simulation time 8080247762 ps
CPU time 501.76 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 06:03:38 PM PDT 24
Peak memory 208496 kb
Host smart-616f0ef3-7362-4e6a-b498-12f92d07379f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1642303508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.1642303508
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1766414825
Short name T873
Test name
Test status
Simulation time 880002367 ps
CPU time 77.31 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:56:32 PM PDT 24
Peak memory 208348 kb
Host smart-76910fc2-fc2c-4599-a55a-b09ff465ebc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1766414825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.1766414825
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3893501285
Short name T844
Test name
Test status
Simulation time 536174772 ps
CPU time 16.21 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:55:33 PM PDT 24
Peak memory 211656 kb
Host smart-03f5bd3e-d9b1-41bf-8608-5bcf8b1ffbec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3893501285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3893501285
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2672353367
Short name T789
Test name
Test status
Simulation time 124297074 ps
CPU time 5.85 seconds
Started Jul 12 05:56:15 PM PDT 24
Finished Jul 12 05:56:22 PM PDT 24
Peak memory 204164 kb
Host smart-20df662d-30c4-4579-8ea8-c6db80d5c061
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2672353367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2672353367
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3588767804
Short name T74
Test name
Test status
Simulation time 7609922500 ps
CPU time 67.56 seconds
Started Jul 12 05:56:17 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 211676 kb
Host smart-5c10a212-c8bc-436b-bed1-7da860ecd0ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3588767804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3588767804
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2493608107
Short name T582
Test name
Test status
Simulation time 1191456253 ps
CPU time 28.16 seconds
Started Jul 12 05:56:16 PM PDT 24
Finished Jul 12 05:56:45 PM PDT 24
Peak memory 203516 kb
Host smart-60886086-4af5-4ced-9e4c-0cd606171802
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2493608107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2493608107
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.2816008834
Short name T7
Test name
Test status
Simulation time 3386659362 ps
CPU time 24.25 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 203532 kb
Host smart-3e390a28-d46f-40d8-be61-4fdb98247013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2816008834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2816008834
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.2296395408
Short name T632
Test name
Test status
Simulation time 140937967 ps
CPU time 9.14 seconds
Started Jul 12 05:56:15 PM PDT 24
Finished Jul 12 05:56:25 PM PDT 24
Peak memory 211592 kb
Host smart-228d475e-b6d8-42d7-8ff7-1ff767d851e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2296395408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2296395408
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1133620401
Short name T336
Test name
Test status
Simulation time 48733946713 ps
CPU time 279.52 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 06:00:55 PM PDT 24
Peak memory 211732 kb
Host smart-84930fcd-db31-4fce-b411-ed38fc45fb03
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133620401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1133620401
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3876245927
Short name T323
Test name
Test status
Simulation time 49174856458 ps
CPU time 245.93 seconds
Started Jul 12 05:56:12 PM PDT 24
Finished Jul 12 06:00:19 PM PDT 24
Peak memory 211708 kb
Host smart-f9839ad5-9ca4-4a49-a337-ed6b957c0c40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3876245927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3876245927
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3884354262
Short name T434
Test name
Test status
Simulation time 174507379 ps
CPU time 23.29 seconds
Started Jul 12 05:56:15 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 211624 kb
Host smart-e3c99e3f-19f9-4984-9af4-9bdaa2ad5c46
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884354262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3884354262
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.4010086807
Short name T808
Test name
Test status
Simulation time 7365836440 ps
CPU time 28.98 seconds
Started Jul 12 05:56:16 PM PDT 24
Finished Jul 12 05:56:46 PM PDT 24
Peak memory 211752 kb
Host smart-25b492af-f254-48fd-9eef-367a47dcc5f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4010086807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.4010086807
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.2802266113
Short name T653
Test name
Test status
Simulation time 105655926 ps
CPU time 2.82 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:16 PM PDT 24
Peak memory 203424 kb
Host smart-1428df0e-a61f-414c-b854-679fdd11bb47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2802266113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2802266113
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1619372759
Short name T676
Test name
Test status
Simulation time 4307680746 ps
CPU time 22.88 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:37 PM PDT 24
Peak memory 203500 kb
Host smart-8309de02-8b81-4c56-a62c-2e719ad95031
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619372759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1619372759
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.4171317236
Short name T678
Test name
Test status
Simulation time 11271999291 ps
CPU time 36.02 seconds
Started Jul 12 05:56:17 PM PDT 24
Finished Jul 12 05:56:53 PM PDT 24
Peak memory 203492 kb
Host smart-39936d78-24a6-4d0f-9725-26de26cb5ce5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4171317236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.4171317236
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2419397296
Short name T424
Test name
Test status
Simulation time 50777087 ps
CPU time 2.41 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:16 PM PDT 24
Peak memory 203480 kb
Host smart-331057b1-28fb-4bdc-b231-90018f7fcd85
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419397296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2419397296
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3747388211
Short name T772
Test name
Test status
Simulation time 5001607537 ps
CPU time 98.77 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 05:57:54 PM PDT 24
Peak memory 206960 kb
Host smart-8b097219-28ac-44a0-b55b-183b46415da6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3747388211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3747388211
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.880719991
Short name T646
Test name
Test status
Simulation time 1969004300 ps
CPU time 108.36 seconds
Started Jul 12 05:56:16 PM PDT 24
Finished Jul 12 05:58:05 PM PDT 24
Peak memory 205432 kb
Host smart-3fe75696-44bb-4316-ab55-fed0710837ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=880719991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.880719991
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3639863071
Short name T661
Test name
Test status
Simulation time 331491393 ps
CPU time 122.17 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 207968 kb
Host smart-57075f10-cdcb-474a-ba3d-b0803b4dcb95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3639863071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.3639863071
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.180143115
Short name T476
Test name
Test status
Simulation time 113051609 ps
CPU time 5.58 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 05:56:21 PM PDT 24
Peak memory 211624 kb
Host smart-117942c5-ff36-412b-8a29-f8ad7366ddc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=180143115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.180143115
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3130743406
Short name T594
Test name
Test status
Simulation time 107011063 ps
CPU time 8.91 seconds
Started Jul 12 05:56:24 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 204544 kb
Host smart-31825f78-0b02-458f-95af-51952a81291f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3130743406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3130743406
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.539752676
Short name T71
Test name
Test status
Simulation time 26594018149 ps
CPU time 204.86 seconds
Started Jul 12 05:56:21 PM PDT 24
Finished Jul 12 05:59:46 PM PDT 24
Peak memory 211744 kb
Host smart-786269fa-fb0d-47f1-8558-b1024a383f73
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=539752676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slo
w_rsp.539752676
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1967978244
Short name T715
Test name
Test status
Simulation time 724961782 ps
CPU time 20.96 seconds
Started Jul 12 05:56:22 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 203500 kb
Host smart-21edf886-c9bc-4a8d-9701-125ff79b404d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1967978244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1967978244
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3603992791
Short name T309
Test name
Test status
Simulation time 178784779 ps
CPU time 4.81 seconds
Started Jul 12 05:56:20 PM PDT 24
Finished Jul 12 05:56:26 PM PDT 24
Peak memory 203512 kb
Host smart-8357f694-5b88-4595-b6cd-855e2c20948d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3603992791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3603992791
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.1619043054
Short name T191
Test name
Test status
Simulation time 141183430 ps
CPU time 17.46 seconds
Started Jul 12 05:56:16 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 211640 kb
Host smart-d4e5808d-c643-48e9-bc79-0504180dca83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1619043054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1619043054
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2194117455
Short name T635
Test name
Test status
Simulation time 4604544222 ps
CPU time 24.54 seconds
Started Jul 12 05:56:15 PM PDT 24
Finished Jul 12 05:56:40 PM PDT 24
Peak memory 204592 kb
Host smart-36e29557-3101-4b1e-b3f8-705f332a425a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194117455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2194117455
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2459209315
Short name T466
Test name
Test status
Simulation time 39939812317 ps
CPU time 195.79 seconds
Started Jul 12 05:56:20 PM PDT 24
Finished Jul 12 05:59:36 PM PDT 24
Peak memory 205032 kb
Host smart-7a949083-c516-4393-a2ca-405f4507f5d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2459209315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2459209315
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2521941646
Short name T273
Test name
Test status
Simulation time 49299033 ps
CPU time 5.97 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:19 PM PDT 24
Peak memory 211648 kb
Host smart-43f6ae15-bb1c-43de-ae34-23509acebb12
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521941646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2521941646
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.3606430081
Short name T447
Test name
Test status
Simulation time 925923751 ps
CPU time 21.35 seconds
Started Jul 12 05:56:22 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 203984 kb
Host smart-ad203102-3784-4d9e-b5cf-51d3f7833c75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3606430081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3606430081
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.2108935777
Short name T429
Test name
Test status
Simulation time 219812658 ps
CPU time 4.14 seconds
Started Jul 12 05:56:13 PM PDT 24
Finished Jul 12 05:56:19 PM PDT 24
Peak memory 203472 kb
Host smart-69e88bcc-fc69-4ff0-bc54-901109b2b751
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2108935777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2108935777
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.940754359
Short name T369
Test name
Test status
Simulation time 5771122775 ps
CPU time 22.9 seconds
Started Jul 12 05:56:15 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 203552 kb
Host smart-c66f90ff-d15a-43f9-a8ec-1f1cad5d2ebd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=940754359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.940754359
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.627918977
Short name T459
Test name
Test status
Simulation time 2433631544 ps
CPU time 23.29 seconds
Started Jul 12 05:56:14 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 203492 kb
Host smart-1b903242-b38b-427f-8d58-6bc82bc62693
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=627918977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.627918977
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1327695039
Short name T402
Test name
Test status
Simulation time 27875559 ps
CPU time 2.31 seconds
Started Jul 12 05:56:15 PM PDT 24
Finished Jul 12 05:56:18 PM PDT 24
Peak memory 203392 kb
Host smart-495be33d-cac9-48e2-9e72-535c603d1a10
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327695039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1327695039
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3674301022
Short name T186
Test name
Test status
Simulation time 1309409499 ps
CPU time 132.16 seconds
Started Jul 12 05:56:21 PM PDT 24
Finished Jul 12 05:58:33 PM PDT 24
Peak memory 209600 kb
Host smart-bbb0c82f-6618-4549-8a0e-1458115684c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3674301022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3674301022
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.952446317
Short name T454
Test name
Test status
Simulation time 8072213343 ps
CPU time 86.99 seconds
Started Jul 12 05:56:20 PM PDT 24
Finished Jul 12 05:57:48 PM PDT 24
Peak memory 206556 kb
Host smart-ad09eca6-3ebf-4ed9-813c-8264d35192c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952446317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.952446317
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2916271736
Short name T504
Test name
Test status
Simulation time 7636225 ps
CPU time 18.41 seconds
Started Jul 12 05:56:22 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 203852 kb
Host smart-f3defbad-765c-4c12-b85b-d221db83b3e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2916271736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.2916271736
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.4129927540
Short name T397
Test name
Test status
Simulation time 1342055830 ps
CPU time 81.95 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:57:46 PM PDT 24
Peak memory 209276 kb
Host smart-9d4fff76-ebbd-4f32-8156-58f107ad8b26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4129927540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.4129927540
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1846744285
Short name T539
Test name
Test status
Simulation time 662343660 ps
CPU time 13.29 seconds
Started Jul 12 05:56:28 PM PDT 24
Finished Jul 12 05:56:43 PM PDT 24
Peak memory 211588 kb
Host smart-fc1bd17a-37e6-4dbf-8019-79f55b9eab59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846744285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1846744285
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.447233571
Short name T70
Test name
Test status
Simulation time 997264561 ps
CPU time 22.43 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:56:46 PM PDT 24
Peak memory 211680 kb
Host smart-e2fb3ec6-bb52-4452-898b-dceeff9fb7de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=447233571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.447233571
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.132365622
Short name T801
Test name
Test status
Simulation time 77757406653 ps
CPU time 577.49 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 06:06:01 PM PDT 24
Peak memory 211756 kb
Host smart-1f6c98e0-3c3f-4e27-ba60-51c293d92bbb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=132365622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo
w_rsp.132365622
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.816127527
Short name T785
Test name
Test status
Simulation time 219104079 ps
CPU time 7.9 seconds
Started Jul 12 05:56:24 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 203660 kb
Host smart-4ed157fa-f05c-4d30-b5ab-c2efa6538ddb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=816127527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.816127527
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1253970051
Short name T354
Test name
Test status
Simulation time 242368911 ps
CPU time 5.62 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:56:30 PM PDT 24
Peak memory 203516 kb
Host smart-284d95c0-b534-41bd-aea3-bce1dc4464de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1253970051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1253970051
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.4125220124
Short name T168
Test name
Test status
Simulation time 49780216 ps
CPU time 6.04 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:35 PM PDT 24
Peak memory 211584 kb
Host smart-35492d60-9028-45de-bcd9-c33bfb873a58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4125220124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.4125220124
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3842989470
Short name T304
Test name
Test status
Simulation time 14197538502 ps
CPU time 70.54 seconds
Started Jul 12 05:56:24 PM PDT 24
Finished Jul 12 05:57:35 PM PDT 24
Peak memory 211752 kb
Host smart-58aa620e-956d-487a-9a54-b3d6f67c3ed0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842989470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3842989470
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.262802397
Short name T713
Test name
Test status
Simulation time 47822320754 ps
CPU time 224.26 seconds
Started Jul 12 05:56:22 PM PDT 24
Finished Jul 12 06:00:07 PM PDT 24
Peak memory 205616 kb
Host smart-e32cab76-c258-452d-8208-60174ef75498
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=262802397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.262802397
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.695764796
Short name T565
Test name
Test status
Simulation time 91380877 ps
CPU time 11.49 seconds
Started Jul 12 05:56:22 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 204544 kb
Host smart-60498f7b-c526-4f73-8a1e-0dd5541089b9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695764796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.695764796
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.1146069039
Short name T848
Test name
Test status
Simulation time 257747108 ps
CPU time 6.8 seconds
Started Jul 12 05:56:21 PM PDT 24
Finished Jul 12 05:56:28 PM PDT 24
Peak memory 203936 kb
Host smart-dda73249-cb64-4e34-8e91-6faf85f14a28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1146069039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1146069039
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.681662671
Short name T595
Test name
Test status
Simulation time 202307018 ps
CPU time 4.1 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 203380 kb
Host smart-d10df967-9ec4-401d-b36d-73811623acf7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681662671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.681662671
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1947732047
Short name T318
Test name
Test status
Simulation time 26541991413 ps
CPU time 41.26 seconds
Started Jul 12 05:56:21 PM PDT 24
Finished Jul 12 05:57:03 PM PDT 24
Peak memory 203496 kb
Host smart-236c7941-fc51-4ca4-a1a2-f700b81f2348
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947732047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1947732047
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2303319561
Short name T295
Test name
Test status
Simulation time 24321649882 ps
CPU time 32.98 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:56:57 PM PDT 24
Peak memory 203520 kb
Host smart-1bdd6646-2ae5-45a4-a3b6-556e99ffae68
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2303319561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2303319561
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1837609046
Short name T587
Test name
Test status
Simulation time 110322814 ps
CPU time 2.73 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:56:27 PM PDT 24
Peak memory 203476 kb
Host smart-1f9539e9-d61c-41c9-8ceb-d84521d900e5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837609046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1837609046
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.228460644
Short name T185
Test name
Test status
Simulation time 1198428839 ps
CPU time 156.49 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:59:00 PM PDT 24
Peak memory 206036 kb
Host smart-3fcad179-d204-40c3-9f01-c890b889e11b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=228460644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.228460644
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3469163475
Short name T240
Test name
Test status
Simulation time 3250475585 ps
CPU time 45.77 seconds
Started Jul 12 05:56:25 PM PDT 24
Finished Jul 12 05:57:12 PM PDT 24
Peak memory 205044 kb
Host smart-69773588-beed-4d99-aba1-a6e58bd099a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3469163475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3469163475
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.4186653393
Short name T427
Test name
Test status
Simulation time 588572817 ps
CPU time 200.41 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:59:47 PM PDT 24
Peak memory 208552 kb
Host smart-d4d95213-4d20-4576-a86b-e22e0f93ea65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4186653393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.4186653393
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3098199235
Short name T578
Test name
Test status
Simulation time 8640139037 ps
CPU time 150.21 seconds
Started Jul 12 05:56:28 PM PDT 24
Finished Jul 12 05:59:00 PM PDT 24
Peak memory 210392 kb
Host smart-d9426ec5-5199-4fa1-82b6-e6af031f1265
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3098199235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.3098199235
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.126365334
Short name T162
Test name
Test status
Simulation time 24205879 ps
CPU time 2.03 seconds
Started Jul 12 05:56:23 PM PDT 24
Finished Jul 12 05:56:26 PM PDT 24
Peak memory 203440 kb
Host smart-f98e1ac2-c155-4787-b184-aaca8077fd37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=126365334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.126365334
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2148664906
Short name T197
Test name
Test status
Simulation time 2174458265 ps
CPU time 45.28 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 211768 kb
Host smart-d8096079-25d5-4edc-b14a-739da7080c06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148664906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2148664906
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1705402042
Short name T138
Test name
Test status
Simulation time 18067752669 ps
CPU time 122.81 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:58:31 PM PDT 24
Peak memory 205252 kb
Host smart-27eb48a6-85bb-47ea-a25c-92f1cba33bc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1705402042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.1705402042
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2883916854
Short name T329
Test name
Test status
Simulation time 794210452 ps
CPU time 25.25 seconds
Started Jul 12 05:56:30 PM PDT 24
Finished Jul 12 05:56:56 PM PDT 24
Peak memory 203416 kb
Host smart-26adc4a9-e2f8-43d6-842b-0f250d965e5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2883916854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2883916854
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.3154006337
Short name T169
Test name
Test status
Simulation time 298213777 ps
CPU time 6.49 seconds
Started Jul 12 05:56:28 PM PDT 24
Finished Jul 12 05:56:36 PM PDT 24
Peak memory 203516 kb
Host smart-772f08dd-34e6-4a63-95d1-d8c1bc18f294
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3154006337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3154006337
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.554710330
Short name T445
Test name
Test status
Simulation time 1330824158 ps
CPU time 30.23 seconds
Started Jul 12 05:56:28 PM PDT 24
Finished Jul 12 05:57:00 PM PDT 24
Peak memory 211672 kb
Host smart-a6f3393d-faa6-451d-94c9-206cf3da5ad3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=554710330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.554710330
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1048424133
Short name T483
Test name
Test status
Simulation time 3377606437 ps
CPU time 14.94 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 203560 kb
Host smart-981b8292-37a3-44d5-9332-cb26544ae070
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048424133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1048424133
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1278181833
Short name T10
Test name
Test status
Simulation time 2223435917 ps
CPU time 20.56 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:50 PM PDT 24
Peak memory 203536 kb
Host smart-f7cf88c4-8b1e-4571-afb9-e129c137c241
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1278181833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1278181833
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4059755173
Short name T128
Test name
Test status
Simulation time 200843726 ps
CPU time 20.73 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:49 PM PDT 24
Peak memory 204700 kb
Host smart-b9755d74-58ef-4fec-ad31-b8d5369ae508
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059755173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.4059755173
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.1787331014
Short name T465
Test name
Test status
Simulation time 393415235 ps
CPU time 5.61 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 203492 kb
Host smart-87f12065-abae-4ee2-8de1-70c37bc281ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1787331014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1787331014
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.1752130134
Short name T622
Test name
Test status
Simulation time 275804974 ps
CPU time 3.45 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:56:30 PM PDT 24
Peak memory 203464 kb
Host smart-6e824ed9-d861-4a46-834e-e8d03e60fb77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752130134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1752130134
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4008875312
Short name T779
Test name
Test status
Simulation time 23045690801 ps
CPU time 38.86 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:57:06 PM PDT 24
Peak memory 203540 kb
Host smart-bed219c4-3ec7-4f73-bb75-b1d0fe204386
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008875312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4008875312
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1605853050
Short name T548
Test name
Test status
Simulation time 2539341101 ps
CPU time 24.17 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:56:52 PM PDT 24
Peak memory 203488 kb
Host smart-bb3bd0d4-68d1-4207-816b-840eb0859cae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1605853050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1605853050
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4151207066
Short name T337
Test name
Test status
Simulation time 55151062 ps
CPU time 2.56 seconds
Started Jul 12 05:56:30 PM PDT 24
Finished Jul 12 05:56:34 PM PDT 24
Peak memory 203472 kb
Host smart-a00332b3-c7ee-429e-aa03-16e8cfd301cd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151207066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4151207066
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.299325644
Short name T49
Test name
Test status
Simulation time 565712152 ps
CPU time 22.74 seconds
Started Jul 12 05:56:29 PM PDT 24
Finished Jul 12 05:56:53 PM PDT 24
Peak memory 206788 kb
Host smart-25ad3130-cafc-4e3b-b4b7-5aa7e7de707f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=299325644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.299325644
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.4052852325
Short name T317
Test name
Test status
Simulation time 2145228779 ps
CPU time 66.79 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:57:35 PM PDT 24
Peak memory 205908 kb
Host smart-1e3da385-14dd-4688-820a-c83a00125a3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4052852325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4052852325
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1401411418
Short name T34
Test name
Test status
Simulation time 1711605683 ps
CPU time 379.98 seconds
Started Jul 12 05:56:29 PM PDT 24
Finished Jul 12 06:02:50 PM PDT 24
Peak memory 208432 kb
Host smart-a90f5a00-c3b0-4f8f-b3b1-52ace0e345d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1401411418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.1401411418
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2543050882
Short name T439
Test name
Test status
Simulation time 10629469616 ps
CPU time 133.1 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:58:41 PM PDT 24
Peak memory 209836 kb
Host smart-69068722-b7c0-4648-809f-9786e278bf2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2543050882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.2543050882
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.22307415
Short name T163
Test name
Test status
Simulation time 111977481 ps
CPU time 4.25 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 211680 kb
Host smart-87b18b8c-7cfa-4c61-ad38-0e9eca4422ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22307415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.22307415
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3389364842
Short name T440
Test name
Test status
Simulation time 359247079 ps
CPU time 28.86 seconds
Started Jul 12 06:55:55 PM PDT 24
Finished Jul 12 06:56:25 PM PDT 24
Peak memory 211692 kb
Host smart-c32cb9a8-7455-410b-92d9-7a8996801b82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3389364842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3389364842
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2606295356
Short name T805
Test name
Test status
Simulation time 54974494170 ps
CPU time 176.47 seconds
Started Jul 12 06:16:34 PM PDT 24
Finished Jul 12 06:19:35 PM PDT 24
Peak memory 211712 kb
Host smart-8235f0dd-232d-4449-8adb-ea003d442d13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2606295356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.2606295356
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3842819019
Short name T710
Test name
Test status
Simulation time 281042378 ps
CPU time 9.44 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:38 PM PDT 24
Peak memory 203496 kb
Host smart-205fdbf8-5a27-414d-9772-79437ea8c318
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3842819019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3842819019
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.2041825864
Short name T563
Test name
Test status
Simulation time 233709557 ps
CPU time 10.8 seconds
Started Jul 12 06:46:51 PM PDT 24
Finished Jul 12 06:47:03 PM PDT 24
Peak memory 203416 kb
Host smart-610f4cde-211c-4b8a-a7c2-83f01940c128
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2041825864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2041825864
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2590490051
Short name T799
Test name
Test status
Simulation time 335347360 ps
CPU time 29.24 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:58 PM PDT 24
Peak memory 211668 kb
Host smart-c197cf41-47db-45ab-a52e-2a5bbb6c6aa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2590490051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2590490051
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3744101533
Short name T154
Test name
Test status
Simulation time 47195443199 ps
CPU time 159.77 seconds
Started Jul 12 05:56:29 PM PDT 24
Finished Jul 12 05:59:10 PM PDT 24
Peak memory 211744 kb
Host smart-8efc4545-9694-4ed7-bb7e-833f37274d69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744101533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3744101533
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3504595681
Short name T720
Test name
Test status
Simulation time 24952117658 ps
CPU time 163.29 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:59:12 PM PDT 24
Peak memory 211716 kb
Host smart-f919f160-a8e5-4b75-84c3-c5184da93e20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3504595681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3504595681
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.811710401
Short name T590
Test name
Test status
Simulation time 135545036 ps
CPU time 16.49 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 211616 kb
Host smart-99c2779a-7573-4e96-bf54-5f81b8300d5b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811710401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.811710401
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.2544165683
Short name T77
Test name
Test status
Simulation time 980133366 ps
CPU time 10.12 seconds
Started Jul 12 05:58:32 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 204036 kb
Host smart-cb5dc291-dec4-4b7b-bde1-d64bb1b2a781
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2544165683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2544165683
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.1481756476
Short name T874
Test name
Test status
Simulation time 177608813 ps
CPU time 3.67 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 203484 kb
Host smart-16821279-27b1-4fb6-9ac1-b31a19f44c84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1481756476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1481756476
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.492113470
Short name T745
Test name
Test status
Simulation time 15653902654 ps
CPU time 41.16 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:57:08 PM PDT 24
Peak memory 203528 kb
Host smart-da561cca-236a-48fb-ac5a-91403a86a271
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=492113470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.492113470
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2506547749
Short name T254
Test name
Test status
Simulation time 9746888051 ps
CPU time 28.52 seconds
Started Jul 12 05:56:28 PM PDT 24
Finished Jul 12 05:56:58 PM PDT 24
Peak memory 203504 kb
Host smart-0749ef9f-f4b4-4c2e-958c-e94633da3d6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2506547749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2506547749
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3074885701
Short name T414
Test name
Test status
Simulation time 39602121 ps
CPU time 2.19 seconds
Started Jul 12 05:56:29 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 203476 kb
Host smart-efb1fb07-ec3e-4749-a438-6d8e5099d755
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074885701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3074885701
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2718459415
Short name T834
Test name
Test status
Simulation time 1962345204 ps
CPU time 168.59 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 210444 kb
Host smart-5ea08423-be8b-48a4-9a46-21528e47a551
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2718459415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2718459415
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.148651494
Short name T294
Test name
Test status
Simulation time 2056275096 ps
CPU time 60.11 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:57:27 PM PDT 24
Peak memory 211636 kb
Host smart-ceb8c214-73af-48e5-9eaa-f2d63071c540
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=148651494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.148651494
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3653431501
Short name T740
Test name
Test status
Simulation time 17833897130 ps
CPU time 468.59 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 06:04:16 PM PDT 24
Peak memory 219892 kb
Host smart-808b81ab-997e-421b-9d0f-96840d7c079a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3653431501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.3653431501
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2486833889
Short name T479
Test name
Test status
Simulation time 7317343040 ps
CPU time 297.94 seconds
Started Jul 12 05:56:29 PM PDT 24
Finished Jul 12 06:01:28 PM PDT 24
Peak memory 211380 kb
Host smart-d0222938-ccc4-4ba9-9f1f-8ddb8335369b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2486833889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.2486833889
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1758169824
Short name T196
Test name
Test status
Simulation time 1416182409 ps
CPU time 28.03 seconds
Started Jul 12 05:56:26 PM PDT 24
Finished Jul 12 05:56:56 PM PDT 24
Peak memory 211676 kb
Host smart-431c418b-4a3c-491e-a388-4dc576df4911
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1758169824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1758169824
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1332584016
Short name T316
Test name
Test status
Simulation time 740863258 ps
CPU time 26.54 seconds
Started Jul 12 05:56:30 PM PDT 24
Finished Jul 12 05:56:57 PM PDT 24
Peak memory 205972 kb
Host smart-2f1c4961-40e9-435c-81d6-d844b07f111e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1332584016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1332584016
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.572800578
Short name T825
Test name
Test status
Simulation time 34324192807 ps
CPU time 292.49 seconds
Started Jul 12 05:56:34 PM PDT 24
Finished Jul 12 06:01:28 PM PDT 24
Peak memory 211680 kb
Host smart-64f1a7a6-62e6-4f8d-bd2b-5128cd109038
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=572800578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.572800578
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2143905295
Short name T36
Test name
Test status
Simulation time 307186362 ps
CPU time 9.24 seconds
Started Jul 12 05:56:31 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 203500 kb
Host smart-b0c4f35b-aefa-412f-b5a8-b9314f60a1e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2143905295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2143905295
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.2340055519
Short name T655
Test name
Test status
Simulation time 101170845 ps
CPU time 9.64 seconds
Started Jul 12 05:56:32 PM PDT 24
Finished Jul 12 05:56:43 PM PDT 24
Peak memory 203528 kb
Host smart-e9ed2861-95ab-4062-bfcc-67e102989dcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2340055519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2340055519
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.3767651211
Short name T95
Test name
Test status
Simulation time 281127901 ps
CPU time 8.22 seconds
Started Jul 12 05:56:38 PM PDT 24
Finished Jul 12 05:56:46 PM PDT 24
Peak memory 211680 kb
Host smart-4ff2ab16-a8c8-4904-be42-1a59b4aa8362
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3767651211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3767651211
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3511097702
Short name T303
Test name
Test status
Simulation time 18729930627 ps
CPU time 107.86 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:58:22 PM PDT 24
Peak memory 211756 kb
Host smart-1c2591fe-76d0-42ce-862f-e1a93f33c025
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511097702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3511097702
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1208798978
Short name T322
Test name
Test status
Simulation time 37408204872 ps
CPU time 147.26 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:59:02 PM PDT 24
Peak memory 211660 kb
Host smart-7abdcc3e-0d6d-47f6-b39e-263586fb0cbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1208798978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1208798978
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.637917026
Short name T453
Test name
Test status
Simulation time 30468818 ps
CPU time 2.29 seconds
Started Jul 12 05:56:32 PM PDT 24
Finished Jul 12 05:56:35 PM PDT 24
Peak memory 203500 kb
Host smart-7b4c3757-2e01-4f30-a581-a72702d680f6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637917026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.637917026
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.3322173031
Short name T682
Test name
Test status
Simulation time 716811167 ps
CPU time 14.05 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:56:48 PM PDT 24
Peak memory 203900 kb
Host smart-bef1455c-1a46-456b-aa88-38d7d02851c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3322173031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3322173031
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.1693837206
Short name T96
Test name
Test status
Simulation time 495167264 ps
CPU time 3.65 seconds
Started Jul 12 05:56:27 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 203480 kb
Host smart-64dbda48-847b-4495-a2c3-79d810adf522
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1693837206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1693837206
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3567208660
Short name T881
Test name
Test status
Simulation time 4201738096 ps
CPU time 27.15 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:57:01 PM PDT 24
Peak memory 203512 kb
Host smart-419086d7-97f7-4a0b-bb0f-b8bc2b8c1631
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567208660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3567208660
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.4155171187
Short name T717
Test name
Test status
Simulation time 4206779111 ps
CPU time 31.47 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:57:05 PM PDT 24
Peak memory 203492 kb
Host smart-347400b1-68d5-48dc-a588-21816b349389
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4155171187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4155171187
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3057872056
Short name T290
Test name
Test status
Simulation time 51136772 ps
CPU time 2.13 seconds
Started Jul 12 05:56:34 PM PDT 24
Finished Jul 12 05:56:37 PM PDT 24
Peak memory 203424 kb
Host smart-6e504b6b-b740-44e7-94e2-1d1b396101fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057872056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3057872056
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.831065732
Short name T536
Test name
Test status
Simulation time 3165830361 ps
CPU time 124.92 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:58:41 PM PDT 24
Peak memory 208000 kb
Host smart-7d4b03ac-ad47-467d-be4e-da2eb53dbe05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=831065732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.831065732
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1118155467
Short name T146
Test name
Test status
Simulation time 8203541669 ps
CPU time 237.87 seconds
Started Jul 12 05:56:31 PM PDT 24
Finished Jul 12 06:00:30 PM PDT 24
Peak memory 210984 kb
Host smart-9e919a67-dabd-4e62-b0ac-19d7f3884a44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1118155467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1118155467
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3084984483
Short name T359
Test name
Test status
Simulation time 1238368261 ps
CPU time 407.93 seconds
Started Jul 12 05:56:32 PM PDT 24
Finished Jul 12 06:03:21 PM PDT 24
Peak memory 208396 kb
Host smart-bce06536-3110-47ce-8115-ec4bad2b26e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3084984483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3084984483
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3122674402
Short name T592
Test name
Test status
Simulation time 749562162 ps
CPU time 222.6 seconds
Started Jul 12 05:56:32 PM PDT 24
Finished Jul 12 06:00:15 PM PDT 24
Peak memory 211644 kb
Host smart-0e1e1d20-ea49-475b-919e-a372507e52c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3122674402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.3122674402
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.315840468
Short name T73
Test name
Test status
Simulation time 815194449 ps
CPU time 11.03 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:56:47 PM PDT 24
Peak memory 211656 kb
Host smart-5816e02d-d458-4bc9-8e49-c98241585525
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=315840468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.315840468
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1196725477
Short name T829
Test name
Test status
Simulation time 1808551678 ps
CPU time 30.88 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:57:07 PM PDT 24
Peak memory 211664 kb
Host smart-dd737729-b0f1-4331-b1ef-2237ad91c738
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196725477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1196725477
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.4258039138
Short name T114
Test name
Test status
Simulation time 23270961766 ps
CPU time 201.87 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:59:58 PM PDT 24
Peak memory 211732 kb
Host smart-72226249-a1d1-4a05-8c92-2fb48218a8d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4258039138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.4258039138
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3772953898
Short name T349
Test name
Test status
Simulation time 3782115964 ps
CPU time 20.48 seconds
Started Jul 12 05:56:37 PM PDT 24
Finished Jul 12 05:56:59 PM PDT 24
Peak memory 203500 kb
Host smart-62718302-cd2c-4df3-886b-987d3424c770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3772953898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3772953898
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.3006233443
Short name T502
Test name
Test status
Simulation time 510514327 ps
CPU time 12.96 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:56:49 PM PDT 24
Peak memory 203512 kb
Host smart-71f9e0cb-b5e1-4dfc-9af0-e00dcb3fe88a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3006233443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3006233443
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.1729331325
Short name T405
Test name
Test status
Simulation time 1671413997 ps
CPU time 23.81 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:57:00 PM PDT 24
Peak memory 211656 kb
Host smart-9c0a87aa-9712-4aa4-8b6b-f09a8ccb628d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1729331325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1729331325
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.287031884
Short name T681
Test name
Test status
Simulation time 2051107098 ps
CPU time 12.54 seconds
Started Jul 12 05:56:34 PM PDT 24
Finished Jul 12 05:56:47 PM PDT 24
Peak memory 203460 kb
Host smart-ab1095b8-cc84-45b3-a7b8-ede25f707603
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=287031884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.287031884
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.388174810
Short name T714
Test name
Test status
Simulation time 42629143422 ps
CPU time 216.44 seconds
Started Jul 12 05:56:34 PM PDT 24
Finished Jul 12 06:00:11 PM PDT 24
Peak memory 211728 kb
Host smart-2fffd329-9e79-4dc4-8875-7a807a8fc79f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=388174810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.388174810
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.834842554
Short name T173
Test name
Test status
Simulation time 241400988 ps
CPU time 29.6 seconds
Started Jul 12 05:56:31 PM PDT 24
Finished Jul 12 05:57:01 PM PDT 24
Peak memory 205012 kb
Host smart-f1edf6f1-6087-488b-9898-29dc8df556db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834842554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.834842554
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.579293252
Short name T410
Test name
Test status
Simulation time 23666786 ps
CPU time 2.02 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:56:40 PM PDT 24
Peak memory 203484 kb
Host smart-3de458fa-af9d-44a5-9b3f-f19688aba09d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=579293252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.579293252
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.1478026149
Short name T665
Test name
Test status
Simulation time 50989550 ps
CPU time 2.16 seconds
Started Jul 12 05:56:32 PM PDT 24
Finished Jul 12 05:56:35 PM PDT 24
Peak memory 203492 kb
Host smart-1653280f-9c30-44f7-a9b3-1b5a136b5737
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1478026149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1478026149
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3121866051
Short name T896
Test name
Test status
Simulation time 6030632168 ps
CPU time 23.91 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:56:58 PM PDT 24
Peak memory 203512 kb
Host smart-153e5158-f8c5-4ad1-accf-e4cae10d7240
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121866051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3121866051
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3204746485
Short name T729
Test name
Test status
Simulation time 3086564475 ps
CPU time 23.28 seconds
Started Jul 12 05:56:31 PM PDT 24
Finished Jul 12 05:56:54 PM PDT 24
Peak memory 203524 kb
Host smart-3a177edf-6365-47eb-8ddd-21ea87154d38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3204746485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3204746485
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4098395640
Short name T564
Test name
Test status
Simulation time 98677055 ps
CPU time 2.56 seconds
Started Jul 12 05:56:33 PM PDT 24
Finished Jul 12 05:56:37 PM PDT 24
Peak memory 203448 kb
Host smart-32a00435-3679-46fe-b129-45e1d426da8a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098395640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4098395640
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2051333751
Short name T866
Test name
Test status
Simulation time 13683842306 ps
CPU time 345.24 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 06:02:21 PM PDT 24
Peak memory 211720 kb
Host smart-25327cd1-634f-40fb-ac20-df84e442da2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2051333751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2051333751
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1292634584
Short name T398
Test name
Test status
Simulation time 9807477696 ps
CPU time 231.02 seconds
Started Jul 12 05:56:38 PM PDT 24
Finished Jul 12 06:00:30 PM PDT 24
Peak memory 209672 kb
Host smart-0d09f258-a1f7-4ba8-9030-45d46d14b089
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1292634584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1292634584
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1359757485
Short name T843
Test name
Test status
Simulation time 42964929 ps
CPU time 14.56 seconds
Started Jul 12 05:56:37 PM PDT 24
Finished Jul 12 05:56:52 PM PDT 24
Peak memory 206060 kb
Host smart-b1402f01-8645-4c13-9ca2-f60ae21a8c54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1359757485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1359757485
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3533969649
Short name T620
Test name
Test status
Simulation time 28080191 ps
CPU time 34.14 seconds
Started Jul 12 05:56:38 PM PDT 24
Finished Jul 12 05:57:12 PM PDT 24
Peak memory 206260 kb
Host smart-b0ae95b3-a957-402c-879e-2c2487884367
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3533969649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.3533969649
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2361194578
Short name T456
Test name
Test status
Simulation time 666792787 ps
CPU time 18.09 seconds
Started Jul 12 05:56:38 PM PDT 24
Finished Jul 12 05:56:56 PM PDT 24
Peak memory 211648 kb
Host smart-de51bccb-1430-40c8-a80b-01d27aa6c36b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2361194578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2361194578
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.4195002397
Short name T93
Test name
Test status
Simulation time 1569621250 ps
CPU time 31.73 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:57:09 PM PDT 24
Peak memory 211640 kb
Host smart-1493db44-bbc0-499e-b177-7438a58504a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4195002397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.4195002397
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3072187072
Short name T224
Test name
Test status
Simulation time 67375811929 ps
CPU time 383.85 seconds
Started Jul 12 05:56:37 PM PDT 24
Finished Jul 12 06:03:01 PM PDT 24
Peak memory 211676 kb
Host smart-76bba956-bbe3-4726-b789-c776b4431c4d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3072187072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.3072187072
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3475500001
Short name T546
Test name
Test status
Simulation time 38567886 ps
CPU time 3.54 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:56:41 PM PDT 24
Peak memory 203444 kb
Host smart-c06b4ad0-fefa-447c-9109-ab20e6e74d10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3475500001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3475500001
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.990034631
Short name T528
Test name
Test status
Simulation time 140051860 ps
CPU time 20.35 seconds
Started Jul 12 05:56:38 PM PDT 24
Finished Jul 12 05:56:59 PM PDT 24
Peak memory 203524 kb
Host smart-45c3647c-30bf-4883-a085-1d54e3ffda99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=990034631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.990034631
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.410519177
Short name T629
Test name
Test status
Simulation time 885061221 ps
CPU time 33.66 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:57:11 PM PDT 24
Peak memory 211696 kb
Host smart-0b937033-b061-410c-8278-36cf6b8d80a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=410519177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.410519177
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.4197783823
Short name T370
Test name
Test status
Simulation time 87767961449 ps
CPU time 238.74 seconds
Started Jul 12 05:56:37 PM PDT 24
Finished Jul 12 06:00:37 PM PDT 24
Peak memory 205284 kb
Host smart-e7495bb3-0484-4b56-a3af-a526a67c61b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197783823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4197783823
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.956583258
Short name T356
Test name
Test status
Simulation time 5790575714 ps
CPU time 48.63 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 211696 kb
Host smart-1813e471-4a99-4fd5-b60e-ead29e54cb73
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=956583258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.956583258
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2312196197
Short name T102
Test name
Test status
Simulation time 82400772 ps
CPU time 10.63 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:56:47 PM PDT 24
Peak memory 211676 kb
Host smart-e66b61f8-8533-4ded-aa24-11c1aa99b0b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312196197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2312196197
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.682175253
Short name T475
Test name
Test status
Simulation time 569251328 ps
CPU time 12.9 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:56:50 PM PDT 24
Peak memory 204056 kb
Host smart-03cecfa9-d8a6-4a76-9db3-00d73de9c870
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682175253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.682175253
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.4074937513
Short name T573
Test name
Test status
Simulation time 41332946 ps
CPU time 1.76 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:56:38 PM PDT 24
Peak memory 203472 kb
Host smart-442fc970-e1ba-447c-a7bf-498c1ff1d4f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4074937513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.4074937513
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2465391529
Short name T380
Test name
Test status
Simulation time 4566094467 ps
CPU time 24.27 seconds
Started Jul 12 05:56:35 PM PDT 24
Finished Jul 12 05:57:01 PM PDT 24
Peak memory 203552 kb
Host smart-0f314cac-8b57-46e7-9cff-520a966f5683
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465391529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2465391529
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1571571087
Short name T130
Test name
Test status
Simulation time 6667098964 ps
CPU time 26.01 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:57:03 PM PDT 24
Peak memory 203496 kb
Host smart-e8d84cf9-db10-4729-8f99-da7513874a29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1571571087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1571571087
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1857508391
Short name T334
Test name
Test status
Simulation time 37527406 ps
CPU time 2.31 seconds
Started Jul 12 05:56:36 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 203464 kb
Host smart-25471281-9cb1-4f8a-a2ba-594195f74034
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857508391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1857508391
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.2004142179
Short name T32
Test name
Test status
Simulation time 10157730589 ps
CPU time 178.14 seconds
Started Jul 12 05:56:42 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 209496 kb
Host smart-e285d8c2-3cce-4c30-8344-387b0365cf8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2004142179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2004142179
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1804479760
Short name T700
Test name
Test status
Simulation time 2156828028 ps
CPU time 67.05 seconds
Started Jul 12 05:56:41 PM PDT 24
Finished Jul 12 05:57:48 PM PDT 24
Peak memory 211688 kb
Host smart-24e884ea-21cf-4e14-8848-3ba7bfcb6ff8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804479760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1804479760
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3834476867
Short name T558
Test name
Test status
Simulation time 305412345 ps
CPU time 175.2 seconds
Started Jul 12 05:56:42 PM PDT 24
Finished Jul 12 05:59:38 PM PDT 24
Peak memory 208040 kb
Host smart-a04dc9cf-c0a3-430d-922b-38fa5ac82f96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3834476867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.3834476867
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3374095910
Short name T392
Test name
Test status
Simulation time 4597125171 ps
CPU time 178.73 seconds
Started Jul 12 05:56:41 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 211332 kb
Host smart-8b33f140-3c5b-4578-b351-521313a53680
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3374095910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.3374095910
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.903000643
Short name T283
Test name
Test status
Simulation time 135089407 ps
CPU time 20.1 seconds
Started Jul 12 05:56:37 PM PDT 24
Finished Jul 12 05:56:58 PM PDT 24
Peak memory 211672 kb
Host smart-6b3b28e2-c845-4232-95d0-f215c62f775a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903000643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.903000643
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1344152882
Short name T91
Test name
Test status
Simulation time 1581316970 ps
CPU time 31.3 seconds
Started Jul 12 05:56:44 PM PDT 24
Finished Jul 12 05:57:16 PM PDT 24
Peak memory 211684 kb
Host smart-ec7cddb7-6829-48c0-8afa-7dd5fe1c7f2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1344152882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1344152882
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2298371441
Short name T875
Test name
Test status
Simulation time 52940432 ps
CPU time 8.11 seconds
Started Jul 12 05:56:41 PM PDT 24
Finished Jul 12 05:56:50 PM PDT 24
Peak memory 203488 kb
Host smart-2225a843-1e4e-4a2d-b188-c006bb9ad9c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2298371441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2298371441
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.3038369582
Short name T132
Test name
Test status
Simulation time 68260402 ps
CPU time 2.87 seconds
Started Jul 12 05:56:40 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 203496 kb
Host smart-9c935dd4-bf94-41f1-971d-15e5733af020
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3038369582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3038369582
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.2037986530
Short name T666
Test name
Test status
Simulation time 3350857045 ps
CPU time 30.46 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:57:17 PM PDT 24
Peak memory 211792 kb
Host smart-7eb301c1-36b4-438e-a019-e8d9a22157fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2037986530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2037986530
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1610905237
Short name T37
Test name
Test status
Simulation time 44278453061 ps
CPU time 169.79 seconds
Started Jul 12 05:56:41 PM PDT 24
Finished Jul 12 05:59:31 PM PDT 24
Peak memory 205372 kb
Host smart-b4ee33db-21e0-431e-86bb-0dc9bb5cec9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610905237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1610905237
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3058866538
Short name T796
Test name
Test status
Simulation time 17240304833 ps
CPU time 66.46 seconds
Started Jul 12 05:56:43 PM PDT 24
Finished Jul 12 05:57:50 PM PDT 24
Peak memory 204720 kb
Host smart-cc5f2d63-3275-4b93-8c1a-1e504bcce21b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3058866538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3058866538
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1138805830
Short name T527
Test name
Test status
Simulation time 80549104 ps
CPU time 8.13 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:56:55 PM PDT 24
Peak memory 211728 kb
Host smart-20135ec2-966a-4925-ba80-01adff4c82fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138805830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1138805830
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.2148318962
Short name T802
Test name
Test status
Simulation time 1540663900 ps
CPU time 37.09 seconds
Started Jul 12 05:56:41 PM PDT 24
Finished Jul 12 05:57:19 PM PDT 24
Peak memory 203500 kb
Host smart-5a7fa697-4dd4-4cd9-b6ea-618b805891c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2148318962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2148318962
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.981090806
Short name T689
Test name
Test status
Simulation time 35151975 ps
CPU time 1.89 seconds
Started Jul 12 05:56:43 PM PDT 24
Finished Jul 12 05:56:45 PM PDT 24
Peak memory 203480 kb
Host smart-7acaa896-af42-4b49-af0d-dd1823d689c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=981090806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.981090806
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1036822178
Short name T212
Test name
Test status
Simulation time 12479534141 ps
CPU time 43.31 seconds
Started Jul 12 05:56:42 PM PDT 24
Finished Jul 12 05:57:26 PM PDT 24
Peak memory 203532 kb
Host smart-708b3d35-3a93-4035-84fd-51d2027826ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036822178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1036822178
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.385423893
Short name T795
Test name
Test status
Simulation time 6414821053 ps
CPU time 32.18 seconds
Started Jul 12 05:56:41 PM PDT 24
Finished Jul 12 05:57:14 PM PDT 24
Peak memory 203540 kb
Host smart-fe593552-1834-4870-bfd9-50444fb400f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=385423893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.385423893
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.943198414
Short name T469
Test name
Test status
Simulation time 37024833 ps
CPU time 2.34 seconds
Started Jul 12 05:56:42 PM PDT 24
Finished Jul 12 05:56:45 PM PDT 24
Peak memory 203468 kb
Host smart-380a6005-07f7-44c1-aaf2-3913203708a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943198414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.943198414
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3089746617
Short name T136
Test name
Test status
Simulation time 4793168739 ps
CPU time 174.26 seconds
Started Jul 12 05:56:43 PM PDT 24
Finished Jul 12 05:59:38 PM PDT 24
Peak memory 209268 kb
Host smart-516b2a55-d04e-4e67-b235-3dbe7b4631a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3089746617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3089746617
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1270868279
Short name T256
Test name
Test status
Simulation time 1354858587 ps
CPU time 100.94 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:58:29 PM PDT 24
Peak memory 206684 kb
Host smart-7a78d60b-e3fa-4065-a310-03ac1649aa3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1270868279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1270868279
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1016048976
Short name T385
Test name
Test status
Simulation time 182343979 ps
CPU time 103.88 seconds
Started Jul 12 05:56:47 PM PDT 24
Finished Jul 12 05:58:32 PM PDT 24
Peak memory 209172 kb
Host smart-e453f1f1-a633-4e13-9d9b-809b10c51ed2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1016048976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1016048976
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2367420422
Short name T420
Test name
Test status
Simulation time 249249688 ps
CPU time 22.21 seconds
Started Jul 12 05:56:45 PM PDT 24
Finished Jul 12 05:57:08 PM PDT 24
Peak memory 211740 kb
Host smart-951dae6d-4e69-41d6-a546-351b973edcb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2367420422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2367420422
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1420853097
Short name T43
Test name
Test status
Simulation time 1735946624 ps
CPU time 59.58 seconds
Started Jul 12 05:56:50 PM PDT 24
Finished Jul 12 05:57:50 PM PDT 24
Peak memory 211676 kb
Host smart-28be3089-25a1-4777-bd83-698873624068
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1420853097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1420853097
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1279500003
Short name T607
Test name
Test status
Simulation time 93397669577 ps
CPU time 822.01 seconds
Started Jul 12 05:56:48 PM PDT 24
Finished Jul 12 06:10:31 PM PDT 24
Peak memory 211684 kb
Host smart-0baeeb4d-1d72-44ad-8936-104fb6481ae3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1279500003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.1279500003
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.4249810229
Short name T832
Test name
Test status
Simulation time 21488511 ps
CPU time 3.06 seconds
Started Jul 12 05:56:54 PM PDT 24
Finished Jul 12 05:56:58 PM PDT 24
Peak memory 203440 kb
Host smart-f4a93625-1522-47ac-af29-060ad2f205a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4249810229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.4249810229
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.174860395
Short name T756
Test name
Test status
Simulation time 355119476 ps
CPU time 9.55 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:56:57 PM PDT 24
Peak memory 203480 kb
Host smart-a4394a50-b81b-43fe-85bb-7c7480b7428b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=174860395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.174860395
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2106799540
Short name T709
Test name
Test status
Simulation time 109053124 ps
CPU time 14.69 seconds
Started Jul 12 05:56:47 PM PDT 24
Finished Jul 12 05:57:02 PM PDT 24
Peak memory 204780 kb
Host smart-691e17ee-ba6b-45aa-ad4c-834b22669e9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2106799540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2106799540
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2407040451
Short name T236
Test name
Test status
Simulation time 21087563863 ps
CPU time 98.15 seconds
Started Jul 12 05:56:49 PM PDT 24
Finished Jul 12 05:58:27 PM PDT 24
Peak memory 211752 kb
Host smart-ecac3bd7-0980-462c-9806-12a48dbf008b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407040451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2407040451
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1320209625
Short name T754
Test name
Test status
Simulation time 47681128556 ps
CPU time 249.73 seconds
Started Jul 12 05:56:48 PM PDT 24
Finished Jul 12 06:00:59 PM PDT 24
Peak memory 211704 kb
Host smart-e5ab6adf-f12a-4ca1-9cc7-549b2192e6a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1320209625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1320209625
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.980169410
Short name T217
Test name
Test status
Simulation time 173271098 ps
CPU time 28.73 seconds
Started Jul 12 05:56:48 PM PDT 24
Finished Jul 12 05:57:18 PM PDT 24
Peak memory 211700 kb
Host smart-d7f53996-9b48-4750-8898-bb633d9b0073
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980169410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.980169410
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.2556319854
Short name T747
Test name
Test status
Simulation time 1348410714 ps
CPU time 35.45 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:57:23 PM PDT 24
Peak memory 204120 kb
Host smart-9ff57e10-e1fe-495b-9b33-9e5ec1374477
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2556319854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2556319854
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.2688097861
Short name T223
Test name
Test status
Simulation time 108069921 ps
CPU time 2.31 seconds
Started Jul 12 05:56:48 PM PDT 24
Finished Jul 12 05:56:51 PM PDT 24
Peak memory 203476 kb
Host smart-ab7837e2-bd9a-4b02-8ad0-d2fa5db7a1bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2688097861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2688097861
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2612269724
Short name T626
Test name
Test status
Simulation time 16874891656 ps
CPU time 32.52 seconds
Started Jul 12 05:56:47 PM PDT 24
Finished Jul 12 05:57:21 PM PDT 24
Peak memory 203560 kb
Host smart-b7aa875b-588d-4dec-8f01-da2f133d04cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612269724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2612269724
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.82402217
Short name T712
Test name
Test status
Simulation time 8985735486 ps
CPU time 32.01 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:57:19 PM PDT 24
Peak memory 203504 kb
Host smart-0ba40409-f635-432a-9e76-7dab6c67f59b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=82402217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.82402217
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.222670426
Short name T522
Test name
Test status
Simulation time 112630189 ps
CPU time 2.49 seconds
Started Jul 12 05:56:46 PM PDT 24
Finished Jul 12 05:56:50 PM PDT 24
Peak memory 203468 kb
Host smart-ff14a22a-3856-41f8-8bdd-f9de2efa6eca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222670426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.222670426
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.603363234
Short name T15
Test name
Test status
Simulation time 255591863 ps
CPU time 40.76 seconds
Started Jul 12 05:56:52 PM PDT 24
Finished Jul 12 05:57:34 PM PDT 24
Peak memory 205692 kb
Host smart-5a46bc64-aa7a-4f5f-9022-959986f2d979
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=603363234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.603363234
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.884276617
Short name T320
Test name
Test status
Simulation time 3455570554 ps
CPU time 34.05 seconds
Started Jul 12 05:56:55 PM PDT 24
Finished Jul 12 05:57:30 PM PDT 24
Peak memory 203804 kb
Host smart-15db376e-a802-49bf-b0e8-e868af435f84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=884276617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.884276617
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1750617025
Short name T115
Test name
Test status
Simulation time 6790477330 ps
CPU time 455.69 seconds
Started Jul 12 05:56:50 PM PDT 24
Finished Jul 12 06:04:26 PM PDT 24
Peak memory 221704 kb
Host smart-0f37ff7c-29e8-4774-b91a-ce54ee5f25bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1750617025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1750617025
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1268292163
Short name T307
Test name
Test status
Simulation time 154536717 ps
CPU time 66.76 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:58:12 PM PDT 24
Peak memory 207236 kb
Host smart-f174f7a1-10b9-41ec-8967-9b71167d0b26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1268292163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1268292163
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.213715041
Short name T187
Test name
Test status
Simulation time 4107524104 ps
CPU time 35.13 seconds
Started Jul 12 05:56:52 PM PDT 24
Finished Jul 12 05:57:28 PM PDT 24
Peak memory 204892 kb
Host smart-09709789-9fe7-495c-ae2a-f8d96eb30471
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=213715041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.213715041
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2650405377
Short name T702
Test name
Test status
Simulation time 3673188051 ps
CPU time 32.61 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:52 PM PDT 24
Peak memory 211720 kb
Host smart-20ba771a-97eb-4738-943b-ff229d04a917
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2650405377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2650405377
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3349308040
Short name T111
Test name
Test status
Simulation time 25630293328 ps
CPU time 223.27 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:59:01 PM PDT 24
Peak memory 211716 kb
Host smart-6f573982-89e3-4638-9e45-5227bcc4e0fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3349308040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.3349308040
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1935106261
Short name T471
Test name
Test status
Simulation time 174373720 ps
CPU time 20.49 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:40 PM PDT 24
Peak memory 211696 kb
Host smart-9d565f81-6318-43c3-b1c8-4e56156da684
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1935106261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1935106261
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.1097695103
Short name T833
Test name
Test status
Simulation time 169521967 ps
CPU time 12.3 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:36 PM PDT 24
Peak memory 203516 kb
Host smart-dc6012c2-6f65-48a7-bf36-ca17196e711e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1097695103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1097695103
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.1023869239
Short name T209
Test name
Test status
Simulation time 406106650 ps
CPU time 28.46 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:55:44 PM PDT 24
Peak memory 205064 kb
Host smart-368be6f3-f936-4ead-9df5-62bb71686e6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1023869239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1023869239
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1477957536
Short name T852
Test name
Test status
Simulation time 4531152857 ps
CPU time 28.81 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:55:44 PM PDT 24
Peak memory 204576 kb
Host smart-f41934da-7415-40e1-87ee-db033328c40a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477957536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1477957536
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1223928080
Short name T557
Test name
Test status
Simulation time 60036771336 ps
CPU time 261.2 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 205192 kb
Host smart-ca40b15e-eb6b-428a-8501-664f838d64ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1223928080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1223928080
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.580551035
Short name T315
Test name
Test status
Simulation time 498533038 ps
CPU time 26.12 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:41 PM PDT 24
Peak memory 211680 kb
Host smart-1c5aeea2-ed02-4592-a0d9-ffbe6289397c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580551035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.580551035
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3401921132
Short name T199
Test name
Test status
Simulation time 5202994245 ps
CPU time 23.05 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:42 PM PDT 24
Peak memory 211624 kb
Host smart-04e01c18-594f-433d-ad9f-02f8a6f8bb6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3401921132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3401921132
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.1707859664
Short name T553
Test name
Test status
Simulation time 612194310 ps
CPU time 3.94 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:19 PM PDT 24
Peak memory 203444 kb
Host smart-c9ff2491-d77d-4474-bea4-126a0449aae4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1707859664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1707859664
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3367401757
Short name T609
Test name
Test status
Simulation time 17088444574 ps
CPU time 38.1 seconds
Started Jul 12 05:55:14 PM PDT 24
Finished Jul 12 05:55:54 PM PDT 24
Peak memory 203488 kb
Host smart-415591ae-c3e4-44c7-b8ce-a410c60307aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367401757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3367401757
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2279068276
Short name T569
Test name
Test status
Simulation time 4039753223 ps
CPU time 34.63 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 203540 kb
Host smart-a87a2e32-e822-4b40-abfa-6b9515e7ff6f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2279068276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2279068276
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3561557407
Short name T623
Test name
Test status
Simulation time 33780145 ps
CPU time 2.21 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:25 PM PDT 24
Peak memory 203444 kb
Host smart-91b84fa8-7e85-45f5-ab77-7ecbd3cf1199
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561557407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3561557407
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1535563998
Short name T597
Test name
Test status
Simulation time 7180783085 ps
CPU time 57.37 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:56:17 PM PDT 24
Peak memory 207584 kb
Host smart-aca2fdde-17fd-4af4-8701-13508fc242af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1535563998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1535563998
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1302483158
Short name T893
Test name
Test status
Simulation time 2048234303 ps
CPU time 118.66 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:57:18 PM PDT 24
Peak memory 206484 kb
Host smart-b443147a-1307-4f18-95b7-6943e3294589
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1302483158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1302483158
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.625734293
Short name T711
Test name
Test status
Simulation time 349960092 ps
CPU time 151.37 seconds
Started Jul 12 05:55:15 PM PDT 24
Finished Jul 12 05:57:48 PM PDT 24
Peak memory 209040 kb
Host smart-843df788-0afc-46db-9bd3-0859bddad9f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=625734293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_
reset.625734293
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2575689551
Short name T888
Test name
Test status
Simulation time 134610180 ps
CPU time 46.81 seconds
Started Jul 12 05:55:18 PM PDT 24
Finished Jul 12 05:56:08 PM PDT 24
Peak memory 206772 kb
Host smart-5bcaa85e-6bc0-401c-827b-afa610dd755d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575689551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.2575689551
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.153419454
Short name T230
Test name
Test status
Simulation time 765848018 ps
CPU time 6.04 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:30 PM PDT 24
Peak memory 211688 kb
Host smart-29a4086c-042b-42a9-aee7-1f6d990d1e5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=153419454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.153419454
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3257996679
Short name T387
Test name
Test status
Simulation time 103611859 ps
CPU time 12.54 seconds
Started Jul 12 05:56:52 PM PDT 24
Finished Jul 12 05:57:06 PM PDT 24
Peak memory 211672 kb
Host smart-76e8db1c-6456-4ad8-b1ef-6c55028a6da2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3257996679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3257996679
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3014391843
Short name T366
Test name
Test status
Simulation time 81221870042 ps
CPU time 287.1 seconds
Started Jul 12 05:57:03 PM PDT 24
Finished Jul 12 06:01:51 PM PDT 24
Peak memory 211748 kb
Host smart-c4bb5746-e8c4-4441-bd4e-212156a874fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3014391843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.3014391843
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.712020905
Short name T517
Test name
Test status
Simulation time 1333197958 ps
CPU time 24.02 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 05:57:17 PM PDT 24
Peak memory 203500 kb
Host smart-9605d32e-d63a-4e37-a8d1-e3232f80a17c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=712020905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.712020905
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.1504127133
Short name T425
Test name
Test status
Simulation time 407829308 ps
CPU time 8.45 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 05:57:01 PM PDT 24
Peak memory 203460 kb
Host smart-81204c51-185b-4546-ba8e-1776a12d78f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1504127133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1504127133
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.4214017751
Short name T104
Test name
Test status
Simulation time 370755072 ps
CPU time 5.05 seconds
Started Jul 12 05:56:54 PM PDT 24
Finished Jul 12 05:57:00 PM PDT 24
Peak memory 204044 kb
Host smart-8fca3092-50dd-4a3f-95b6-8ac004c207d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4214017751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.4214017751
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3609412888
Short name T882
Test name
Test status
Simulation time 4828294721 ps
CPU time 29.05 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:34 PM PDT 24
Peak memory 211732 kb
Host smart-bcec6bc0-94b3-4911-920c-8957c0b94364
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609412888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3609412888
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1923847283
Short name T300
Test name
Test status
Simulation time 16697586476 ps
CPU time 83.7 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 211712 kb
Host smart-a28e06a0-f260-48ea-8365-7c11ed180e04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1923847283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1923847283
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.521102745
Short name T642
Test name
Test status
Simulation time 328861244 ps
CPU time 15.73 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:20 PM PDT 24
Peak memory 211660 kb
Host smart-63947633-07f5-4620-9318-47a725c0e089
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521102745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.521102745
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.3494938281
Short name T458
Test name
Test status
Simulation time 2077451457 ps
CPU time 28.54 seconds
Started Jul 12 05:56:53 PM PDT 24
Finished Jul 12 05:57:22 PM PDT 24
Peak memory 203528 kb
Host smart-555a3b0b-a558-4b48-bc9e-2809c0051f53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3494938281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3494938281
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.2977767023
Short name T497
Test name
Test status
Simulation time 28808172 ps
CPU time 2.16 seconds
Started Jul 12 06:04:10 PM PDT 24
Finished Jul 12 06:04:13 PM PDT 24
Peak memory 203452 kb
Host smart-b9408748-e995-4d91-ba28-a74e88b723fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2977767023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2977767023
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.567035469
Short name T798
Test name
Test status
Simulation time 7636969278 ps
CPU time 33.77 seconds
Started Jul 12 05:56:52 PM PDT 24
Finished Jul 12 05:57:27 PM PDT 24
Peak memory 203520 kb
Host smart-684d4098-6516-4e33-a6de-ec8e2f1e58a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=567035469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.567035469
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2683364220
Short name T243
Test name
Test status
Simulation time 4096523304 ps
CPU time 33.91 seconds
Started Jul 12 05:56:50 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 203524 kb
Host smart-dcbe7907-cf78-47e4-9223-da746d3a087d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2683364220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2683364220
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3641802585
Short name T773
Test name
Test status
Simulation time 38753194 ps
CPU time 2.94 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 05:56:56 PM PDT 24
Peak memory 203376 kb
Host smart-9bc8861c-f425-4208-947f-28888a6c6358
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641802585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3641802585
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3832646625
Short name T193
Test name
Test status
Simulation time 905184195 ps
CPU time 85.23 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:58:30 PM PDT 24
Peak memory 209224 kb
Host smart-22654960-9156-4b72-9685-a73cd39df3e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3832646625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3832646625
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1863547409
Short name T837
Test name
Test status
Simulation time 1438167969 ps
CPU time 54.89 seconds
Started Jul 12 05:56:53 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 204672 kb
Host smart-cdfe72b8-f473-4052-af32-f7bf2ae28b2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1863547409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1863547409
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.845535930
Short name T81
Test name
Test status
Simulation time 10885195918 ps
CPU time 300.26 seconds
Started Jul 12 05:57:03 PM PDT 24
Finished Jul 12 06:02:04 PM PDT 24
Peak memory 209936 kb
Host smart-e7cd0edb-41e9-4716-8af0-1e1f1a8ee512
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=845535930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand
_reset.845535930
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.258852127
Short name T378
Test name
Test status
Simulation time 2603972633 ps
CPU time 278.28 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 06:01:31 PM PDT 24
Peak memory 209396 kb
Host smart-9271e8da-4754-45df-9256-6e5bc45a83c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258852127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res
et_error.258852127
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2802561600
Short name T12
Test name
Test status
Simulation time 352042334 ps
CPU time 4.32 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 05:56:57 PM PDT 24
Peak memory 211676 kb
Host smart-a685e9e7-c279-4f04-a343-64d462601004
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2802561600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2802561600
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.885264766
Short name T120
Test name
Test status
Simulation time 8430121960 ps
CPU time 59.84 seconds
Started Jul 12 05:56:56 PM PDT 24
Finished Jul 12 05:57:56 PM PDT 24
Peak memory 204736 kb
Host smart-03fcb4e5-693a-44e9-8e18-98d49d67c0eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=885264766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.885264766
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1418552148
Short name T139
Test name
Test status
Simulation time 5842395630 ps
CPU time 30.71 seconds
Started Jul 12 05:56:57 PM PDT 24
Finished Jul 12 05:57:30 PM PDT 24
Peak memory 203492 kb
Host smart-bc53bcfe-7c2b-451f-a5d3-1aa679977c75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1418552148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1418552148
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3804849316
Short name T314
Test name
Test status
Simulation time 153131935 ps
CPU time 4.04 seconds
Started Jul 12 05:56:57 PM PDT 24
Finished Jul 12 05:57:03 PM PDT 24
Peak memory 203444 kb
Host smart-c903b466-e4e4-432f-8593-8112a02b9fc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3804849316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3804849316
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.2282192567
Short name T403
Test name
Test status
Simulation time 1287029691 ps
CPU time 30.91 seconds
Started Jul 12 05:56:58 PM PDT 24
Finished Jul 12 05:57:31 PM PDT 24
Peak memory 203468 kb
Host smart-9b1c52de-cca1-4871-8363-8eb2c190515d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2282192567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2282192567
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.3300864075
Short name T270
Test name
Test status
Simulation time 259533441 ps
CPU time 25.49 seconds
Started Jul 12 05:56:54 PM PDT 24
Finished Jul 12 05:57:20 PM PDT 24
Peak memory 211648 kb
Host smart-10c7b630-920d-4816-abb4-102835d29b72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3300864075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3300864075
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3833781619
Short name T753
Test name
Test status
Simulation time 97103538067 ps
CPU time 119.51 seconds
Started Jul 12 05:56:56 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 211728 kb
Host smart-c45b9187-f7d1-4fc2-bb79-8fdfda1dc118
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833781619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3833781619
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1420656730
Short name T750
Test name
Test status
Simulation time 29196034565 ps
CPU time 95.87 seconds
Started Jul 12 05:56:57 PM PDT 24
Finished Jul 12 05:58:35 PM PDT 24
Peak memory 211760 kb
Host smart-7cc57a11-bb12-41f0-86d1-8b5beebcb04f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1420656730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1420656730
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1024476529
Short name T428
Test name
Test status
Simulation time 170912966 ps
CPU time 13.27 seconds
Started Jul 12 05:56:58 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 204656 kb
Host smart-69b91007-86f2-43c8-a8b0-5d290839c330
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024476529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1024476529
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.246770460
Short name T251
Test name
Test status
Simulation time 1453934836 ps
CPU time 21.26 seconds
Started Jul 12 05:56:59 PM PDT 24
Finished Jul 12 05:57:21 PM PDT 24
Peak memory 203580 kb
Host smart-503a6c17-79b2-4648-95bb-3f4c4df911bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=246770460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.246770460
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.3884085892
Short name T399
Test name
Test status
Simulation time 647747419 ps
CPU time 3.87 seconds
Started Jul 12 05:56:53 PM PDT 24
Finished Jul 12 05:56:58 PM PDT 24
Peak memory 203480 kb
Host smart-7eb48ebf-fd36-4db7-9807-b7ce8497b039
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3884085892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3884085892
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1996818375
Short name T267
Test name
Test status
Simulation time 5354714911 ps
CPU time 31.55 seconds
Started Jul 12 05:56:51 PM PDT 24
Finished Jul 12 05:57:24 PM PDT 24
Peak memory 203532 kb
Host smart-5e6727ad-d9cf-4d47-af11-546dd8953033
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996818375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1996818375
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1227322456
Short name T707
Test name
Test status
Simulation time 3398486078 ps
CPU time 27.79 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 203316 kb
Host smart-d6168b93-d631-48c4-9e85-899f97959ebe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1227322456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1227322456
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3494306220
Short name T851
Test name
Test status
Simulation time 33030405 ps
CPU time 2.7 seconds
Started Jul 12 05:56:52 PM PDT 24
Finished Jul 12 05:56:56 PM PDT 24
Peak memory 203476 kb
Host smart-3ad67da1-f4b5-4405-af99-ecf9a02fce69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494306220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3494306220
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.25202948
Short name T784
Test name
Test status
Simulation time 3670049313 ps
CPU time 135.48 seconds
Started Jul 12 05:56:56 PM PDT 24
Finished Jul 12 05:59:14 PM PDT 24
Peak memory 208628 kb
Host smart-b5f36930-1dca-4c75-a2a4-b7097d8acb98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25202948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.25202948
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3078701648
Short name T355
Test name
Test status
Simulation time 988183346 ps
CPU time 90.84 seconds
Started Jul 12 05:56:56 PM PDT 24
Finished Jul 12 05:58:30 PM PDT 24
Peak memory 205488 kb
Host smart-51572020-8a6e-42b1-8489-b5d10fe5b8f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3078701648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3078701648
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3326331645
Short name T876
Test name
Test status
Simulation time 380524997 ps
CPU time 185.25 seconds
Started Jul 12 05:56:57 PM PDT 24
Finished Jul 12 06:00:05 PM PDT 24
Peak memory 208344 kb
Host smart-e266840c-6c44-4f47-b3f6-7493966de44d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3326331645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.3326331645
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1690789856
Short name T441
Test name
Test status
Simulation time 7202285 ps
CPU time 9.91 seconds
Started Jul 12 05:56:58 PM PDT 24
Finished Jul 12 05:57:10 PM PDT 24
Peak memory 203608 kb
Host smart-371f19a7-622a-4c49-87e7-4a7e90b732c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690789856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.1690789856
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2275759641
Short name T313
Test name
Test status
Simulation time 48582318 ps
CPU time 6.02 seconds
Started Jul 12 05:56:56 PM PDT 24
Finished Jul 12 05:57:05 PM PDT 24
Peak memory 211652 kb
Host smart-5f3e32da-af3e-4c83-b9d6-9c7823f90c90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2275759641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2275759641
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2942270202
Short name T464
Test name
Test status
Simulation time 271980953 ps
CPU time 11.14 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:16 PM PDT 24
Peak memory 203508 kb
Host smart-1c175542-fb1b-496f-af09-043c517e46c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2942270202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2942270202
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1005945908
Short name T396
Test name
Test status
Simulation time 229860023356 ps
CPU time 447.29 seconds
Started Jul 12 05:57:06 PM PDT 24
Finished Jul 12 06:04:34 PM PDT 24
Peak memory 211676 kb
Host smart-f51afc2d-0d5d-4d86-bb46-de6f3655525e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1005945908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1005945908
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3260594468
Short name T265
Test name
Test status
Simulation time 230014904 ps
CPU time 7.75 seconds
Started Jul 12 05:57:03 PM PDT 24
Finished Jul 12 05:57:11 PM PDT 24
Peak memory 203504 kb
Host smart-5e1ac964-19dd-4d75-bfd3-3de9ace358c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3260594468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3260594468
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.640630881
Short name T846
Test name
Test status
Simulation time 185430732 ps
CPU time 8.66 seconds
Started Jul 12 05:57:07 PM PDT 24
Finished Jul 12 05:57:16 PM PDT 24
Peak memory 203508 kb
Host smart-4a9fe198-e7f5-4414-9190-4a6a0b0d1596
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=640630881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.640630881
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.549215318
Short name T408
Test name
Test status
Simulation time 1214987639 ps
CPU time 23.9 seconds
Started Jul 12 05:57:06 PM PDT 24
Finished Jul 12 05:57:31 PM PDT 24
Peak memory 211648 kb
Host smart-66f9b2ce-f8c8-4da2-8589-05e0bc63ade2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=549215318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.549215318
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2481262777
Short name T52
Test name
Test status
Simulation time 3433795826 ps
CPU time 19.74 seconds
Started Jul 12 05:57:06 PM PDT 24
Finished Jul 12 05:57:27 PM PDT 24
Peak memory 203508 kb
Host smart-9866ee68-a218-47fb-b8d6-71013882bfab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481262777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2481262777
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3807064748
Short name T760
Test name
Test status
Simulation time 9024178409 ps
CPU time 52.2 seconds
Started Jul 12 05:57:06 PM PDT 24
Finished Jul 12 05:57:59 PM PDT 24
Peak memory 211700 kb
Host smart-46c6522a-122e-479f-b352-65924065ed35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3807064748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3807064748
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1901143246
Short name T503
Test name
Test status
Simulation time 458200759 ps
CPU time 24.94 seconds
Started Jul 12 05:57:07 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 211644 kb
Host smart-88e394f4-2c06-4eea-a980-5f4b109c336c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901143246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1901143246
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.190732579
Short name T602
Test name
Test status
Simulation time 2643551388 ps
CPU time 11.04 seconds
Started Jul 12 05:57:11 PM PDT 24
Finished Jul 12 05:57:24 PM PDT 24
Peak memory 204060 kb
Host smart-64de5a60-97e9-46b2-aeee-28580d49f5f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=190732579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.190732579
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.3934377162
Short name T803
Test name
Test status
Simulation time 372946552 ps
CPU time 3.17 seconds
Started Jul 12 05:56:58 PM PDT 24
Finished Jul 12 05:57:03 PM PDT 24
Peak memory 203476 kb
Host smart-1c7b443c-79d0-4ffa-baab-27cb44a90957
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934377162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3934377162
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3989922437
Short name T262
Test name
Test status
Simulation time 6966252835 ps
CPU time 28.25 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 203536 kb
Host smart-b9e26e08-f39b-443a-886c-0986f90357c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989922437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3989922437
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1788808239
Short name T6
Test name
Test status
Simulation time 3704925731 ps
CPU time 34.75 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:40 PM PDT 24
Peak memory 203492 kb
Host smart-a642ea59-5e21-44b6-a6f1-93ac02e668a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1788808239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1788808239
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.202446148
Short name T824
Test name
Test status
Simulation time 67838408 ps
CPU time 2.43 seconds
Started Jul 12 05:56:56 PM PDT 24
Finished Jul 12 05:57:01 PM PDT 24
Peak memory 203440 kb
Host smart-98231c3a-3117-413a-b60b-2a660fbc576d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202446148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.202446148
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1267933351
Short name T194
Test name
Test status
Simulation time 357291004 ps
CPU time 43.7 seconds
Started Jul 12 05:57:02 PM PDT 24
Finished Jul 12 05:57:47 PM PDT 24
Peak memory 205588 kb
Host smart-821e0cdf-4b38-4b74-9d02-53a4936f300b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1267933351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1267933351
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.333008935
Short name T372
Test name
Test status
Simulation time 5703996552 ps
CPU time 132.57 seconds
Started Jul 12 05:57:03 PM PDT 24
Finished Jul 12 05:59:16 PM PDT 24
Peak memory 209220 kb
Host smart-5a8bdc30-0cc2-4037-9962-36ff302891a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=333008935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.333008935
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3590331199
Short name T650
Test name
Test status
Simulation time 2056160957 ps
CPU time 397.62 seconds
Started Jul 12 05:57:06 PM PDT 24
Finished Jul 12 06:03:44 PM PDT 24
Peak memory 209356 kb
Host smart-99768f9c-2f3d-4b3b-81e5-225d073ce799
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3590331199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.3590331199
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2317085913
Short name T35
Test name
Test status
Simulation time 2830829067 ps
CPU time 178.76 seconds
Started Jul 12 05:57:07 PM PDT 24
Finished Jul 12 06:00:06 PM PDT 24
Peak memory 211692 kb
Host smart-fe9f15e1-b5a4-4b12-939d-97d364735323
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2317085913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2317085913
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1489307923
Short name T550
Test name
Test status
Simulation time 45834213 ps
CPU time 3.24 seconds
Started Jul 12 05:57:05 PM PDT 24
Finished Jul 12 05:57:09 PM PDT 24
Peak memory 211616 kb
Host smart-dfb9b3bc-691a-4f6e-9103-a081b7e28c52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1489307923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1489307923
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3595568241
Short name T268
Test name
Test status
Simulation time 117512260 ps
CPU time 16.51 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:37 PM PDT 24
Peak memory 205452 kb
Host smart-2dd34663-a5f9-4dab-a4a5-97d004f20e37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3595568241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3595568241
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3978220446
Short name T435
Test name
Test status
Simulation time 180065044 ps
CPU time 6.47 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:57:16 PM PDT 24
Peak memory 203596 kb
Host smart-0fa19093-edf0-437c-8ed0-c84c6b9504f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3978220446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3978220446
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.1110157034
Short name T618
Test name
Test status
Simulation time 1355548326 ps
CPU time 27.89 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 05:57:37 PM PDT 24
Peak memory 203504 kb
Host smart-4260e2ff-08a2-4852-ae1f-eb4d8b492b2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1110157034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1110157034
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.4011234654
Short name T3
Test name
Test status
Simulation time 5201040842 ps
CPU time 28.77 seconds
Started Jul 12 05:57:05 PM PDT 24
Finished Jul 12 05:57:34 PM PDT 24
Peak memory 204796 kb
Host smart-5875242b-5b52-45c2-9e6e-760621789567
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4011234654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4011234654
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.4263127078
Short name T788
Test name
Test status
Simulation time 28113639376 ps
CPU time 129.05 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 05:59:18 PM PDT 24
Peak memory 204988 kb
Host smart-9384e44e-2246-4bbb-912f-5859f8d4d666
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263127078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4263127078
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2513380265
Short name T455
Test name
Test status
Simulation time 35256962551 ps
CPU time 186.24 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 06:00:15 PM PDT 24
Peak memory 211696 kb
Host smart-578e34e2-b6ad-409c-8db5-8ff05eff8fc9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2513380265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2513380265
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2898818009
Short name T342
Test name
Test status
Simulation time 115186352 ps
CPU time 11.59 seconds
Started Jul 12 05:57:02 PM PDT 24
Finished Jul 12 05:57:14 PM PDT 24
Peak memory 211640 kb
Host smart-fad0615b-4b08-4faa-aeb2-1b99d6e071da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898818009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2898818009
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1204281983
Short name T649
Test name
Test status
Simulation time 186025752 ps
CPU time 4.21 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 203512 kb
Host smart-50691cc2-d7b2-41eb-a046-138b7799c37e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204281983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1204281983
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.2843570155
Short name T99
Test name
Test status
Simulation time 525493505 ps
CPU time 4.14 seconds
Started Jul 12 05:57:04 PM PDT 24
Finished Jul 12 05:57:09 PM PDT 24
Peak memory 203480 kb
Host smart-63d70e10-113c-41a1-af33-4e1cc9e7ad3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2843570155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2843570155
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2965202743
Short name T56
Test name
Test status
Simulation time 16939086204 ps
CPU time 28.28 seconds
Started Jul 12 05:57:07 PM PDT 24
Finished Jul 12 05:57:36 PM PDT 24
Peak memory 203484 kb
Host smart-d1353305-7c66-44aa-a695-ffc2d7050300
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965202743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2965202743
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.972407545
Short name T662
Test name
Test status
Simulation time 2399272473 ps
CPU time 19.82 seconds
Started Jul 12 05:57:06 PM PDT 24
Finished Jul 12 05:57:26 PM PDT 24
Peak memory 203528 kb
Host smart-8b0908a5-7473-45b9-9975-bac79459a90c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=972407545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.972407545
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1469206597
Short name T593
Test name
Test status
Simulation time 25553870 ps
CPU time 2.06 seconds
Started Jul 12 05:57:05 PM PDT 24
Finished Jul 12 05:57:08 PM PDT 24
Peak memory 203488 kb
Host smart-5e65e032-b0b5-40e3-aa69-2bb967564f22
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469206597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1469206597
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2428698513
Short name T856
Test name
Test status
Simulation time 1050490251 ps
CPU time 32.3 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:57:43 PM PDT 24
Peak memory 206008 kb
Host smart-ad35ebd9-396b-4f35-a8b5-327b0bbfc20d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2428698513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2428698513
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3684223627
Short name T889
Test name
Test status
Simulation time 178009900 ps
CPU time 39.88 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 206972 kb
Host smart-77f9b6a0-3d08-4065-bb36-283fecc1edbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3684223627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3684223627
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.141801416
Short name T473
Test name
Test status
Simulation time 2305010297 ps
CPU time 172.82 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 06:00:02 PM PDT 24
Peak memory 210832 kb
Host smart-20d9149b-46ec-4e2f-b6cd-9e7a95c59626
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=141801416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res
et_error.141801416
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3237541256
Short name T266
Test name
Test status
Simulation time 649663357 ps
CPU time 12.51 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 211476 kb
Host smart-ca90cfe4-7dfc-4cbe-875c-7ad2805a0baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3237541256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3237541256
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3313509785
Short name T467
Test name
Test status
Simulation time 2247885086 ps
CPU time 46.92 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:57:58 PM PDT 24
Peak memory 211744 kb
Host smart-f1da1eec-6397-41ec-8641-37c901068d73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313509785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3313509785
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4287864754
Short name T487
Test name
Test status
Simulation time 66834755707 ps
CPU time 148.82 seconds
Started Jul 12 05:57:17 PM PDT 24
Finished Jul 12 05:59:49 PM PDT 24
Peak memory 204916 kb
Host smart-810b2326-fbb0-471f-a6bf-df83cc56474e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4287864754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.4287864754
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1189455878
Short name T684
Test name
Test status
Simulation time 30582796 ps
CPU time 2.82 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:57:14 PM PDT 24
Peak memory 203524 kb
Host smart-70c8abf2-c843-4514-827b-3ef045a728c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1189455878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1189455878
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.3181382702
Short name T278
Test name
Test status
Simulation time 145540007 ps
CPU time 10.48 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:57:22 PM PDT 24
Peak memory 203500 kb
Host smart-7b8caea5-864d-4ce5-92ac-ef680da721c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3181382702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3181382702
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.3039204025
Short name T490
Test name
Test status
Simulation time 86006928 ps
CPU time 8.08 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:57:20 PM PDT 24
Peak memory 204580 kb
Host smart-ca072813-b0f0-4fdd-adfc-a85ce24cc994
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3039204025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3039204025
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1186297313
Short name T759
Test name
Test status
Simulation time 22835118534 ps
CPU time 123.39 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 05:59:13 PM PDT 24
Peak memory 205200 kb
Host smart-6b5972b2-41a8-4080-b4bc-92145a3341a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186297313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1186297313
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1721419302
Short name T601
Test name
Test status
Simulation time 23546393474 ps
CPU time 155.73 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:59:46 PM PDT 24
Peak memory 211728 kb
Host smart-aeb25216-bf23-47e6-abbf-48db9a131c10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1721419302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1721419302
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1448269915
Short name T599
Test name
Test status
Simulation time 26328694 ps
CPU time 3.58 seconds
Started Jul 12 05:57:11 PM PDT 24
Finished Jul 12 05:57:16 PM PDT 24
Peak memory 203448 kb
Host smart-b15035d1-c68c-4713-9948-0e7ba9583fae
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448269915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1448269915
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.2059501199
Short name T614
Test name
Test status
Simulation time 2709218710 ps
CPU time 33.77 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:57:45 PM PDT 24
Peak memory 204044 kb
Host smart-a6f7eeee-e137-4858-921d-a206b8fd6c8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2059501199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2059501199
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.2389953511
Short name T636
Test name
Test status
Simulation time 244691915 ps
CPU time 3.89 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 203444 kb
Host smart-d422dbae-52ae-43d8-9b4d-0b56f343d4f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2389953511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2389953511
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.93782152
Short name T339
Test name
Test status
Simulation time 7828412997 ps
CPU time 32.96 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:57:45 PM PDT 24
Peak memory 203524 kb
Host smart-bdbf7bdf-854c-4e04-911f-c658af2d1d16
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=93782152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.93782152
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2796906324
Short name T324
Test name
Test status
Simulation time 5029577611 ps
CPU time 28.03 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:57:39 PM PDT 24
Peak memory 203484 kb
Host smart-09815a17-188d-4528-955d-8c519e5d2a08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2796906324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2796906324
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.242357001
Short name T819
Test name
Test status
Simulation time 29154221 ps
CPU time 2.35 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 203484 kb
Host smart-c527875c-8548-49cb-b71e-ea3908c25b0e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242357001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.242357001
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3037201784
Short name T628
Test name
Test status
Simulation time 364872263 ps
CPU time 57.06 seconds
Started Jul 12 05:57:10 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 206468 kb
Host smart-bd213576-3e11-4791-adba-e9312c80f175
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037201784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3037201784
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3277857260
Short name T638
Test name
Test status
Simulation time 1161310973 ps
CPU time 121.97 seconds
Started Jul 12 05:57:08 PM PDT 24
Finished Jul 12 05:59:10 PM PDT 24
Peak memory 207976 kb
Host smart-c644aaff-5cb0-49f1-b9d5-d3f36aef0731
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3277857260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3277857260
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.4153833391
Short name T26
Test name
Test status
Simulation time 308124689 ps
CPU time 96.3 seconds
Started Jul 12 05:57:07 PM PDT 24
Finished Jul 12 05:58:44 PM PDT 24
Peak memory 208280 kb
Host smart-e86adf15-1e13-40b4-a4c8-8fa8fe700a07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4153833391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.4153833391
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1403439166
Short name T259
Test name
Test status
Simulation time 616390060 ps
CPU time 109.81 seconds
Started Jul 12 05:57:11 PM PDT 24
Finished Jul 12 05:59:02 PM PDT 24
Peak memory 209064 kb
Host smart-2d973366-932d-4d41-aac8-6dee455f96c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1403439166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1403439166
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3613366710
Short name T567
Test name
Test status
Simulation time 126499047 ps
CPU time 16.59 seconds
Started Jul 12 05:57:11 PM PDT 24
Finished Jul 12 05:57:29 PM PDT 24
Peak memory 211668 kb
Host smart-1150b5de-1d0b-4475-a526-91b943135c79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3613366710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3613366710
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2993305341
Short name T419
Test name
Test status
Simulation time 2125286143 ps
CPU time 56.55 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:58:12 PM PDT 24
Peak memory 211624 kb
Host smart-06b8c91e-b94b-4358-a452-7fc2d2cf4397
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2993305341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2993305341
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1563289306
Short name T821
Test name
Test status
Simulation time 281006853731 ps
CPU time 753.7 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 06:09:50 PM PDT 24
Peak memory 211680 kb
Host smart-2df5f50f-5575-463f-898e-7a07601fe993
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1563289306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1563289306
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.341974822
Short name T631
Test name
Test status
Simulation time 477718864 ps
CPU time 18.94 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:57:35 PM PDT 24
Peak memory 203512 kb
Host smart-ba432f4d-66c7-4ace-8b40-8545580f7384
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=341974822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.341974822
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3447004676
Short name T704
Test name
Test status
Simulation time 159088141 ps
CPU time 14.65 seconds
Started Jul 12 05:57:25 PM PDT 24
Finished Jul 12 05:57:52 PM PDT 24
Peak memory 203324 kb
Host smart-2489e85a-5a91-4398-9f4e-5d56d318bbfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3447004676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3447004676
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.1452048030
Short name T180
Test name
Test status
Simulation time 83398686 ps
CPU time 8.81 seconds
Started Jul 12 05:57:25 PM PDT 24
Finished Jul 12 05:57:46 PM PDT 24
Peak memory 211484 kb
Host smart-5eff4115-86da-44ca-82e9-ebacd9fe9f34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1452048030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1452048030
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.145290320
Short name T498
Test name
Test status
Simulation time 27325396135 ps
CPU time 131.94 seconds
Started Jul 12 05:57:12 PM PDT 24
Finished Jul 12 05:59:26 PM PDT 24
Peak memory 211728 kb
Host smart-48a297a2-6510-4322-a50e-44d3f7ce400c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=145290320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.145290320
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3504609694
Short name T282
Test name
Test status
Simulation time 24179670039 ps
CPU time 77.86 seconds
Started Jul 12 05:57:15 PM PDT 24
Finished Jul 12 05:58:35 PM PDT 24
Peak memory 211704 kb
Host smart-f09f0171-a56f-4836-bf5d-d02b4981bd29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3504609694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3504609694
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1560419805
Short name T365
Test name
Test status
Simulation time 65978117 ps
CPU time 2.01 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:57:38 PM PDT 24
Peak memory 203228 kb
Host smart-9ccf8033-e52b-42a4-bcbc-bb77d9a4200f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560419805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1560419805
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.2475285461
Short name T412
Test name
Test status
Simulation time 2889071670 ps
CPU time 22.55 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:57:38 PM PDT 24
Peak memory 203600 kb
Host smart-c1e84b6f-fd25-49cf-8449-bd6edff1ef88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2475285461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2475285461
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.1537944044
Short name T705
Test name
Test status
Simulation time 142731558 ps
CPU time 3.61 seconds
Started Jul 12 05:57:09 PM PDT 24
Finished Jul 12 05:57:15 PM PDT 24
Peak memory 203460 kb
Host smart-0dad9caf-470a-4258-851a-b23abc7af894
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1537944044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1537944044
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1597587114
Short name T872
Test name
Test status
Simulation time 14402190596 ps
CPU time 36.4 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:57:52 PM PDT 24
Peak memory 203536 kb
Host smart-19c88497-049e-4482-be0e-8ce1f3588c4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597587114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1597587114
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1610674549
Short name T175
Test name
Test status
Simulation time 21768326478 ps
CPU time 37.65 seconds
Started Jul 12 05:57:14 PM PDT 24
Finished Jul 12 05:57:54 PM PDT 24
Peak memory 203484 kb
Host smart-85c36690-de84-4d4e-9394-fd76a0744280
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1610674549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1610674549
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1021284954
Short name T624
Test name
Test status
Simulation time 23689737 ps
CPU time 2.01 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:57:18 PM PDT 24
Peak memory 203420 kb
Host smart-fd2f73db-168c-4c47-a366-03822709e43b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021284954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1021284954
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.4016694474
Short name T693
Test name
Test status
Simulation time 15478641838 ps
CPU time 172.08 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 06:00:28 PM PDT 24
Peak memory 211564 kb
Host smart-7cebc2b5-7338-46e0-8770-05067da0c72b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4016694474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4016694474
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.834480913
Short name T500
Test name
Test status
Simulation time 2509609477 ps
CPU time 49.64 seconds
Started Jul 12 05:57:12 PM PDT 24
Finished Jul 12 05:58:03 PM PDT 24
Peak memory 204560 kb
Host smart-9598e2fc-a29b-4298-b625-b99586723ce4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=834480913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.834480913
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.293183418
Short name T23
Test name
Test status
Simulation time 1884544418 ps
CPU time 366.95 seconds
Started Jul 12 05:57:12 PM PDT 24
Finished Jul 12 06:03:22 PM PDT 24
Peak memory 209704 kb
Host smart-11491600-fe73-4c16-a7fa-baac8a8469d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=293183418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand
_reset.293183418
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.77442707
Short name T659
Test name
Test status
Simulation time 265583499 ps
CPU time 75.69 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:58:31 PM PDT 24
Peak memory 207428 kb
Host smart-4a755b7f-cd7f-4dd7-94b6-b6232c75d1cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77442707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rese
t_error.77442707
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1450712106
Short name T658
Test name
Test status
Simulation time 576601868 ps
CPU time 23.11 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:44 PM PDT 24
Peak memory 211648 kb
Host smart-f2220206-ddc3-47f8-8525-61ccbf810c27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1450712106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1450712106
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2077996463
Short name T103
Test name
Test status
Simulation time 449434576 ps
CPU time 40.27 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 05:58:04 PM PDT 24
Peak memory 211688 kb
Host smart-0580b389-51a2-41f1-a77a-5ca52cda3b96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2077996463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2077996463
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.769991620
Short name T561
Test name
Test status
Simulation time 180075117750 ps
CPU time 329.85 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 06:02:55 PM PDT 24
Peak memory 211636 kb
Host smart-6f90782c-f8a1-49d3-a4ec-a06cd362015c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=769991620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo
w_rsp.769991620
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2204506372
Short name T698
Test name
Test status
Simulation time 185363471 ps
CPU time 16.94 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 05:57:44 PM PDT 24
Peak memory 203492 kb
Host smart-74de0630-aa12-4262-b309-0859fd549303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2204506372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2204506372
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.402689710
Short name T237
Test name
Test status
Simulation time 415030325 ps
CPU time 13.06 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:34 PM PDT 24
Peak memory 203500 kb
Host smart-af1528a9-768d-464d-9816-2fb76eb0c611
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=402689710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.402689710
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.999006106
Short name T752
Test name
Test status
Simulation time 1064461418 ps
CPU time 26.47 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 05:58:11 PM PDT 24
Peak memory 211476 kb
Host smart-1f067e10-cdab-4e85-9d1d-7967d9c0da64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=999006106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.999006106
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3084867907
Short name T617
Test name
Test status
Simulation time 38778844350 ps
CPU time 230.24 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 06:01:12 PM PDT 24
Peak memory 211748 kb
Host smart-aeb9b336-cc92-4046-b077-3e9ca2913ca2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084867907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3084867907
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1124309996
Short name T119
Test name
Test status
Simulation time 38793002833 ps
CPU time 278.54 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 06:02:02 PM PDT 24
Peak memory 211728 kb
Host smart-328cd075-74e3-469d-a134-f5578a340636
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1124309996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1124309996
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1212557073
Short name T667
Test name
Test status
Simulation time 195991818 ps
CPU time 25.15 seconds
Started Jul 12 05:57:22 PM PDT 24
Finished Jul 12 05:57:57 PM PDT 24
Peak memory 211676 kb
Host smart-b26b841e-3062-4532-90b3-637122a0c79d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212557073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1212557073
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.411603170
Short name T263
Test name
Test status
Simulation time 262728890 ps
CPU time 10.4 seconds
Started Jul 12 05:57:22 PM PDT 24
Finished Jul 12 05:57:41 PM PDT 24
Peak memory 204032 kb
Host smart-a5129e24-1db4-49b1-b160-166aef68e9df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=411603170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.411603170
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.11891748
Short name T131
Test name
Test status
Simulation time 44621039 ps
CPU time 2.48 seconds
Started Jul 12 05:57:13 PM PDT 24
Finished Jul 12 05:57:18 PM PDT 24
Peak memory 203456 kb
Host smart-1c860b94-46f0-4f12-910d-9cff6ee70e15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11891748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.11891748
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3045063824
Short name T66
Test name
Test status
Simulation time 9604881669 ps
CPU time 33.78 seconds
Started Jul 12 05:57:14 PM PDT 24
Finished Jul 12 05:57:51 PM PDT 24
Peak memory 203544 kb
Host smart-fe246a4b-1e96-4b4d-8632-0c56891a4ab4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045063824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3045063824
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3904852046
Short name T433
Test name
Test status
Simulation time 10546137648 ps
CPU time 33.55 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 203280 kb
Host smart-fed8cf24-425a-4084-9819-2a3315d30f4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3904852046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3904852046
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2248077888
Short name T246
Test name
Test status
Simulation time 37413495 ps
CPU time 2.47 seconds
Started Jul 12 05:57:12 PM PDT 24
Finished Jul 12 05:57:17 PM PDT 24
Peak memory 203488 kb
Host smart-969715e4-0e4c-4042-87c8-a0a51a7f5a75
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248077888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2248077888
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.1033355675
Short name T116
Test name
Test status
Simulation time 7181886891 ps
CPU time 253.42 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 06:01:40 PM PDT 24
Peak memory 209792 kb
Host smart-038c9957-951f-4101-aa25-1b5b17613620
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1033355675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1033355675
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1015347525
Short name T452
Test name
Test status
Simulation time 21060269070 ps
CPU time 136.64 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 05:59:40 PM PDT 24
Peak memory 206496 kb
Host smart-5abf8446-3652-446b-8c29-02b4076e95c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1015347525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1015347525
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2465028780
Short name T820
Test name
Test status
Simulation time 559642315 ps
CPU time 98 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 05:59:01 PM PDT 24
Peak memory 208220 kb
Host smart-9a124377-c62d-46b7-b825-86885165f116
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2465028780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.2465028780
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2790708969
Short name T758
Test name
Test status
Simulation time 804957871 ps
CPU time 205.22 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 06:00:51 PM PDT 24
Peak memory 219852 kb
Host smart-e4ae27c1-21a5-4c03-9d65-4282f1f97d89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2790708969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.2790708969
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1002682388
Short name T462
Test name
Test status
Simulation time 292152679 ps
CPU time 15.38 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 05:57:38 PM PDT 24
Peak memory 211688 kb
Host smart-8d205962-9cd3-460c-b513-e624538a70c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1002682388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1002682388
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.4177375996
Short name T172
Test name
Test status
Simulation time 878665479 ps
CPU time 44.06 seconds
Started Jul 12 05:57:22 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 211664 kb
Host smart-1314def4-f43e-470e-b211-ba9fdcf53334
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4177375996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.4177375996
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1685762631
Short name T878
Test name
Test status
Simulation time 4183761869 ps
CPU time 32.01 seconds
Started Jul 12 05:57:19 PM PDT 24
Finished Jul 12 05:57:56 PM PDT 24
Peak memory 203536 kb
Host smart-1d441422-363f-4c01-b26f-8b63c5f98a2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1685762631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1685762631
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1144992430
Short name T409
Test name
Test status
Simulation time 921044484 ps
CPU time 30.18 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 203412 kb
Host smart-76f3fef4-1df9-4996-82b1-d8a666fc7bd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1144992430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1144992430
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.2164961058
Short name T692
Test name
Test status
Simulation time 40546150 ps
CPU time 4.04 seconds
Started Jul 12 05:57:21 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 203496 kb
Host smart-2111b367-e03b-4e12-8263-a8dbc8a051cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2164961058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2164961058
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.443526440
Short name T656
Test name
Test status
Simulation time 179786092 ps
CPU time 21.59 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 211616 kb
Host smart-a887824e-20a1-4cb7-85f3-8db678730e98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=443526440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.443526440
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1733987256
Short name T308
Test name
Test status
Simulation time 13322043596 ps
CPU time 20.93 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 05:57:46 PM PDT 24
Peak memory 203528 kb
Host smart-feb001e0-07ce-48c4-bb0d-01406a8d0ff6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733987256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1733987256
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1512125324
Short name T822
Test name
Test status
Simulation time 94235862679 ps
CPU time 212.04 seconds
Started Jul 12 05:57:21 PM PDT 24
Finished Jul 12 06:01:01 PM PDT 24
Peak memory 211736 kb
Host smart-999e540b-4110-4949-afa3-3fd4f4936121
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1512125324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1512125324
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.371465603
Short name T598
Test name
Test status
Simulation time 140948293 ps
CPU time 18.38 seconds
Started Jul 12 05:57:21 PM PDT 24
Finished Jul 12 05:57:46 PM PDT 24
Peak memory 204492 kb
Host smart-affde864-b798-4305-84db-49b0da70fa43
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371465603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.371465603
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3903304795
Short name T133
Test name
Test status
Simulation time 986367085 ps
CPU time 19.78 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:42 PM PDT 24
Peak memory 203544 kb
Host smart-b7a0ff2d-0115-467a-8435-2e000582582e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3903304795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3903304795
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.4030090636
Short name T489
Test name
Test status
Simulation time 351451433 ps
CPU time 3.8 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 203460 kb
Host smart-49bcdbe4-75a8-41b3-996f-dc4e43d4538e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4030090636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.4030090636
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2631070329
Short name T393
Test name
Test status
Simulation time 9830626103 ps
CPU time 23.35 seconds
Started Jul 12 05:57:21 PM PDT 24
Finished Jul 12 05:57:51 PM PDT 24
Peak memory 203508 kb
Host smart-c7d171a3-6d89-4f16-a032-0680ce0d6980
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631070329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2631070329
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.258973737
Short name T211
Test name
Test status
Simulation time 19870836578 ps
CPU time 36.17 seconds
Started Jul 12 05:57:18 PM PDT 24
Finished Jul 12 05:57:57 PM PDT 24
Peak memory 203488 kb
Host smart-b4d7a895-38b3-4700-b175-70b8c7dc9712
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=258973737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.258973737
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2269444816
Short name T97
Test name
Test status
Simulation time 45528807 ps
CPU time 2.17 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 05:57:27 PM PDT 24
Peak memory 203464 kb
Host smart-804764c7-6a0b-433b-9deb-5cf5c0b76291
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269444816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2269444816
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.2387924642
Short name T364
Test name
Test status
Simulation time 2285980907 ps
CPU time 44.45 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:58:23 PM PDT 24
Peak memory 205568 kb
Host smart-53d52bd7-1114-4494-921d-adcf670bccab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2387924642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2387924642
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1648599804
Short name T177
Test name
Test status
Simulation time 1763003218 ps
CPU time 167.91 seconds
Started Jul 12 05:57:25 PM PDT 24
Finished Jul 12 06:00:25 PM PDT 24
Peak memory 205932 kb
Host smart-f9922aeb-05fa-44f4-87ed-efd5354755c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1648599804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1648599804
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.315830178
Short name T79
Test name
Test status
Simulation time 1729571475 ps
CPU time 134.5 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:59:53 PM PDT 24
Peak memory 208864 kb
Host smart-99933153-4572-40e7-9cd9-85e164bfe0b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=315830178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand
_reset.315830178
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4172993441
Short name T64
Test name
Test status
Simulation time 842483842 ps
CPU time 21.92 seconds
Started Jul 12 05:57:20 PM PDT 24
Finished Jul 12 05:57:48 PM PDT 24
Peak memory 211660 kb
Host smart-0fcc19e0-e27e-4e2c-85ae-a31c75fb43f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4172993441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4172993441
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3820265451
Short name T515
Test name
Test status
Simulation time 148413028 ps
CPU time 17.25 seconds
Started Jul 12 05:57:27 PM PDT 24
Finished Jul 12 05:57:57 PM PDT 24
Peak memory 211684 kb
Host smart-ab66fa2c-70eb-4459-8bc7-b706c18cf603
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3820265451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3820265451
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3337483415
Short name T894
Test name
Test status
Simulation time 34232714085 ps
CPU time 98.05 seconds
Started Jul 12 05:57:23 PM PDT 24
Finished Jul 12 05:59:11 PM PDT 24
Peak memory 211744 kb
Host smart-a09d9a2f-6101-4f38-b666-f2c0b7106f0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3337483415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3337483415
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.375977533
Short name T481
Test name
Test status
Simulation time 853681881 ps
CPU time 10.26 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 203500 kb
Host smart-3e46bd5d-bc71-4433-96c6-5810a9e74d72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=375977533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.375977533
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3365365273
Short name T694
Test name
Test status
Simulation time 4635280733 ps
CPU time 30.86 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:58:10 PM PDT 24
Peak memory 203480 kb
Host smart-ac754684-3f0d-406d-b3a8-7ff06f24c47b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3365365273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3365365273
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.40198761
Short name T778
Test name
Test status
Simulation time 883408298 ps
CPU time 20.08 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:57:56 PM PDT 24
Peak memory 204792 kb
Host smart-92feb679-ba99-47f8-aab3-cbcfb38ea6fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40198761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.40198761
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1015780431
Short name T741
Test name
Test status
Simulation time 35185682809 ps
CPU time 71.75 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 05:58:56 PM PDT 24
Peak memory 204736 kb
Host smart-f82d520f-9e9d-4889-9a90-efa5e881f1e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015780431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1015780431
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.974703230
Short name T507
Test name
Test status
Simulation time 11332731670 ps
CPU time 45.89 seconds
Started Jul 12 05:57:23 PM PDT 24
Finished Jul 12 05:58:19 PM PDT 24
Peak memory 211680 kb
Host smart-de42b9ee-1ff8-4948-a09d-09ff2200a460
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=974703230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.974703230
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2242034350
Short name T345
Test name
Test status
Simulation time 725129457 ps
CPU time 27.59 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:58:06 PM PDT 24
Peak memory 211676 kb
Host smart-df8bf199-d0da-4387-8e07-63bb247fc2ed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242034350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2242034350
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.1749608610
Short name T16
Test name
Test status
Simulation time 253782182 ps
CPU time 15.85 seconds
Started Jul 12 05:57:28 PM PDT 24
Finished Jul 12 05:57:57 PM PDT 24
Peak memory 203536 kb
Host smart-153a3aa1-c814-446e-bf5d-b918490698a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1749608610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1749608610
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.3671123414
Short name T379
Test name
Test status
Simulation time 26140955 ps
CPU time 2.29 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:57:36 PM PDT 24
Peak memory 203480 kb
Host smart-75304589-5abd-4fba-ac26-3475fce58eb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3671123414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3671123414
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2820604411
Short name T512
Test name
Test status
Simulation time 5723913366 ps
CPU time 34.87 seconds
Started Jul 12 05:57:27 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 203456 kb
Host smart-51a40010-75e6-4767-ba3e-93726c51e417
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820604411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2820604411
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.367186585
Short name T863
Test name
Test status
Simulation time 3346824334 ps
CPU time 23.91 seconds
Started Jul 12 05:57:26 PM PDT 24
Finished Jul 12 05:58:02 PM PDT 24
Peak memory 203544 kb
Host smart-a5129f6c-d0fd-4083-93b8-1b786d84b4d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=367186585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.367186585
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1920332889
Short name T739
Test name
Test status
Simulation time 36112376 ps
CPU time 2.1 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:57:38 PM PDT 24
Peak memory 203468 kb
Host smart-90b26a57-a8fc-428a-844f-572fddd69b78
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920332889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1920332889
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.468091143
Short name T129
Test name
Test status
Simulation time 16624348263 ps
CPU time 332.41 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 06:03:16 PM PDT 24
Peak memory 207520 kb
Host smart-6878352a-7007-4df1-8ec0-e136b5c36e5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=468091143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.468091143
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3997562733
Short name T463
Test name
Test status
Simulation time 1688699704 ps
CPU time 117.14 seconds
Started Jul 12 05:57:32 PM PDT 24
Finished Jul 12 05:59:43 PM PDT 24
Peak memory 205528 kb
Host smart-95865243-5c8a-4906-9097-60bfc471daba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3997562733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3997562733
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2478260298
Short name T442
Test name
Test status
Simulation time 1790567327 ps
CPU time 355.84 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 06:03:40 PM PDT 24
Peak memory 211688 kb
Host smart-241b8fd9-af19-4300-8c0a-7a348c30b398
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2478260298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2478260298
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3049194769
Short name T257
Test name
Test status
Simulation time 466182779 ps
CPU time 108.8 seconds
Started Jul 12 05:57:29 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 209728 kb
Host smart-ee671ba6-9fc7-4a17-95cf-c0df80d42234
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3049194769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3049194769
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3678746615
Short name T855
Test name
Test status
Simulation time 85397856 ps
CPU time 4.06 seconds
Started Jul 12 05:57:24 PM PDT 24
Finished Jul 12 05:57:39 PM PDT 24
Peak memory 211636 kb
Host smart-09a266be-2504-4a28-a7db-6a27d7f3dfda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3678746615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3678746615
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.171083118
Short name T160
Test name
Test status
Simulation time 478296915 ps
CPU time 32.44 seconds
Started Jul 12 05:57:32 PM PDT 24
Finished Jul 12 05:58:18 PM PDT 24
Peak memory 211668 kb
Host smart-28aea620-eeee-4917-869c-bb0fe0ce24de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=171083118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.171083118
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.872477151
Short name T150
Test name
Test status
Simulation time 29267445345 ps
CPU time 202.48 seconds
Started Jul 12 05:57:29 PM PDT 24
Finished Jul 12 06:01:05 PM PDT 24
Peak memory 211744 kb
Host smart-2fb8e55e-df9a-4ec8-9ec4-c36738cf5f10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=872477151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.872477151
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3287874602
Short name T206
Test name
Test status
Simulation time 1356390881 ps
CPU time 8.97 seconds
Started Jul 12 05:57:32 PM PDT 24
Finished Jul 12 05:57:55 PM PDT 24
Peak memory 203464 kb
Host smart-3fadf7df-4417-4883-9ef2-867c28f73337
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3287874602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3287874602
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.95464923
Short name T559
Test name
Test status
Simulation time 165213225 ps
CPU time 11.46 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 05:58:00 PM PDT 24
Peak memory 203516 kb
Host smart-fbf98773-d48a-4bc2-bc3e-1ef1a704bc87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95464923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.95464923
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.70333654
Short name T781
Test name
Test status
Simulation time 92876504 ps
CPU time 9.81 seconds
Started Jul 12 05:57:31 PM PDT 24
Finished Jul 12 05:57:56 PM PDT 24
Peak memory 204792 kb
Host smart-25080d7a-ffc8-4999-ba6b-007ce431f015
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70333654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.70333654
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3606570275
Short name T174
Test name
Test status
Simulation time 17045123397 ps
CPU time 57.39 seconds
Started Jul 12 05:57:29 PM PDT 24
Finished Jul 12 05:58:40 PM PDT 24
Peak memory 211732 kb
Host smart-8d0d2cf3-807e-4600-aae1-5d5b1bdd3e6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606570275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3606570275
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.597350137
Short name T680
Test name
Test status
Simulation time 16572151109 ps
CPU time 114.67 seconds
Started Jul 12 05:57:32 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 211744 kb
Host smart-c9888f73-6c5a-4473-a9a3-3bd021ad0d96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=597350137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.597350137
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.746451632
Short name T271
Test name
Test status
Simulation time 153168906 ps
CPU time 17.61 seconds
Started Jul 12 05:57:29 PM PDT 24
Finished Jul 12 05:58:00 PM PDT 24
Peak memory 204592 kb
Host smart-4e34ee09-1ea2-4640-8051-eda78b3dbecb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746451632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.746451632
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.1339146183
Short name T134
Test name
Test status
Simulation time 1018514369 ps
CPU time 22.71 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:58:12 PM PDT 24
Peak memory 204184 kb
Host smart-d6cdb6b4-300c-49fd-8fae-6b15692db549
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1339146183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1339146183
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3412695805
Short name T787
Test name
Test status
Simulation time 240080932 ps
CPU time 3.42 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 05:57:47 PM PDT 24
Peak memory 203424 kb
Host smart-2866bdc4-1734-4da4-993f-16ac069f3622
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3412695805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3412695805
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.4215552585
Short name T575
Test name
Test status
Simulation time 11155511580 ps
CPU time 33.09 seconds
Started Jul 12 05:57:30 PM PDT 24
Finished Jul 12 05:58:17 PM PDT 24
Peak memory 203548 kb
Host smart-ac1dbefc-abf9-4bba-8665-ccf4853a1da0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215552585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.4215552585
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.170700486
Short name T811
Test name
Test status
Simulation time 4451611399 ps
CPU time 39.99 seconds
Started Jul 12 05:57:29 PM PDT 24
Finished Jul 12 05:58:23 PM PDT 24
Peak memory 203492 kb
Host smart-64e3df8c-77aa-44c9-ab77-bf9f23a36f99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=170700486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.170700486
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1014194074
Short name T247
Test name
Test status
Simulation time 54340346 ps
CPU time 2.21 seconds
Started Jul 12 05:57:37 PM PDT 24
Finished Jul 12 05:57:52 PM PDT 24
Peak memory 203444 kb
Host smart-e8e35d9b-07c4-4185-85d7-eba270457d09
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014194074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1014194074
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1651364075
Short name T806
Test name
Test status
Simulation time 9385932481 ps
CPU time 121.56 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 05:59:50 PM PDT 24
Peak memory 208552 kb
Host smart-066c6b36-e6b0-49d8-961f-5451385b9736
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1651364075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1651364075
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.313621366
Short name T255
Test name
Test status
Simulation time 15424486032 ps
CPU time 268.7 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 06:02:18 PM PDT 24
Peak memory 207396 kb
Host smart-4c11e301-fb3c-446a-ad6d-c54acd614406
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=313621366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.313621366
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3434241048
Short name T648
Test name
Test status
Simulation time 1972832508 ps
CPU time 314.24 seconds
Started Jul 12 05:57:29 PM PDT 24
Finished Jul 12 06:02:57 PM PDT 24
Peak memory 220024 kb
Host smart-d173b1ca-f6de-4ba8-954c-df7655e3fb99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3434241048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.3434241048
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2169268202
Short name T381
Test name
Test status
Simulation time 267132254 ps
CPU time 18.2 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:58:08 PM PDT 24
Peak memory 211656 kb
Host smart-72bb9709-a120-48c2-b4dd-6979caf988ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2169268202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2169268202
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2412870898
Short name T690
Test name
Test status
Simulation time 1332088349 ps
CPU time 11.68 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:31 PM PDT 24
Peak memory 203492 kb
Host smart-cd97dfb4-f54e-40b2-b451-26895301451a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2412870898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2412870898
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3004436759
Short name T450
Test name
Test status
Simulation time 59038968832 ps
CPU time 407.27 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 06:02:09 PM PDT 24
Peak memory 211712 kb
Host smart-d3b71a7a-623b-4f77-9a45-47d364fcd012
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3004436759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3004436759
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3350421932
Short name T388
Test name
Test status
Simulation time 723912213 ps
CPU time 24.44 seconds
Started Jul 12 05:55:16 PM PDT 24
Finished Jul 12 05:55:43 PM PDT 24
Peak memory 203544 kb
Host smart-2dab6a9c-e3cd-4403-9818-879b29d2d37a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3350421932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3350421932
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.414106884
Short name T422
Test name
Test status
Simulation time 553649294 ps
CPU time 5.74 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:28 PM PDT 24
Peak memory 203488 kb
Host smart-08abb1aa-a83b-4021-a6a9-91a4c1a8a035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=414106884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.414106884
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2246991883
Short name T127
Test name
Test status
Simulation time 308658615 ps
CPU time 4.92 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:27 PM PDT 24
Peak memory 204292 kb
Host smart-5473ba91-e1db-4e41-9041-23dd3ca0e914
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2246991883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2246991883
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2176918691
Short name T555
Test name
Test status
Simulation time 98545089465 ps
CPU time 283.91 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 06:00:06 PM PDT 24
Peak memory 204776 kb
Host smart-7ea03812-a605-4fd4-ac86-92a3f480ede3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176918691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2176918691
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4003682625
Short name T89
Test name
Test status
Simulation time 28742098052 ps
CPU time 147.96 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:57:47 PM PDT 24
Peak memory 211724 kb
Host smart-92b74526-bced-4a0f-8192-b40e7a71aa62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4003682625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4003682625
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1962515742
Short name T686
Test name
Test status
Simulation time 110354958 ps
CPU time 11.8 seconds
Started Jul 12 05:55:13 PM PDT 24
Finished Jul 12 05:55:25 PM PDT 24
Peak memory 211652 kb
Host smart-66622999-fcda-401a-add5-a727e02c9f79
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962515742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1962515742
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.2268808593
Short name T675
Test name
Test status
Simulation time 141307350 ps
CPU time 9.94 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:29 PM PDT 24
Peak memory 204164 kb
Host smart-60f3db45-83cc-4728-802f-defb36d0a952
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2268808593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2268808593
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.3161436259
Short name T895
Test name
Test status
Simulation time 847350027 ps
CPU time 3.96 seconds
Started Jul 12 05:59:57 PM PDT 24
Finished Jul 12 06:00:04 PM PDT 24
Peak memory 203480 kb
Host smart-4d45ba60-e105-40de-a950-159896d23e68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3161436259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3161436259
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4057794091
Short name T571
Test name
Test status
Simulation time 5090954986 ps
CPU time 26.59 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 203028 kb
Host smart-ef7a5dff-ad4e-445a-a73b-980fc8f52e5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057794091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4057794091
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3291588872
Short name T446
Test name
Test status
Simulation time 3079702587 ps
CPU time 25.64 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 203048 kb
Host smart-3464b419-4a34-4d64-936f-cbc17148e702
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3291588872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3291588872
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.449725855
Short name T813
Test name
Test status
Simulation time 68665115 ps
CPU time 2.2 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 203472 kb
Host smart-92095185-3885-407f-a485-7de7b37d4cfb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449725855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.449725855
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2471082088
Short name T845
Test name
Test status
Simulation time 2075069842 ps
CPU time 70.4 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:56:33 PM PDT 24
Peak memory 205540 kb
Host smart-f59105be-cdea-491d-a6b9-d8eefb65b72c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2471082088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2471082088
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2064273476
Short name T809
Test name
Test status
Simulation time 319123493 ps
CPU time 17.96 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:41 PM PDT 24
Peak memory 205280 kb
Host smart-c76bd2b1-e0d6-4e82-9c04-e993db1475fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2064273476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2064273476
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1711966210
Short name T460
Test name
Test status
Simulation time 145141043 ps
CPU time 65.64 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:56:30 PM PDT 24
Peak memory 206724 kb
Host smart-6cbde493-184f-417f-b674-d70a66775efb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1711966210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.1711966210
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.316170644
Short name T668
Test name
Test status
Simulation time 32975699 ps
CPU time 30.6 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:53 PM PDT 24
Peak memory 204984 kb
Host smart-5cd66fa2-29a3-45eb-b2f6-fe022777485c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=316170644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese
t_error.316170644
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2814760466
Short name T554
Test name
Test status
Simulation time 769373467 ps
CPU time 21.03 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:46 PM PDT 24
Peak memory 211636 kb
Host smart-13e364ee-f7ae-44d0-97d4-ffe47a309f7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2814760466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2814760466
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3813540884
Short name T645
Test name
Test status
Simulation time 2754635279 ps
CPU time 58.83 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 05:58:48 PM PDT 24
Peak memory 211708 kb
Host smart-1ff63577-0f61-48ae-a5bb-b8569828c680
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3813540884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3813540884
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1363621806
Short name T506
Test name
Test status
Simulation time 72090441193 ps
CPU time 394.45 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 06:04:23 PM PDT 24
Peak memory 211736 kb
Host smart-075fbe01-8d80-4369-8abf-6ab50dfc1381
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1363621806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.1363621806
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.38764249
Short name T495
Test name
Test status
Simulation time 29367225 ps
CPU time 3.25 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 05:57:52 PM PDT 24
Peak memory 203404 kb
Host smart-b95e5fdc-82f1-415b-9d09-9903a6492b7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38764249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.38764249
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2368491071
Short name T437
Test name
Test status
Simulation time 359941592 ps
CPU time 13.44 seconds
Started Jul 12 05:57:37 PM PDT 24
Finished Jul 12 05:58:04 PM PDT 24
Peak memory 203480 kb
Host smart-0ad2d83f-559e-4332-8cc1-f94e31f17a56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2368491071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2368491071
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.2785687619
Short name T685
Test name
Test status
Simulation time 131466538 ps
CPU time 9.93 seconds
Started Jul 12 05:57:37 PM PDT 24
Finished Jul 12 05:58:01 PM PDT 24
Peak memory 211660 kb
Host smart-605f9271-0e05-4328-bfa1-d39429282074
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2785687619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2785687619
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.721745151
Short name T492
Test name
Test status
Simulation time 20364495918 ps
CPU time 121.7 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:59:51 PM PDT 24
Peak memory 211744 kb
Host smart-4cd4af5d-f216-470d-af59-4eb1c56745ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=721745151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.721745151
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3401781298
Short name T110
Test name
Test status
Simulation time 150137063062 ps
CPU time 310.02 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 06:02:59 PM PDT 24
Peak memory 211732 kb
Host smart-39821c2a-d05d-493a-9e4e-c6c6a8841607
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3401781298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3401781298
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1233233289
Short name T733
Test name
Test status
Simulation time 187370428 ps
CPU time 17.13 seconds
Started Jul 12 05:57:39 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 211644 kb
Host smart-3771b3d6-8635-458f-a323-c21e4cc0ed80
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233233289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1233233289
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.1663714041
Short name T472
Test name
Test status
Simulation time 2024978160 ps
CPU time 22.96 seconds
Started Jul 12 05:57:33 PM PDT 24
Finished Jul 12 05:58:10 PM PDT 24
Peak memory 203520 kb
Host smart-e8c2d8ac-0ad1-4132-8f33-5b64362648cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663714041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1663714041
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.3309650104
Short name T105
Test name
Test status
Simulation time 99543195 ps
CPU time 3.25 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:57:53 PM PDT 24
Peak memory 203448 kb
Host smart-16681f78-f1f7-4122-b349-c08d13a256e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3309650104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3309650104
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3756754802
Short name T253
Test name
Test status
Simulation time 6637909829 ps
CPU time 36.81 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 05:58:26 PM PDT 24
Peak memory 203560 kb
Host smart-86893f1a-d59e-4cf4-95b0-d2b2800aa7dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756754802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3756754802
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1381960272
Short name T793
Test name
Test status
Simulation time 10104710569 ps
CPU time 32.74 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:58:22 PM PDT 24
Peak memory 203508 kb
Host smart-3773337f-d599-4322-b226-6f01cfb80fc9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1381960272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1381960272
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3623759137
Short name T842
Test name
Test status
Simulation time 45354327 ps
CPU time 2.39 seconds
Started Jul 12 05:57:31 PM PDT 24
Finished Jul 12 05:57:47 PM PDT 24
Peak memory 203484 kb
Host smart-73cd92d6-1551-4e26-9647-f42adbc81abe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623759137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3623759137
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3359578499
Short name T797
Test name
Test status
Simulation time 1077578553 ps
CPU time 126.77 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:59:56 PM PDT 24
Peak memory 208396 kb
Host smart-6f743b50-b866-4d13-a3f0-c864f9772ec2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3359578499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3359578499
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2356937940
Short name T815
Test name
Test status
Simulation time 2287472674 ps
CPU time 36.05 seconds
Started Jul 12 05:57:37 PM PDT 24
Finished Jul 12 05:58:27 PM PDT 24
Peak memory 204108 kb
Host smart-6db7e77c-71df-4951-88ce-fda9dc535e90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2356937940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2356937940
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3044074735
Short name T887
Test name
Test status
Simulation time 409530716 ps
CPU time 137.86 seconds
Started Jul 12 05:57:38 PM PDT 24
Finished Jul 12 06:00:09 PM PDT 24
Peak memory 209024 kb
Host smart-791ca1b5-d37a-4b7d-bff4-9c4574786670
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3044074735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.3044074735
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1063231923
Short name T310
Test name
Test status
Simulation time 614058609 ps
CPU time 147.07 seconds
Started Jul 12 05:57:34 PM PDT 24
Finished Jul 12 06:00:16 PM PDT 24
Peak memory 211136 kb
Host smart-645780ad-e8ac-4fa7-a90b-7f530d14bfbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1063231923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.1063231923
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3483750260
Short name T179
Test name
Test status
Simulation time 528462535 ps
CPU time 15.25 seconds
Started Jul 12 05:57:34 PM PDT 24
Finished Jul 12 05:58:03 PM PDT 24
Peak memory 211644 kb
Host smart-671df846-e89c-46bd-99f0-8e82e75f9b2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3483750260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3483750260
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3335676923
Short name T62
Test name
Test status
Simulation time 3850137683 ps
CPU time 22.14 seconds
Started Jul 12 05:57:40 PM PDT 24
Finished Jul 12 05:58:15 PM PDT 24
Peak memory 211676 kb
Host smart-0f37990f-7f00-4ad1-a7b2-fbda8566d257
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3335676923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3335676923
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.630065432
Short name T519
Test name
Test status
Simulation time 13743575390 ps
CPU time 107.5 seconds
Started Jul 12 05:57:39 PM PDT 24
Finished Jul 12 05:59:39 PM PDT 24
Peak memory 211740 kb
Host smart-3e91ce14-30c6-4a3f-b0cd-58cd0712f4ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=630065432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.630065432
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.261269837
Short name T868
Test name
Test status
Simulation time 267513510 ps
CPU time 19 seconds
Started Jul 12 05:57:41 PM PDT 24
Finished Jul 12 05:58:12 PM PDT 24
Peak memory 203492 kb
Host smart-162fd679-51ee-47c3-a787-88aa4c821ede
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=261269837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.261269837
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.3555560774
Short name T250
Test name
Test status
Simulation time 147072831 ps
CPU time 12.77 seconds
Started Jul 12 05:57:39 PM PDT 24
Finished Jul 12 05:58:05 PM PDT 24
Peak memory 203516 kb
Host smart-29983d65-8bdf-44c3-b477-6520bf1636d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3555560774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3555560774
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.2775262599
Short name T625
Test name
Test status
Simulation time 46782073 ps
CPU time 5.63 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:57:55 PM PDT 24
Peak memory 204584 kb
Host smart-b512d524-8a6e-4b60-8cb4-d6009499d09c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2775262599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2775262599
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2509444991
Short name T606
Test name
Test status
Simulation time 112989970566 ps
CPU time 162.43 seconds
Started Jul 12 05:57:34 PM PDT 24
Finished Jul 12 06:00:30 PM PDT 24
Peak memory 211600 kb
Host smart-aa796a8e-2958-49a3-a474-27ebfc1b8496
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509444991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2509444991
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.539109128
Short name T60
Test name
Test status
Simulation time 13885140706 ps
CPU time 80.43 seconds
Started Jul 12 05:57:41 PM PDT 24
Finished Jul 12 05:59:13 PM PDT 24
Peak memory 211708 kb
Host smart-734c1f78-d998-48dd-b41f-d6dd5e16bf60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=539109128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.539109128
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.38204165
Short name T867
Test name
Test status
Simulation time 54018123 ps
CPU time 7.85 seconds
Started Jul 12 05:57:37 PM PDT 24
Finished Jul 12 05:57:59 PM PDT 24
Peak memory 204552 kb
Host smart-4b729951-df00-46c7-bae6-9652746f5b43
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.38204165
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.3746254184
Short name T807
Test name
Test status
Simulation time 2211063464 ps
CPU time 28.89 seconds
Started Jul 12 05:57:41 PM PDT 24
Finished Jul 12 05:58:22 PM PDT 24
Peak memory 204224 kb
Host smart-d664f3f7-c74b-44a3-bcd0-c14f8d1f0464
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746254184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3746254184
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.3472899681
Short name T630
Test name
Test status
Simulation time 50830268 ps
CPU time 2.45 seconds
Started Jul 12 05:57:36 PM PDT 24
Finished Jul 12 05:57:52 PM PDT 24
Peak memory 203480 kb
Host smart-d29ed6e8-d652-4f2d-9720-e4973a67d719
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3472899681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3472899681
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2363257097
Short name T858
Test name
Test status
Simulation time 10340874741 ps
CPU time 25.33 seconds
Started Jul 12 05:57:40 PM PDT 24
Finished Jul 12 05:58:18 PM PDT 24
Peak memory 203524 kb
Host smart-b2f5026e-65fb-4042-b79e-dd9252aa1cea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363257097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2363257097
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3777221022
Short name T530
Test name
Test status
Simulation time 3675360199 ps
CPU time 30.38 seconds
Started Jul 12 05:57:35 PM PDT 24
Finished Jul 12 05:58:19 PM PDT 24
Peak memory 203620 kb
Host smart-40630458-85f9-43b1-904b-283259703390
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3777221022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3777221022
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.830419620
Short name T298
Test name
Test status
Simulation time 30920161 ps
CPU time 2.51 seconds
Started Jul 12 05:57:33 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 203408 kb
Host smart-5203a5f7-413c-4d78-83f9-37307c38a170
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830419620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.830419620
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.938915303
Short name T82
Test name
Test status
Simulation time 4870206059 ps
CPU time 166.7 seconds
Started Jul 12 05:57:45 PM PDT 24
Finished Jul 12 06:00:43 PM PDT 24
Peak memory 210332 kb
Host smart-cfc8eb1f-94e4-4c57-8a6c-1c2508b791d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=938915303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.938915303
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1759965777
Short name T730
Test name
Test status
Simulation time 2192923933 ps
CPU time 92.34 seconds
Started Jul 12 05:57:40 PM PDT 24
Finished Jul 12 05:59:25 PM PDT 24
Peak memory 205460 kb
Host smart-90050769-613b-4f02-a60e-e7282a22a29a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759965777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1759965777
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3143345180
Short name T171
Test name
Test status
Simulation time 1751615177 ps
CPU time 408.14 seconds
Started Jul 12 05:57:40 PM PDT 24
Finished Jul 12 06:04:41 PM PDT 24
Peak memory 209332 kb
Host smart-4f3895c0-acc1-48b2-aae5-21e3eaa9fb35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3143345180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3143345180
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1121374152
Short name T542
Test name
Test status
Simulation time 257252349 ps
CPU time 101.06 seconds
Started Jul 12 05:57:41 PM PDT 24
Finished Jul 12 05:59:34 PM PDT 24
Peak memory 209284 kb
Host smart-59c9709b-6a37-462f-854d-f465d9b04025
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1121374152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.1121374152
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2937506671
Short name T724
Test name
Test status
Simulation time 345091520 ps
CPU time 14.25 seconds
Started Jul 12 05:57:40 PM PDT 24
Finished Jul 12 05:58:07 PM PDT 24
Peak memory 211660 kb
Host smart-bf18da6d-951f-4b27-b9b0-6b4012fb6c59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2937506671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2937506671
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.560428251
Short name T86
Test name
Test status
Simulation time 248213456 ps
CPU time 3.9 seconds
Started Jul 12 05:57:47 PM PDT 24
Finished Jul 12 05:58:01 PM PDT 24
Peak memory 203508 kb
Host smart-6d6d9716-4cdf-43b9-a49b-3c54c23504e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=560428251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.560428251
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.25450758
Short name T122
Test name
Test status
Simulation time 155471173318 ps
CPU time 528.62 seconds
Started Jul 12 05:57:45 PM PDT 24
Finished Jul 12 06:06:44 PM PDT 24
Peak memory 211716 kb
Host smart-e3e6f7ae-9857-4c08-9ac4-eef09da3eee2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=25450758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow
_rsp.25450758
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1374112239
Short name T716
Test name
Test status
Simulation time 142778032 ps
CPU time 17.96 seconds
Started Jul 12 05:57:47 PM PDT 24
Finished Jul 12 05:58:15 PM PDT 24
Peak memory 203500 kb
Host smart-07b1813c-c52c-4b8f-9d49-dfa304ee9475
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1374112239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1374112239
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3495663185
Short name T98
Test name
Test status
Simulation time 3370424112 ps
CPU time 31.97 seconds
Started Jul 12 05:57:44 PM PDT 24
Finished Jul 12 05:58:27 PM PDT 24
Peak memory 203560 kb
Host smart-bb071f3e-27f1-4736-95d0-a49983aa60ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3495663185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3495663185
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.1445373616
Short name T332
Test name
Test status
Simulation time 131875305 ps
CPU time 20.93 seconds
Started Jul 12 05:57:39 PM PDT 24
Finished Jul 12 05:58:13 PM PDT 24
Peak memory 204636 kb
Host smart-c8df7c01-3468-4ef2-8525-4f5beba61cdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1445373616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1445373616
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3330991977
Short name T749
Test name
Test status
Simulation time 15355129837 ps
CPU time 38.07 seconds
Started Jul 12 05:57:38 PM PDT 24
Finished Jul 12 05:58:30 PM PDT 24
Peak memory 211672 kb
Host smart-89ea4d45-adf8-4915-90fb-7880222e1694
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330991977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3330991977
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3561688990
Short name T210
Test name
Test status
Simulation time 30540758288 ps
CPU time 214.75 seconds
Started Jul 12 05:57:45 PM PDT 24
Finished Jul 12 06:01:31 PM PDT 24
Peak memory 211720 kb
Host smart-1488a9a0-440a-4f02-8a51-f53fd9b0f1cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3561688990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3561688990
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.853212950
Short name T836
Test name
Test status
Simulation time 194133752 ps
CPU time 18.08 seconds
Started Jul 12 05:57:39 PM PDT 24
Finished Jul 12 05:58:10 PM PDT 24
Peak memory 204756 kb
Host smart-624d5e47-b657-4184-a25c-778c2e2101de
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853212950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.853212950
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.4178801141
Short name T155
Test name
Test status
Simulation time 216027182 ps
CPU time 5.51 seconds
Started Jul 12 05:57:46 PM PDT 24
Finished Jul 12 05:58:02 PM PDT 24
Peak memory 203504 kb
Host smart-f4432605-f73d-4d3a-8063-8e2375d02b83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178801141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4178801141
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2381519918
Short name T531
Test name
Test status
Simulation time 738299310 ps
CPU time 3.8 seconds
Started Jul 12 05:57:40 PM PDT 24
Finished Jul 12 05:57:57 PM PDT 24
Peak memory 203492 kb
Host smart-a3b28c5c-b201-429c-8496-bf91f42f9d8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2381519918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2381519918
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.4222442249
Short name T226
Test name
Test status
Simulation time 17307831482 ps
CPU time 31.94 seconds
Started Jul 12 05:57:43 PM PDT 24
Finished Jul 12 05:58:26 PM PDT 24
Peak memory 203560 kb
Host smart-d09e2dca-7b85-414f-bf89-1d3fd01a8d6b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222442249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4222442249
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1124070150
Short name T126
Test name
Test status
Simulation time 5235845745 ps
CPU time 28.17 seconds
Started Jul 12 05:57:41 PM PDT 24
Finished Jul 12 05:58:21 PM PDT 24
Peak memory 203540 kb
Host smart-e7f48dc4-f843-4fbc-a11e-eab41250c7bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1124070150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1124070150
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2927140847
Short name T540
Test name
Test status
Simulation time 23591799 ps
CPU time 2.29 seconds
Started Jul 12 05:57:41 PM PDT 24
Finished Jul 12 05:57:55 PM PDT 24
Peak memory 203432 kb
Host smart-50dddd39-49f5-40ed-8081-3e450f58b2c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927140847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2927140847
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1741036398
Short name T182
Test name
Test status
Simulation time 363813996 ps
CPU time 51.43 seconds
Started Jul 12 05:57:47 PM PDT 24
Finished Jul 12 05:58:49 PM PDT 24
Peak memory 211660 kb
Host smart-063eaf46-9be9-4a24-8320-b4f704ded5f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1741036398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1741036398
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1064742557
Short name T280
Test name
Test status
Simulation time 1157110554 ps
CPU time 73.23 seconds
Started Jul 12 05:57:45 PM PDT 24
Finished Jul 12 05:59:09 PM PDT 24
Peak memory 211720 kb
Host smart-4fe75dc6-ad8b-4d88-a700-c57b6abf9b0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064742557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1064742557
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.71145613
Short name T158
Test name
Test status
Simulation time 813720765 ps
CPU time 176.01 seconds
Started Jul 12 05:57:46 PM PDT 24
Finished Jul 12 06:00:52 PM PDT 24
Peak memory 209416 kb
Host smart-6e9df51c-24c8-42e7-a985-34c380d41f73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71145613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_
reset.71145613
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1920712146
Short name T505
Test name
Test status
Simulation time 68423357 ps
CPU time 6.36 seconds
Started Jul 12 05:57:48 PM PDT 24
Finished Jul 12 05:58:04 PM PDT 24
Peak memory 211632 kb
Host smart-e0e2293f-5b57-462e-8433-c0c5ed8e7e2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1920712146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1920712146
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1922558572
Short name T744
Test name
Test status
Simulation time 275038067 ps
CPU time 29.03 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 05:58:32 PM PDT 24
Peak memory 211696 kb
Host smart-f7382da1-5d5b-40fa-98a1-5baf4aa08b4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1922558572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1922558572
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4293100392
Short name T859
Test name
Test status
Simulation time 83323879991 ps
CPU time 688.4 seconds
Started Jul 12 05:57:51 PM PDT 24
Finished Jul 12 06:09:30 PM PDT 24
Peak memory 206144 kb
Host smart-82e3568d-14d8-475b-83ce-baedc817eeb2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4293100392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.4293100392
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1295136999
Short name T574
Test name
Test status
Simulation time 27431029 ps
CPU time 4.01 seconds
Started Jul 12 05:57:52 PM PDT 24
Finished Jul 12 05:58:06 PM PDT 24
Peak memory 203504 kb
Host smart-7702c63f-563e-4417-b378-1a3740b32edd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1295136999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1295136999
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1816168844
Short name T222
Test name
Test status
Simulation time 74659985 ps
CPU time 6.65 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 203440 kb
Host smart-7a501a92-7680-450b-98ea-6f2339a60f30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1816168844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1816168844
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1600606219
Short name T269
Test name
Test status
Simulation time 125949485 ps
CPU time 15.75 seconds
Started Jul 12 05:57:49 PM PDT 24
Finished Jul 12 05:58:16 PM PDT 24
Peak memory 211684 kb
Host smart-a611e21f-909d-4fbc-b074-bbe6e3092ae8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1600606219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1600606219
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2500223454
Short name T879
Test name
Test status
Simulation time 36336548842 ps
CPU time 158.31 seconds
Started Jul 12 05:57:52 PM PDT 24
Finished Jul 12 06:00:41 PM PDT 24
Peak memory 211708 kb
Host smart-06e404bf-0b46-478e-bcba-8d91bc8e0398
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500223454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2500223454
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1061528453
Short name T87
Test name
Test status
Simulation time 18099283587 ps
CPU time 148.51 seconds
Started Jul 12 05:57:50 PM PDT 24
Finished Jul 12 06:00:29 PM PDT 24
Peak memory 211744 kb
Host smart-3c257334-7903-4859-8954-25cf753e6d10
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1061528453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1061528453
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1905780331
Short name T149
Test name
Test status
Simulation time 60545026 ps
CPU time 8.36 seconds
Started Jul 12 05:57:50 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 211640 kb
Host smart-05ef3e9e-021d-4c67-9185-079c9439142a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905780331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1905780331
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.3460173144
Short name T603
Test name
Test status
Simulation time 401274889 ps
CPU time 10.66 seconds
Started Jul 12 05:57:49 PM PDT 24
Finished Jul 12 05:58:11 PM PDT 24
Peak memory 203916 kb
Host smart-7edf8bc4-7059-4821-b2cc-9e56e81663bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3460173144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3460173144
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.3938784042
Short name T672
Test name
Test status
Simulation time 90417324 ps
CPU time 2.27 seconds
Started Jul 12 05:57:47 PM PDT 24
Finished Jul 12 05:58:00 PM PDT 24
Peak memory 203484 kb
Host smart-73ab2848-a1c0-447a-bb9a-c66871eb76d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3938784042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3938784042
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1056960540
Short name T764
Test name
Test status
Simulation time 7508100052 ps
CPU time 26.5 seconds
Started Jul 12 05:57:44 PM PDT 24
Finished Jul 12 05:58:22 PM PDT 24
Peak memory 203532 kb
Host smart-a6006747-2605-4b9f-8812-b78d3539e218
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056960540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1056960540
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1802962561
Short name T862
Test name
Test status
Simulation time 4645649631 ps
CPU time 33.26 seconds
Started Jul 12 05:57:49 PM PDT 24
Finished Jul 12 05:58:33 PM PDT 24
Peak memory 203488 kb
Host smart-348a0f0d-1cb9-4104-9418-e195e915b94b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1802962561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1802962561
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3789853541
Short name T241
Test name
Test status
Simulation time 41563474 ps
CPU time 2.4 seconds
Started Jul 12 05:57:44 PM PDT 24
Finished Jul 12 05:57:57 PM PDT 24
Peak memory 203488 kb
Host smart-a0c8648c-bbcc-4e46-9929-e47c66d146c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789853541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3789853541
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1849355460
Short name T543
Test name
Test status
Simulation time 22678509499 ps
CPU time 243.87 seconds
Started Jul 12 05:57:52 PM PDT 24
Finished Jul 12 06:02:06 PM PDT 24
Peak memory 207520 kb
Host smart-c9490a65-973b-4e08-b6de-f7ffbeb0718a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1849355460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1849355460
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2124818872
Short name T701
Test name
Test status
Simulation time 5334567246 ps
CPU time 105.9 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 05:59:48 PM PDT 24
Peak memory 205696 kb
Host smart-03f36785-27bf-4bfe-b2e6-b3f6fb863b87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124818872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2124818872
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1093621004
Short name T533
Test name
Test status
Simulation time 3284193553 ps
CPU time 371.63 seconds
Started Jul 12 05:57:49 PM PDT 24
Finished Jul 12 06:04:10 PM PDT 24
Peak memory 210700 kb
Host smart-cf99b98f-2ec6-4930-9ebd-fe29c08f8249
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1093621004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.1093621004
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1892093986
Short name T24
Test name
Test status
Simulation time 1111636271 ps
CPU time 184.85 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 06:01:08 PM PDT 24
Peak memory 211644 kb
Host smart-58752530-46bb-4ea3-a3ee-d3fb4ba20f76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1892093986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1892093986
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.4031141925
Short name T152
Test name
Test status
Simulation time 2216928051 ps
CPU time 26.73 seconds
Started Jul 12 05:57:50 PM PDT 24
Finished Jul 12 05:58:27 PM PDT 24
Peak memory 211740 kb
Host smart-e3e31a2a-d1b7-45de-8ea4-3b217bd9f12f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4031141925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4031141925
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2880397085
Short name T80
Test name
Test status
Simulation time 3111646877 ps
CPU time 77.24 seconds
Started Jul 12 05:58:04 PM PDT 24
Finished Jul 12 05:59:39 PM PDT 24
Peak memory 207056 kb
Host smart-5e452510-2944-4650-8813-25cb9dd90683
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2880397085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2880397085
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3801927994
Short name T769
Test name
Test status
Simulation time 231092518719 ps
CPU time 561.49 seconds
Started Jul 12 05:57:57 PM PDT 24
Finished Jul 12 06:07:28 PM PDT 24
Peak memory 211712 kb
Host smart-e3e401d5-3196-495d-9b0f-8566d732ff88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3801927994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.3801927994
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2928766301
Short name T644
Test name
Test status
Simulation time 1129935870 ps
CPU time 28.76 seconds
Started Jul 12 05:57:56 PM PDT 24
Finished Jul 12 05:58:35 PM PDT 24
Peak memory 203692 kb
Host smart-b98ff8b8-8de0-436a-aaf9-d1bcf58082d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2928766301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2928766301
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.522934770
Short name T732
Test name
Test status
Simulation time 763468414 ps
CPU time 13.82 seconds
Started Jul 12 05:57:55 PM PDT 24
Finished Jul 12 05:58:18 PM PDT 24
Peak memory 203516 kb
Host smart-92807913-6d2f-4d59-9305-3b9d0c3f588a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=522934770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.522934770
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.597892994
Short name T621
Test name
Test status
Simulation time 2056583528 ps
CPU time 27.36 seconds
Started Jul 12 05:57:50 PM PDT 24
Finished Jul 12 05:58:28 PM PDT 24
Peak memory 211608 kb
Host smart-5305248b-4d46-4915-bb7a-c687bfab1832
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=597892994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.597892994
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.197687394
Short name T57
Test name
Test status
Simulation time 92536622071 ps
CPU time 173.56 seconds
Started Jul 12 05:57:52 PM PDT 24
Finished Jul 12 06:00:56 PM PDT 24
Peak memory 204808 kb
Host smart-24de808f-47b1-428b-8a1f-8e03cc3c272d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=197687394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.197687394
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3311944742
Short name T374
Test name
Test status
Simulation time 25111278508 ps
CPU time 205.31 seconds
Started Jul 12 05:57:48 PM PDT 24
Finished Jul 12 06:01:23 PM PDT 24
Peak memory 205260 kb
Host smart-72f0df74-0842-498d-a9f9-78143b68faf5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3311944742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3311944742
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3967383765
Short name T213
Test name
Test status
Simulation time 25058767 ps
CPU time 3.76 seconds
Started Jul 12 05:57:51 PM PDT 24
Finished Jul 12 05:58:04 PM PDT 24
Peak memory 203480 kb
Host smart-f5b6ef0d-ca8b-4b26-a681-64f6e33c573f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967383765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3967383765
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.4116491552
Short name T538
Test name
Test status
Simulation time 275297311 ps
CPU time 2.94 seconds
Started Jul 12 05:57:56 PM PDT 24
Finished Jul 12 05:58:09 PM PDT 24
Peak memory 203484 kb
Host smart-3c4c3885-0d21-45b7-928e-d704664a4e37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4116491552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4116491552
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1966438788
Short name T376
Test name
Test status
Simulation time 508727185 ps
CPU time 3.79 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 05:58:07 PM PDT 24
Peak memory 203468 kb
Host smart-e649a277-89ab-4c85-bee1-c4c480ad5c51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1966438788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1966438788
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3246551570
Short name T245
Test name
Test status
Simulation time 4817893915 ps
CPU time 30.18 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 05:58:33 PM PDT 24
Peak memory 203560 kb
Host smart-6cd4cd3f-5e42-47a1-aeaa-3bb305b937e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246551570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3246551570
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4020590410
Short name T40
Test name
Test status
Simulation time 3361904573 ps
CPU time 22.98 seconds
Started Jul 12 05:57:53 PM PDT 24
Finished Jul 12 05:58:26 PM PDT 24
Peak memory 203496 kb
Host smart-9b67338f-cf7c-4755-8247-ee73e48f0005
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4020590410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4020590410
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1553573370
Short name T591
Test name
Test status
Simulation time 33267867 ps
CPU time 2.13 seconds
Started Jul 12 05:57:51 PM PDT 24
Finished Jul 12 05:58:03 PM PDT 24
Peak memory 203476 kb
Host smart-a1200e70-5da9-4065-b6b2-a8d982f2427c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553573370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1553573370
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.976482722
Short name T861
Test name
Test status
Simulation time 3550063434 ps
CPU time 78.38 seconds
Started Jul 12 05:57:57 PM PDT 24
Finished Jul 12 05:59:25 PM PDT 24
Peak memory 207524 kb
Host smart-7beeead1-8c15-423d-817b-fc6a4ced7990
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=976482722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.976482722
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.36107015
Short name T728
Test name
Test status
Simulation time 2004009872 ps
CPU time 118.61 seconds
Started Jul 12 05:57:54 PM PDT 24
Finished Jul 12 06:00:02 PM PDT 24
Peak memory 207256 kb
Host smart-28a91795-1154-4ec1-a51a-0c22954ae68b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36107015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.36107015
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3238322717
Short name T588
Test name
Test status
Simulation time 2587972025 ps
CPU time 352.86 seconds
Started Jul 12 05:58:03 PM PDT 24
Finished Jul 12 06:04:13 PM PDT 24
Peak memory 209156 kb
Host smart-aeb706f9-82c4-424e-8fb2-30eadd05084f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3238322717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.3238322717
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2876092827
Short name T183
Test name
Test status
Simulation time 675735325 ps
CPU time 174.82 seconds
Started Jul 12 05:57:54 PM PDT 24
Finished Jul 12 06:00:59 PM PDT 24
Peak memory 211488 kb
Host smart-5a43f07d-7512-46c0-af71-8076c3b4dae9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2876092827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.2876092827
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2522185287
Short name T827
Test name
Test status
Simulation time 48882321 ps
CPU time 3.79 seconds
Started Jul 12 05:57:57 PM PDT 24
Finished Jul 12 05:58:11 PM PDT 24
Peak memory 204988 kb
Host smart-b8ab1650-a23d-4efb-b72b-1e5f088b103f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2522185287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2522185287
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.816015724
Short name T411
Test name
Test status
Simulation time 3831072923 ps
CPU time 81.21 seconds
Started Jul 12 05:57:58 PM PDT 24
Finished Jul 12 05:59:30 PM PDT 24
Peak memory 211684 kb
Host smart-73908f9a-6f2c-40ac-9f50-5793d6956b94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=816015724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.816015724
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.377627486
Short name T897
Test name
Test status
Simulation time 129232626480 ps
CPU time 529.33 seconds
Started Jul 12 05:58:01 PM PDT 24
Finished Jul 12 06:07:03 PM PDT 24
Peak memory 211744 kb
Host smart-7da664dd-084d-4b4e-98b7-8957971cdf26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=377627486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo
w_rsp.377627486
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.895395783
Short name T305
Test name
Test status
Simulation time 483929023 ps
CPU time 17.79 seconds
Started Jul 12 05:58:00 PM PDT 24
Finished Jul 12 05:58:30 PM PDT 24
Peak memory 203844 kb
Host smart-ffbd3fec-ea33-4d06-9e56-840dc335a113
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=895395783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.895395783
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2263370453
Short name T352
Test name
Test status
Simulation time 90700227 ps
CPU time 9.35 seconds
Started Jul 12 05:58:02 PM PDT 24
Finished Jul 12 05:58:25 PM PDT 24
Peak memory 203512 kb
Host smart-22b606b1-a532-482c-8753-f9e41a12c65e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2263370453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2263370453
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.1461222710
Short name T534
Test name
Test status
Simulation time 295486709 ps
CPU time 14.07 seconds
Started Jul 12 05:57:56 PM PDT 24
Finished Jul 12 05:58:20 PM PDT 24
Peak memory 211676 kb
Host smart-17478362-b080-40df-bd61-0dc11164d03f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1461222710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1461222710
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.259857556
Short name T389
Test name
Test status
Simulation time 8763027210 ps
CPU time 37.29 seconds
Started Jul 12 05:58:03 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 211700 kb
Host smart-df7c2c20-6bd0-4551-89f8-f6929d1caae1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=259857556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.259857556
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3172835192
Short name T189
Test name
Test status
Simulation time 20763825602 ps
CPU time 163.68 seconds
Started Jul 12 05:58:01 PM PDT 24
Finished Jul 12 06:00:59 PM PDT 24
Peak memory 211696 kb
Host smart-d636255d-ba47-41fe-af5f-480957a5b916
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3172835192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3172835192
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.347647424
Short name T218
Test name
Test status
Simulation time 151877921 ps
CPU time 20.26 seconds
Started Jul 12 05:57:55 PM PDT 24
Finished Jul 12 05:58:25 PM PDT 24
Peak memory 211680 kb
Host smart-2d2d4816-e748-42a6-8ece-714b91980243
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347647424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.347647424
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.86672163
Short name T477
Test name
Test status
Simulation time 481473137 ps
CPU time 11.11 seconds
Started Jul 12 05:57:58 PM PDT 24
Finished Jul 12 05:58:21 PM PDT 24
Peak memory 203516 kb
Host smart-d1b83409-2d36-44d5-a876-41dd310e0525
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86672163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.86672163
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.318977519
Short name T880
Test name
Test status
Simulation time 219402970 ps
CPU time 4.11 seconds
Started Jul 12 05:57:54 PM PDT 24
Finished Jul 12 05:58:08 PM PDT 24
Peak memory 203472 kb
Host smart-5f226325-d28c-404d-b603-ac78e8e2a859
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=318977519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.318977519
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.692597725
Short name T570
Test name
Test status
Simulation time 7081673925 ps
CPU time 31.93 seconds
Started Jul 12 05:57:54 PM PDT 24
Finished Jul 12 05:58:36 PM PDT 24
Peak memory 203512 kb
Host smart-b1171e32-70d3-4129-b8d5-74d8b811f258
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=692597725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.692597725
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1672048977
Short name T244
Test name
Test status
Simulation time 10994135212 ps
CPU time 36.55 seconds
Started Jul 12 05:57:55 PM PDT 24
Finished Jul 12 05:58:41 PM PDT 24
Peak memory 203520 kb
Host smart-31e2063d-9b28-4d17-9645-20cae5944912
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1672048977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1672048977
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2434855894
Short name T488
Test name
Test status
Simulation time 27835902 ps
CPU time 2.36 seconds
Started Jul 12 05:57:56 PM PDT 24
Finished Jul 12 05:58:08 PM PDT 24
Peak memory 203476 kb
Host smart-aa4870e2-91dd-4381-b703-5db261194e20
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434855894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2434855894
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.298796550
Short name T227
Test name
Test status
Simulation time 625897841 ps
CPU time 19.71 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:58:45 PM PDT 24
Peak memory 204876 kb
Host smart-97cab9d3-010e-457f-8cf5-4363d75a1df7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=298796550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.298796550
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.508301326
Short name T501
Test name
Test status
Simulation time 2316028653 ps
CPU time 142.73 seconds
Started Jul 12 05:58:00 PM PDT 24
Finished Jul 12 06:00:35 PM PDT 24
Peak memory 211768 kb
Host smart-113953c9-7225-45ca-a9e8-93ed39db3560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=508301326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.508301326
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3273265537
Short name T157
Test name
Test status
Simulation time 2147842071 ps
CPU time 388.38 seconds
Started Jul 12 05:58:00 PM PDT 24
Finished Jul 12 06:04:41 PM PDT 24
Peak memory 209464 kb
Host smart-47fed674-cacf-4393-b1c3-a8228c49c5e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3273265537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.3273265537
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4005682821
Short name T612
Test name
Test status
Simulation time 209156607 ps
CPU time 50.02 seconds
Started Jul 12 05:57:59 PM PDT 24
Finished Jul 12 05:59:01 PM PDT 24
Peak memory 207156 kb
Host smart-f60c2411-0f77-42ac-a531-7095ceb9f64b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005682821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.4005682821
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2365356579
Short name T353
Test name
Test status
Simulation time 715686401 ps
CPU time 5.77 seconds
Started Jul 12 05:58:06 PM PDT 24
Finished Jul 12 05:58:33 PM PDT 24
Peak memory 211608 kb
Host smart-518354ad-ed91-4df3-bf1e-e4037c37f0b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365356579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2365356579
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2447856604
Short name T899
Test name
Test status
Simulation time 3517347916 ps
CPU time 32.87 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 211712 kb
Host smart-eb08e8ba-9868-4536-8527-4530926c1369
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2447856604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2447856604
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1105670301
Short name T232
Test name
Test status
Simulation time 26654122291 ps
CPU time 153.95 seconds
Started Jul 12 05:58:06 PM PDT 24
Finished Jul 12 06:01:00 PM PDT 24
Peak memory 211692 kb
Host smart-ec76329d-d6d1-461e-8a61-24c13cd70f65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1105670301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.1105670301
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2988626964
Short name T746
Test name
Test status
Simulation time 83956138 ps
CPU time 11.29 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:58:37 PM PDT 24
Peak memory 203516 kb
Host smart-84bdfc77-d3da-42de-9ed5-de54272e8bdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2988626964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2988626964
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.3584527664
Short name T448
Test name
Test status
Simulation time 327733442 ps
CPU time 10.19 seconds
Started Jul 12 05:58:06 PM PDT 24
Finished Jul 12 05:58:38 PM PDT 24
Peak memory 203484 kb
Host smart-c82e2bcc-12d9-493a-9561-e8cd657f8d86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3584527664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3584527664
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.2608253066
Short name T234
Test name
Test status
Simulation time 81415457 ps
CPU time 3.26 seconds
Started Jul 12 05:57:59 PM PDT 24
Finished Jul 12 05:58:14 PM PDT 24
Peak memory 203464 kb
Host smart-a1198857-3be7-4f23-a1c1-92bb86169a2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2608253066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2608253066
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.237289999
Short name T341
Test name
Test status
Simulation time 76262938343 ps
CPU time 100.49 seconds
Started Jul 12 05:58:00 PM PDT 24
Finished Jul 12 05:59:53 PM PDT 24
Peak memory 211744 kb
Host smart-70a95f95-b638-4a7b-8dbb-5d7e03fb9f3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=237289999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.237289999
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2089572266
Short name T176
Test name
Test status
Simulation time 34403040817 ps
CPU time 72 seconds
Started Jul 12 05:57:59 PM PDT 24
Finished Jul 12 05:59:24 PM PDT 24
Peak memory 204824 kb
Host smart-525d505a-7928-4b7f-ad7c-af19afe145b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2089572266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2089572266
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1456692005
Short name T184
Test name
Test status
Simulation time 190497274 ps
CPU time 17.01 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:58:43 PM PDT 24
Peak memory 211596 kb
Host smart-2a6c66a9-f369-429c-a708-8144ab8135bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456692005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1456692005
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.1450750012
Short name T407
Test name
Test status
Simulation time 455904791 ps
CPU time 18.43 seconds
Started Jul 12 05:58:10 PM PDT 24
Finished Jul 12 05:58:55 PM PDT 24
Peak memory 204384 kb
Host smart-512fdcf5-2b42-405c-9809-bc0b70cef9e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1450750012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1450750012
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1853919787
Short name T520
Test name
Test status
Simulation time 30937892 ps
CPU time 2.31 seconds
Started Jul 12 05:58:00 PM PDT 24
Finished Jul 12 05:58:15 PM PDT 24
Peak memory 203452 kb
Host smart-bbbd4863-48c9-408a-a474-2308efa94f05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1853919787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1853919787
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2153090792
Short name T416
Test name
Test status
Simulation time 9131834371 ps
CPU time 36.63 seconds
Started Jul 12 05:58:06 PM PDT 24
Finished Jul 12 05:59:04 PM PDT 24
Peak memory 203504 kb
Host smart-91a03992-6e27-4cf5-8e8a-9c121b0cdd0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153090792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2153090792
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1739157991
Short name T38
Test name
Test status
Simulation time 3946501916 ps
CPU time 25.56 seconds
Started Jul 12 05:58:00 PM PDT 24
Finished Jul 12 05:58:38 PM PDT 24
Peak memory 203524 kb
Host smart-227457a8-c066-4323-b131-9fb85800e1a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1739157991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1739157991
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.402415025
Short name T691
Test name
Test status
Simulation time 24244235 ps
CPU time 2.24 seconds
Started Jul 12 05:57:59 PM PDT 24
Finished Jul 12 05:58:14 PM PDT 24
Peak memory 203488 kb
Host smart-32fa47f3-c4c9-4be7-9301-f664f687f4b5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402415025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.402415025
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2734323314
Short name T292
Test name
Test status
Simulation time 1002393169 ps
CPU time 96.82 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 06:00:02 PM PDT 24
Peak memory 209192 kb
Host smart-696d7610-b54b-4e6f-a42a-d6aed36173ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2734323314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2734323314
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2355225424
Short name T639
Test name
Test status
Simulation time 1021308618 ps
CPU time 77.73 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:59:43 PM PDT 24
Peak memory 206024 kb
Host smart-a3f5e00a-fb15-47d8-89fb-f8bd863adcfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2355225424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2355225424
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1631761111
Short name T633
Test name
Test status
Simulation time 1753966319 ps
CPU time 483.5 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 06:06:29 PM PDT 24
Peak memory 219884 kb
Host smart-4e68497e-7adf-4291-8d03-0e55a4c6d8b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1631761111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.1631761111
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3098721521
Short name T357
Test name
Test status
Simulation time 4096071523 ps
CPU time 504.07 seconds
Started Jul 12 05:58:09 PM PDT 24
Finished Jul 12 06:06:56 PM PDT 24
Peak memory 220032 kb
Host smart-a80157b4-d9c9-47e4-addd-b41605129d65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3098721521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.3098721521
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1308574686
Short name T360
Test name
Test status
Simulation time 226756210 ps
CPU time 7.51 seconds
Started Jul 12 05:58:09 PM PDT 24
Finished Jul 12 05:58:40 PM PDT 24
Peak memory 211516 kb
Host smart-510a9867-382c-47ff-8ef2-9642c0079cba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1308574686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1308574686
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.463502352
Short name T238
Test name
Test status
Simulation time 61711769 ps
CPU time 3.74 seconds
Started Jul 12 05:58:10 PM PDT 24
Finished Jul 12 05:58:38 PM PDT 24
Peak memory 203584 kb
Host smart-79fd2a88-dd53-4afa-af78-4e5d0aa890fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=463502352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.463502352
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.790526893
Short name T85
Test name
Test status
Simulation time 85576871562 ps
CPU time 576.38 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 06:08:19 PM PDT 24
Peak memory 211580 kb
Host smart-00f6577d-9e60-4cea-b685-f3cbc6e40712
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=790526893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo
w_rsp.790526893
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.264574392
Short name T544
Test name
Test status
Simulation time 17280775 ps
CPU time 1.81 seconds
Started Jul 12 05:58:13 PM PDT 24
Finished Jul 12 05:58:41 PM PDT 24
Peak memory 203500 kb
Host smart-fd84da4d-0e2b-4084-becd-baf64bb60a9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=264574392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.264574392
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2159757115
Short name T264
Test name
Test status
Simulation time 282929073 ps
CPU time 23.8 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 05:59:06 PM PDT 24
Peak memory 203460 kb
Host smart-1ba68e3a-3ef9-4322-bc8e-99bad9a7f59e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2159757115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2159757115
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.1051882058
Short name T885
Test name
Test status
Simulation time 666429213 ps
CPU time 22.8 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:58:48 PM PDT 24
Peak memory 211672 kb
Host smart-9499f141-9631-489a-b308-efa9d1a8f4f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1051882058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1051882058
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1674718516
Short name T148
Test name
Test status
Simulation time 13984041685 ps
CPU time 85.05 seconds
Started Jul 12 05:58:14 PM PDT 24
Finished Jul 12 06:00:07 PM PDT 24
Peak memory 211660 kb
Host smart-34725957-f7ed-4410-9bab-0ddca5f1441c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674718516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1674718516
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1592329929
Short name T869
Test name
Test status
Simulation time 27828203873 ps
CPU time 188.37 seconds
Started Jul 12 05:58:11 PM PDT 24
Finished Jul 12 06:01:45 PM PDT 24
Peak memory 211724 kb
Host smart-b1412c3b-89d4-438e-a6d5-6605f6f1c0d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1592329929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1592329929
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2124045224
Short name T275
Test name
Test status
Simulation time 171305249 ps
CPU time 23.1 seconds
Started Jul 12 05:58:05 PM PDT 24
Finished Jul 12 05:58:48 PM PDT 24
Peak memory 211620 kb
Host smart-abfab9ce-4260-4277-824d-724348be664c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124045224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2124045224
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.362388029
Short name T331
Test name
Test status
Simulation time 167963459 ps
CPU time 13.61 seconds
Started Jul 12 05:58:13 PM PDT 24
Finished Jul 12 05:58:55 PM PDT 24
Peak memory 203468 kb
Host smart-7968f35b-d162-425b-8f74-13b24b5a0b01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=362388029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.362388029
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.474778904
Short name T509
Test name
Test status
Simulation time 112727524 ps
CPU time 1.98 seconds
Started Jul 12 05:58:06 PM PDT 24
Finished Jul 12 05:58:28 PM PDT 24
Peak memory 203468 kb
Host smart-88c977f4-3f0c-4531-aa9e-cbcac97af2d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=474778904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.474778904
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1147626968
Short name T141
Test name
Test status
Simulation time 8894930705 ps
CPU time 30.09 seconds
Started Jul 12 05:58:07 PM PDT 24
Finished Jul 12 05:59:00 PM PDT 24
Peak memory 203504 kb
Host smart-6891e587-a4ab-41b1-8761-e1c678e42996
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147626968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1147626968
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1902648525
Short name T59
Test name
Test status
Simulation time 4197753232 ps
CPU time 28.71 seconds
Started Jul 12 05:58:04 PM PDT 24
Finished Jul 12 05:58:52 PM PDT 24
Peak memory 203520 kb
Host smart-129bf222-e227-4d8d-ad22-b904684afaad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1902648525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1902648525
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2357231301
Short name T165
Test name
Test status
Simulation time 25484968 ps
CPU time 2.15 seconds
Started Jul 12 05:58:09 PM PDT 24
Finished Jul 12 05:58:34 PM PDT 24
Peak memory 203344 kb
Host smart-91999858-9151-4051-b388-37f242fb8b5a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357231301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2357231301
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1166555805
Short name T485
Test name
Test status
Simulation time 675522145 ps
CPU time 78.66 seconds
Started Jul 12 05:58:11 PM PDT 24
Finished Jul 12 05:59:55 PM PDT 24
Peak memory 206992 kb
Host smart-a1b59d49-e54b-412a-8dd7-6e524ee9e6f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1166555805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1166555805
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3329681145
Short name T884
Test name
Test status
Simulation time 11161013505 ps
CPU time 289.74 seconds
Started Jul 12 05:58:14 PM PDT 24
Finished Jul 12 06:03:32 PM PDT 24
Peak memory 207452 kb
Host smart-0b27ac8a-feff-41b7-9d74-075562c1c45d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3329681145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3329681145
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2554692444
Short name T118
Test name
Test status
Simulation time 5188593292 ps
CPU time 136.23 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 06:01:00 PM PDT 24
Peak memory 209748 kb
Host smart-6dffaa6f-95fc-4f32-8585-3776bbf7460b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2554692444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.2554692444
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2941588008
Short name T390
Test name
Test status
Simulation time 3580415811 ps
CPU time 243.61 seconds
Started Jul 12 05:58:13 PM PDT 24
Finished Jul 12 06:02:45 PM PDT 24
Peak memory 219900 kb
Host smart-6357270a-7df8-4493-aba7-422df1632355
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2941588008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.2941588008
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3361790479
Short name T468
Test name
Test status
Simulation time 440699092 ps
CPU time 12.37 seconds
Started Jul 12 05:58:12 PM PDT 24
Finished Jul 12 05:58:49 PM PDT 24
Peak memory 211632 kb
Host smart-6ae1f2e2-7961-411d-9fe8-ee22b24ee5fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3361790479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3361790479
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2375859591
Short name T657
Test name
Test status
Simulation time 1073996011 ps
CPU time 26.56 seconds
Started Jul 12 05:58:11 PM PDT 24
Finished Jul 12 05:59:03 PM PDT 24
Peak memory 211696 kb
Host smart-7d7b8431-b61b-4250-8126-d02eacad325c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2375859591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2375859591
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.106623721
Short name T368
Test name
Test status
Simulation time 44534836209 ps
CPU time 297.41 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 06:03:42 PM PDT 24
Peak memory 206848 kb
Host smart-d003e7c8-4966-4a38-a5f2-45fa957dedd7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=106623721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo
w_rsp.106623721
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4068046582
Short name T306
Test name
Test status
Simulation time 131322286 ps
CPU time 10.44 seconds
Started Jul 12 05:58:16 PM PDT 24
Finished Jul 12 05:58:55 PM PDT 24
Peak memory 203516 kb
Host smart-7732d409-8a42-4294-ada7-ae2a3ed9a5cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4068046582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.4068046582
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.1211365039
Short name T525
Test name
Test status
Simulation time 125900472 ps
CPU time 11.86 seconds
Started Jul 12 05:58:17 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 203520 kb
Host smart-429093ba-a26a-4538-ba42-29ebee296f0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1211365039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1211365039
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.460427951
Short name T431
Test name
Test status
Simulation time 489851194 ps
CPU time 15.66 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 05:58:58 PM PDT 24
Peak memory 211660 kb
Host smart-d8a40e49-21c1-4056-8b02-dbf9f50f5f6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=460427951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.460427951
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.616377583
Short name T58
Test name
Test status
Simulation time 14802108615 ps
CPU time 27.2 seconds
Started Jul 12 05:58:11 PM PDT 24
Finished Jul 12 05:59:04 PM PDT 24
Peak memory 203644 kb
Host smart-972965f9-d97f-4ee4-814c-9269d5bf8edd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=616377583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.616377583
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.249880311
Short name T311
Test name
Test status
Simulation time 23714360744 ps
CPU time 201.18 seconds
Started Jul 12 05:58:12 PM PDT 24
Finished Jul 12 06:01:58 PM PDT 24
Peak memory 204828 kb
Host smart-7b2d4cd6-5b9d-4282-9af1-88d96b703311
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=249880311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.249880311
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2344736245
Short name T430
Test name
Test status
Simulation time 265466712 ps
CPU time 15.37 seconds
Started Jul 12 05:58:13 PM PDT 24
Finished Jul 12 05:58:54 PM PDT 24
Peak memory 211620 kb
Host smart-9d9e4631-a32c-4660-9d6d-d0cd26d5e4cf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344736245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2344736245
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.2376806755
Short name T346
Test name
Test status
Simulation time 919557170 ps
CPU time 18.66 seconds
Started Jul 12 05:58:09 PM PDT 24
Finished Jul 12 05:58:52 PM PDT 24
Peak memory 203524 kb
Host smart-544c1c89-4932-437a-8d22-e0dea5cb9451
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2376806755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2376806755
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.4026749462
Short name T42
Test name
Test status
Simulation time 132665594 ps
CPU time 3.3 seconds
Started Jul 12 05:58:11 PM PDT 24
Finished Jul 12 05:58:40 PM PDT 24
Peak memory 203488 kb
Host smart-aa8dc390-b8d3-4d69-84dd-ec54bb0d7f39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4026749462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.4026749462
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1961502259
Short name T886
Test name
Test status
Simulation time 7440709791 ps
CPU time 33.06 seconds
Started Jul 12 05:58:16 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 203528 kb
Host smart-b25b1f36-10a6-496b-877d-c9234861c5b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961502259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1961502259
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.178530293
Short name T585
Test name
Test status
Simulation time 4718094217 ps
CPU time 27.82 seconds
Started Jul 12 05:58:14 PM PDT 24
Finished Jul 12 05:59:10 PM PDT 24
Peak memory 203520 kb
Host smart-c81e70ee-c702-4924-9828-17c75c705026
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=178530293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.178530293
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1919682025
Short name T652
Test name
Test status
Simulation time 32170901 ps
CPU time 2.5 seconds
Started Jul 12 05:58:09 PM PDT 24
Finished Jul 12 05:58:36 PM PDT 24
Peak memory 203472 kb
Host smart-14506fd7-e3e5-4ac3-a8d6-0bd24e8094a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919682025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1919682025
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.23166528
Short name T202
Test name
Test status
Simulation time 7977265906 ps
CPU time 173.53 seconds
Started Jul 12 05:58:17 PM PDT 24
Finished Jul 12 06:01:38 PM PDT 24
Peak memory 208668 kb
Host smart-c09afdae-8559-4022-9d11-a9ea3cd87e22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23166528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.23166528
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3232722581
Short name T854
Test name
Test status
Simulation time 4183755868 ps
CPU time 141.74 seconds
Started Jul 12 05:58:16 PM PDT 24
Finished Jul 12 06:01:06 PM PDT 24
Peak memory 211732 kb
Host smart-5328aead-04be-4563-ab21-f30431c9bcb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3232722581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3232722581
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1262337634
Short name T838
Test name
Test status
Simulation time 89635547 ps
CPU time 60.26 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 05:59:43 PM PDT 24
Peak memory 206736 kb
Host smart-d13fe1b2-6d5a-43fb-a3a0-36ea6f0e7b22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262337634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.1262337634
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1630852926
Short name T22
Test name
Test status
Simulation time 1592483063 ps
CPU time 366.59 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 06:04:49 PM PDT 24
Peak memory 219900 kb
Host smart-d1dea009-9b90-4af7-8513-75b625bc5c6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1630852926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1630852926
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1538342377
Short name T697
Test name
Test status
Simulation time 50658298 ps
CPU time 6.46 seconds
Started Jul 12 05:58:16 PM PDT 24
Finished Jul 12 05:58:51 PM PDT 24
Peak memory 211676 kb
Host smart-12371245-1561-4caf-b8f2-cb3cf3c3d870
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1538342377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1538342377
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1666064328
Short name T580
Test name
Test status
Simulation time 477183450 ps
CPU time 23.66 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 05:59:13 PM PDT 24
Peak memory 205616 kb
Host smart-ef98efe1-6345-4df3-a1ad-1302fce60ada
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1666064328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1666064328
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1046326326
Short name T170
Test name
Test status
Simulation time 38414380642 ps
CPU time 185.51 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 06:01:55 PM PDT 24
Peak memory 206124 kb
Host smart-27dd0928-bb81-444d-92f3-fabb0ff52e00
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1046326326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.1046326326
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1265516108
Short name T584
Test name
Test status
Simulation time 52060198 ps
CPU time 4.81 seconds
Started Jul 12 05:58:22 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 203760 kb
Host smart-cd418b05-e636-4439-a825-bc67ce5a139a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1265516108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1265516108
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.75363056
Short name T281
Test name
Test status
Simulation time 913059180 ps
CPU time 26.36 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 05:59:16 PM PDT 24
Peak memory 203488 kb
Host smart-034192b5-a4ef-4424-8fcf-260d5f410d42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75363056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.75363056
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.99226445
Short name T444
Test name
Test status
Simulation time 867785807 ps
CPU time 33.85 seconds
Started Jul 12 05:58:17 PM PDT 24
Finished Jul 12 05:59:19 PM PDT 24
Peak memory 211684 kb
Host smart-bf7d7bbe-7620-46d7-859a-854314c96d1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99226445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.99226445
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.4057308237
Short name T604
Test name
Test status
Simulation time 6431148245 ps
CPU time 23.81 seconds
Started Jul 12 05:58:22 PM PDT 24
Finished Jul 12 05:59:16 PM PDT 24
Peak memory 203576 kb
Host smart-1f26c89e-3fa4-4164-8ba7-2b1a819ff24e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057308237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4057308237
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4263289662
Short name T654
Test name
Test status
Simulation time 29626208623 ps
CPU time 131.8 seconds
Started Jul 12 05:58:23 PM PDT 24
Finished Jul 12 06:01:04 PM PDT 24
Peak memory 211660 kb
Host smart-e0b5791e-0167-4921-b60c-3ea576965e24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4263289662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4263289662
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.4294419049
Short name T615
Test name
Test status
Simulation time 109533095 ps
CPU time 12.12 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 05:59:02 PM PDT 24
Peak memory 204584 kb
Host smart-b6198950-6114-4a3f-b12b-db5d49d8b441
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294419049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.4294419049
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.3338634495
Short name T161
Test name
Test status
Simulation time 1341828104 ps
CPU time 25.82 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 05:59:15 PM PDT 24
Peak memory 211660 kb
Host smart-2d66e44b-a6f1-474b-905d-e3966b578331
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3338634495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3338634495
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.4271411571
Short name T634
Test name
Test status
Simulation time 206758712 ps
CPU time 3.71 seconds
Started Jul 12 05:58:17 PM PDT 24
Finished Jul 12 05:58:49 PM PDT 24
Peak memory 203440 kb
Host smart-9d757466-97b0-4d8c-b9c7-562dabe80310
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4271411571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4271411571
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2905218266
Short name T377
Test name
Test status
Simulation time 11565352558 ps
CPU time 33.68 seconds
Started Jul 12 05:58:18 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 203728 kb
Host smart-1720a7cc-597d-468e-b6db-62725e201f28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905218266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2905218266
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1135749247
Short name T401
Test name
Test status
Simulation time 5207913401 ps
CPU time 30.11 seconds
Started Jul 12 05:58:16 PM PDT 24
Finished Jul 12 05:59:15 PM PDT 24
Peak memory 203544 kb
Host smart-09336148-c9c1-4dbc-99a2-ed672ca5bdf9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1135749247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1135749247
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1182555420
Short name T208
Test name
Test status
Simulation time 49716254 ps
CPU time 2.3 seconds
Started Jul 12 05:58:15 PM PDT 24
Finished Jul 12 05:58:45 PM PDT 24
Peak memory 203456 kb
Host smart-2a373823-f644-4944-8ce1-98791b56ce50
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182555420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1182555420
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1895287226
Short name T776
Test name
Test status
Simulation time 3841212209 ps
CPU time 132.71 seconds
Started Jul 12 05:58:21 PM PDT 24
Finished Jul 12 06:01:02 PM PDT 24
Peak memory 208028 kb
Host smart-aaf721ee-cd13-41a7-ae4f-625169f78d7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1895287226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1895287226
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.4268666246
Short name T892
Test name
Test status
Simulation time 3687467565 ps
CPU time 60.07 seconds
Started Jul 12 05:58:24 PM PDT 24
Finished Jul 12 05:59:54 PM PDT 24
Peak memory 204844 kb
Host smart-876fd4b8-1a4d-463e-b0f9-996d47bbcc5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4268666246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.4268666246
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2189684874
Short name T229
Test name
Test status
Simulation time 3496743032 ps
CPU time 274.19 seconds
Started Jul 12 05:58:25 PM PDT 24
Finished Jul 12 06:03:28 PM PDT 24
Peak memory 208748 kb
Host smart-a18f1041-4d26-4995-a10c-1909df0f385f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2189684874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.2189684874
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1348724467
Short name T33
Test name
Test status
Simulation time 352048591 ps
CPU time 127.2 seconds
Started Jul 12 05:58:26 PM PDT 24
Finished Jul 12 06:01:03 PM PDT 24
Peak memory 209860 kb
Host smart-6c934c18-5032-4559-9b19-93fa43e041dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1348724467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.1348724467
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.748759327
Short name T493
Test name
Test status
Simulation time 237601646 ps
CPU time 4 seconds
Started Jul 12 05:58:24 PM PDT 24
Finished Jul 12 05:58:58 PM PDT 24
Peak memory 211504 kb
Host smart-3554fbbe-ff05-4f50-9bcd-4324a56cb8ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748759327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.748759327
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1394239032
Short name T674
Test name
Test status
Simulation time 589852146 ps
CPU time 30.46 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:53 PM PDT 24
Peak memory 204780 kb
Host smart-fc8e2aa7-7e94-4fcf-9bb6-a451159926fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394239032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1394239032
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2216344811
Short name T203
Test name
Test status
Simulation time 73966947459 ps
CPU time 601.87 seconds
Started Jul 12 05:55:18 PM PDT 24
Finished Jul 12 06:05:23 PM PDT 24
Peak memory 211732 kb
Host smart-3b455d87-79b9-4087-b3f5-6abfa23ee2ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2216344811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.2216344811
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1338077666
Short name T9
Test name
Test status
Simulation time 5788510062 ps
CPU time 30.52 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:55 PM PDT 24
Peak memory 204052 kb
Host smart-334c4873-394e-46a8-bfa9-637934228b1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1338077666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1338077666
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.705186295
Short name T277
Test name
Test status
Simulation time 336008048 ps
CPU time 20.41 seconds
Started Jul 12 05:55:21 PM PDT 24
Finished Jul 12 05:55:43 PM PDT 24
Peak memory 203528 kb
Host smart-886cf0fa-0c4f-4556-8799-296849dd97a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=705186295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.705186295
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.2610043458
Short name T144
Test name
Test status
Simulation time 476771207 ps
CPU time 11.62 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 204612 kb
Host smart-f0bf7cdc-9975-44ac-9fcc-346ea2215173
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2610043458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2610043458
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1414091675
Short name T53
Test name
Test status
Simulation time 5495694324 ps
CPU time 22.23 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:47 PM PDT 24
Peak memory 211764 kb
Host smart-31e8db1a-5d9f-4854-b6a7-d75499008063
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414091675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1414091675
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1993515949
Short name T291
Test name
Test status
Simulation time 10611161833 ps
CPU time 104.75 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:57:06 PM PDT 24
Peak memory 205008 kb
Host smart-79a902b5-d926-411e-97bb-4e90975b8ef8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1993515949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1993515949
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1681820499
Short name T545
Test name
Test status
Simulation time 82181773 ps
CPU time 9.47 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 211684 kb
Host smart-99fa045b-b890-4283-a212-e460bbdfc72f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681820499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1681820499
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.3862900375
Short name T616
Test name
Test status
Simulation time 845501111 ps
CPU time 17.46 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:40 PM PDT 24
Peak memory 203952 kb
Host smart-c0eb162c-e8ef-4dc8-9f0b-4a9874b5c63a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3862900375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3862900375
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.133015368
Short name T572
Test name
Test status
Simulation time 36642042 ps
CPU time 1.96 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:24 PM PDT 24
Peak memory 203452 kb
Host smart-000ce47d-2d92-45e8-b258-188b30250223
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=133015368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.133015368
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2624849238
Short name T63
Test name
Test status
Simulation time 2417868078 ps
CPU time 22.89 seconds
Started Jul 12 05:55:17 PM PDT 24
Finished Jul 12 05:55:42 PM PDT 24
Peak memory 203520 kb
Host smart-e29e049d-8ba5-4b78-83db-f579ea9b0874
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2624849238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2624849238
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1126872770
Short name T812
Test name
Test status
Simulation time 27576516 ps
CPU time 2.12 seconds
Started Jul 12 05:55:19 PM PDT 24
Finished Jul 12 05:55:23 PM PDT 24
Peak memory 203464 kb
Host smart-3034be3e-bb02-4668-bbd5-684da8f46a2a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126872770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1126872770
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3627506851
Short name T523
Test name
Test status
Simulation time 4039669334 ps
CPU time 16.21 seconds
Started Jul 12 05:55:20 PM PDT 24
Finished Jul 12 05:55:39 PM PDT 24
Peak memory 204972 kb
Host smart-b79881da-5a4e-40f7-846a-230dc78f78ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3627506851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3627506851
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3522706628
Short name T272
Test name
Test status
Simulation time 719294569 ps
CPU time 65.95 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:56:31 PM PDT 24
Peak memory 205364 kb
Host smart-141c651a-6a13-49c3-9ccd-ada1c9108e22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3522706628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3522706628
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.600699624
Short name T117
Test name
Test status
Simulation time 8800785562 ps
CPU time 507.07 seconds
Started Jul 12 05:55:22 PM PDT 24
Finished Jul 12 06:03:51 PM PDT 24
Peak memory 221600 kb
Host smart-30cb6efb-7498-4996-a83c-c7737b7b5d43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=600699624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_
reset.600699624
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4170671162
Short name T258
Test name
Test status
Simulation time 442207583 ps
CPU time 123.56 seconds
Started Jul 12 05:55:22 PM PDT 24
Finished Jul 12 05:57:27 PM PDT 24
Peak memory 210280 kb
Host smart-ddf55f33-ef46-4343-827f-b77c237f15e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4170671162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.4170671162
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2269198463
Short name T418
Test name
Test status
Simulation time 3347626423 ps
CPU time 27.63 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:52 PM PDT 24
Peak memory 211724 kb
Host smart-33504c85-35a9-4d96-b219-b6e3e5d0e4bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2269198463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2269198463
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3813643122
Short name T723
Test name
Test status
Simulation time 1290934613 ps
CPU time 34.01 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 211680 kb
Host smart-cbe77e11-a824-4166-841e-b24ee7d23045
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3813643122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3813643122
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1201273151
Short name T72
Test name
Test status
Simulation time 44645502325 ps
CPU time 241.27 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:59:26 PM PDT 24
Peak memory 211712 kb
Host smart-6c55f8e1-d424-44df-bdf5-e7ffde0cbfae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1201273151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.1201273151
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3282969029
Short name T135
Test name
Test status
Simulation time 2707943780 ps
CPU time 20.15 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:46 PM PDT 24
Peak memory 203576 kb
Host smart-0bcabfbd-110c-4e44-b935-69bc6a0c1a03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3282969029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3282969029
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.3496186259
Short name T216
Test name
Test status
Simulation time 652341238 ps
CPU time 7.99 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:55:37 PM PDT 24
Peak memory 203464 kb
Host smart-555db420-f2f0-43c9-9ef6-11d1d80e2348
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3496186259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3496186259
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.2847593912
Short name T736
Test name
Test status
Simulation time 173250369 ps
CPU time 9.41 seconds
Started Jul 12 05:55:26 PM PDT 24
Finished Jul 12 05:55:36 PM PDT 24
Peak memory 211664 kb
Host smart-b7592fbb-bd15-4e02-9d4a-351b7bb2b57e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2847593912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2847593912
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2239697642
Short name T774
Test name
Test status
Simulation time 39939166407 ps
CPU time 233.99 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:59:20 PM PDT 24
Peak memory 204972 kb
Host smart-cf606096-d410-4e65-a7c3-93f4ed4b1b38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239697642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2239697642
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3887026531
Short name T404
Test name
Test status
Simulation time 26955108132 ps
CPU time 208.91 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:58:54 PM PDT 24
Peak memory 211744 kb
Host smart-1ad46a46-e9a8-4531-8e75-6940d3b1f10a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3887026531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3887026531
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.929142787
Short name T285
Test name
Test status
Simulation time 554307112 ps
CPU time 18.62 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:44 PM PDT 24
Peak memory 211612 kb
Host smart-79dc02f5-ae58-4940-841d-f903a4e74787
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929142787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.929142787
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.3416965230
Short name T195
Test name
Test status
Simulation time 2082848040 ps
CPU time 22.09 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 203444 kb
Host smart-2d73d66f-c302-4682-bc80-37d7b3069209
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3416965230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3416965230
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.2857155234
Short name T551
Test name
Test status
Simulation time 177881093 ps
CPU time 3.69 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:29 PM PDT 24
Peak memory 203480 kb
Host smart-14b9eeae-d68f-4bf0-8ea4-5fd5cec63dbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2857155234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2857155234
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.229480346
Short name T279
Test name
Test status
Simulation time 18102638867 ps
CPU time 33.84 seconds
Started Jul 12 05:55:23 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 203516 kb
Host smart-02ec5c6b-4823-4854-b6e2-0b11607417d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=229480346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.229480346
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1235033878
Short name T762
Test name
Test status
Simulation time 4636789051 ps
CPU time 32.15 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:58 PM PDT 24
Peak memory 203520 kb
Host smart-4dcb24ed-c214-498c-ad06-3a37f1cd41ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1235033878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1235033878
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3830569478
Short name T751
Test name
Test status
Simulation time 46876933 ps
CPU time 2.38 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:28 PM PDT 24
Peak memory 203484 kb
Host smart-58eca954-3e15-47b1-a73a-a0c571cc2e6f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830569478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3830569478
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.191522749
Short name T423
Test name
Test status
Simulation time 1615286907 ps
CPU time 76.8 seconds
Started Jul 12 05:55:26 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 205900 kb
Host smart-48a9565f-2cb0-4b13-b54d-16459160449a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=191522749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.191522749
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.191526753
Short name T581
Test name
Test status
Simulation time 3860626182 ps
CPU time 72.48 seconds
Started Jul 12 05:55:25 PM PDT 24
Finished Jul 12 05:56:38 PM PDT 24
Peak memory 205356 kb
Host smart-1bd360c0-eedc-4fae-87eb-aa1d7b6c981d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=191526753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.191526753
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1539891065
Short name T19
Test name
Test status
Simulation time 3587774632 ps
CPU time 300.89 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 06:00:27 PM PDT 24
Peak memory 210832 kb
Host smart-2e5ec95b-3009-4a6a-a634-47ecdf372703
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1539891065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.1539891065
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.494041648
Short name T383
Test name
Test status
Simulation time 183838664 ps
CPU time 49.8 seconds
Started Jul 12 05:55:25 PM PDT 24
Finished Jul 12 05:56:16 PM PDT 24
Peak memory 206868 kb
Host smart-b69cdf45-6bec-4c2a-8b29-f3bf33b7eec7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=494041648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese
t_error.494041648
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3907846416
Short name T735
Test name
Test status
Simulation time 90343416 ps
CPU time 9.21 seconds
Started Jul 12 05:55:24 PM PDT 24
Finished Jul 12 05:55:35 PM PDT 24
Peak memory 205020 kb
Host smart-746a5dd4-866d-4e0c-b6f7-d7f608356b8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3907846416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3907846416
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.711948598
Short name T61
Test name
Test status
Simulation time 1740537103 ps
CPU time 21.68 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:55:51 PM PDT 24
Peak memory 211688 kb
Host smart-aba7762d-ec8e-44c5-95ab-4f18a613efbd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=711948598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.711948598
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2672419715
Short name T207
Test name
Test status
Simulation time 1756120922 ps
CPU time 26.7 seconds
Started Jul 12 05:55:30 PM PDT 24
Finished Jul 12 05:55:58 PM PDT 24
Peak memory 203500 kb
Host smart-970676cb-dc95-451b-97cf-7cc52cca95d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2672419715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2672419715
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.1417833559
Short name T537
Test name
Test status
Simulation time 1621346781 ps
CPU time 15.14 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:55:45 PM PDT 24
Peak memory 203492 kb
Host smart-e8cb1ea1-4da6-437d-8c3e-342d78058edf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1417833559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1417833559
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.644163922
Short name T45
Test name
Test status
Simulation time 1180278039 ps
CPU time 16.22 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:55:47 PM PDT 24
Peak memory 211640 kb
Host smart-3e720f51-c258-4ce0-9131-fca2c73f1239
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=644163922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.644163922
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.4108427254
Short name T231
Test name
Test status
Simulation time 31902858552 ps
CPU time 182.66 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:58:32 PM PDT 24
Peak memory 205228 kb
Host smart-6d93ba30-02a9-4472-be2b-4b817a0dc3a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108427254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4108427254
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2206252690
Short name T143
Test name
Test status
Simulation time 7325056810 ps
CPU time 27.9 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 211708 kb
Host smart-43b77219-4409-4e1f-a48a-3a502a2c07a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2206252690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2206252690
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1617082571
Short name T159
Test name
Test status
Simulation time 327688185 ps
CPU time 21.17 seconds
Started Jul 12 05:55:26 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 211616 kb
Host smart-9e191f94-8d15-4b97-ac41-5438a139c433
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617082571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1617082571
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2059493581
Short name T391
Test name
Test status
Simulation time 2520273991 ps
CPU time 30.83 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 211736 kb
Host smart-90f1d8c2-91ba-4ce0-88c3-5e913f57d609
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2059493581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2059493581
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.18805668
Short name T853
Test name
Test status
Simulation time 204537808 ps
CPU time 3.86 seconds
Started Jul 12 05:55:26 PM PDT 24
Finished Jul 12 05:55:31 PM PDT 24
Peak memory 203468 kb
Host smart-a8e459fe-fe5d-4071-981a-09509ccb4666
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18805668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.18805668
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3347036608
Short name T55
Test name
Test status
Simulation time 11972811753 ps
CPU time 31.65 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:56:01 PM PDT 24
Peak memory 203520 kb
Host smart-8f604071-34ed-4fa2-9136-feb2afb6585e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347036608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3347036608
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1709743829
Short name T478
Test name
Test status
Simulation time 8868596323 ps
CPU time 27.92 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:55:58 PM PDT 24
Peak memory 203536 kb
Host smart-9ef7437e-f518-45ad-a4f9-ad5130f8ca27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1709743829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1709743829
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2411663824
Short name T871
Test name
Test status
Simulation time 30532310 ps
CPU time 2.23 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:55:30 PM PDT 24
Peak memory 203480 kb
Host smart-e48ecbb3-1c64-400d-9a21-b490347f9111
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411663824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2411663824
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3406631775
Short name T757
Test name
Test status
Simulation time 1756867620 ps
CPU time 160.15 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:58:10 PM PDT 24
Peak memory 210080 kb
Host smart-46dfc5e0-c38f-4af5-ac34-75dddcd0baf4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3406631775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3406631775
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.273564637
Short name T330
Test name
Test status
Simulation time 216180103 ps
CPU time 22.1 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:55:52 PM PDT 24
Peak memory 203472 kb
Host smart-fe457ba7-db1c-4a52-bca7-5e95b0eb250e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273564637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.273564637
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3305497589
Short name T610
Test name
Test status
Simulation time 2753599220 ps
CPU time 170.96 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:58:25 PM PDT 24
Peak memory 208052 kb
Host smart-cbfec1ff-b284-442e-9791-b9158208b4d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3305497589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.3305497589
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2014534980
Short name T328
Test name
Test status
Simulation time 7565031195 ps
CPU time 140.14 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 209668 kb
Host smart-418a54c8-dbbe-4322-8983-d632ab891393
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2014534980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.2014534980
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3259083479
Short name T65
Test name
Test status
Simulation time 69344665 ps
CPU time 2.16 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:55:32 PM PDT 24
Peak memory 203496 kb
Host smart-30cc4cfb-7993-4415-b8bd-55a437618822
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3259083479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3259083479
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.4277372329
Short name T137
Test name
Test status
Simulation time 2884786170 ps
CPU time 76.44 seconds
Started Jul 12 05:55:26 PM PDT 24
Finished Jul 12 05:56:44 PM PDT 24
Peak memory 211684 kb
Host smart-ed07e876-e0dc-44b9-8580-5470f130b45e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4277372329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.4277372329
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3162959890
Short name T228
Test name
Test status
Simulation time 78121274252 ps
CPU time 449.87 seconds
Started Jul 12 05:55:35 PM PDT 24
Finished Jul 12 06:03:07 PM PDT 24
Peak memory 211728 kb
Host smart-5e78d50a-9f5a-4647-b11b-da3d117adf88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3162959890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.3162959890
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.4140640981
Short name T482
Test name
Test status
Simulation time 1591728847 ps
CPU time 22.11 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:55:55 PM PDT 24
Peak memory 203864 kb
Host smart-c4a6483e-bf25-459e-8af6-2e177503a900
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4140640981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4140640981
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.424103627
Short name T767
Test name
Test status
Simulation time 237551145 ps
CPU time 8.35 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:55:37 PM PDT 24
Peak memory 203440 kb
Host smart-b605707c-484c-4361-a697-7501acec3343
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=424103627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.424103627
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.3017038888
Short name T770
Test name
Test status
Simulation time 7183664086 ps
CPU time 43.99 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:56:20 PM PDT 24
Peak memory 211712 kb
Host smart-542886a2-6d1b-43b9-a373-f715a3668ae4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3017038888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3017038888
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1842802802
Short name T791
Test name
Test status
Simulation time 242246278566 ps
CPU time 342.67 seconds
Started Jul 12 05:55:35 PM PDT 24
Finished Jul 12 06:01:20 PM PDT 24
Peak memory 211736 kb
Host smart-3fcc9c4f-e1ce-429f-b585-107c3f8ffaf6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842802802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1842802802
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3170171732
Short name T600
Test name
Test status
Simulation time 3888461537 ps
CPU time 22.46 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:55:56 PM PDT 24
Peak memory 203544 kb
Host smart-d499431e-ff52-422d-b778-8d31d141de1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3170171732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3170171732
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.207756332
Short name T860
Test name
Test status
Simulation time 35101075 ps
CPU time 3.81 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:55:35 PM PDT 24
Peak memory 211604 kb
Host smart-783d83ac-aa9c-41be-9974-b49adf468581
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207756332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.207756332
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2129902258
Short name T296
Test name
Test status
Simulation time 155544444 ps
CPU time 11.39 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:55:39 PM PDT 24
Peak memory 203688 kb
Host smart-0ab6f1e2-3542-4443-892b-1c6cd833c1bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2129902258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2129902258
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.2597776993
Short name T748
Test name
Test status
Simulation time 46234664 ps
CPU time 2.24 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:55:36 PM PDT 24
Peak memory 203468 kb
Host smart-db29635e-0394-4515-bb3d-a78026f1a255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2597776993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2597776993
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.4098706165
Short name T312
Test name
Test status
Simulation time 13040868600 ps
CPU time 31.14 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:56:00 PM PDT 24
Peak memory 203544 kb
Host smart-b82101db-be3e-4ed1-9935-a71e13b05a59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098706165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4098706165
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2804151025
Short name T841
Test name
Test status
Simulation time 14353918493 ps
CPU time 37.19 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 05:56:06 PM PDT 24
Peak memory 203532 kb
Host smart-34aab6c3-7075-47fb-9959-f5de3da708d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2804151025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2804151025
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.4075371120
Short name T731
Test name
Test status
Simulation time 39742495 ps
CPU time 2.58 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:55:32 PM PDT 24
Peak memory 203480 kb
Host smart-713a099a-6780-4345-84b5-dc21ad09fc38
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075371120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.4075371120
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.4126178181
Short name T510
Test name
Test status
Simulation time 234475925 ps
CPU time 32.72 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:56:02 PM PDT 24
Peak memory 206328 kb
Host smart-b8c8ecef-e63f-4036-b045-fb5a1e2021c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4126178181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4126178181
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.113200166
Short name T319
Test name
Test status
Simulation time 17368238254 ps
CPU time 189.61 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:58:41 PM PDT 24
Peak memory 209908 kb
Host smart-aaa32beb-7781-48c0-b39f-704f464c66e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113200166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.113200166
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2898077302
Short name T421
Test name
Test status
Simulation time 1482383057 ps
CPU time 280.67 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 06:00:09 PM PDT 24
Peak memory 211684 kb
Host smart-27142372-d336-4b57-87f0-c491117e74f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2898077302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.2898077302
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1147536337
Short name T883
Test name
Test status
Simulation time 26307095 ps
CPU time 1.94 seconds
Started Jul 12 05:55:30 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 203468 kb
Host smart-07a92eca-5ac0-4cda-be93-f68f1bfd3d57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1147536337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1147536337
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.842055756
Short name T810
Test name
Test status
Simulation time 121493727 ps
CPU time 8.03 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:55:43 PM PDT 24
Peak memory 203496 kb
Host smart-481e932b-d6be-40ec-aad5-949404846247
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=842055756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.842055756
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.890352315
Short name T499
Test name
Test status
Simulation time 476237249 ps
CPU time 15.75 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:55:46 PM PDT 24
Peak memory 203516 kb
Host smart-81a94d04-ad27-4bd4-811e-39f132e81c63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=890352315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.890352315
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.3554239047
Short name T284
Test name
Test status
Simulation time 2635909474 ps
CPU time 25.91 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:56:02 PM PDT 24
Peak memory 203644 kb
Host smart-03eae807-79fc-4bf5-97eb-7fce4ec4aabf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3554239047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3554239047
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.121243843
Short name T737
Test name
Test status
Simulation time 439438310 ps
CPU time 14.73 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 211620 kb
Host smart-1bcc02fc-1a5c-43c3-a9fb-6535c6f02c20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=121243843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.121243843
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2506236887
Short name T577
Test name
Test status
Simulation time 4276979142 ps
CPU time 13.8 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:55:48 PM PDT 24
Peak memory 203540 kb
Host smart-59e83209-a6ab-41a7-aa90-39fd2e4d208e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506236887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2506236887
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.24723785
Short name T145
Test name
Test status
Simulation time 24000777678 ps
CPU time 125.93 seconds
Started Jul 12 05:55:32 PM PDT 24
Finished Jul 12 05:57:41 PM PDT 24
Peak memory 211724 kb
Host smart-0660313c-c058-4e37-956e-7e22b6ca1ca4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=24723785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.24723785
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3338588703
Short name T637
Test name
Test status
Simulation time 440121146 ps
CPU time 27.45 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:56:03 PM PDT 24
Peak memory 205200 kb
Host smart-e32b8310-1932-4b1b-a798-6b4b6396fde8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338588703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3338588703
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.150825442
Short name T287
Test name
Test status
Simulation time 1337093597 ps
CPU time 27.2 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:56:03 PM PDT 24
Peak memory 203556 kb
Host smart-dde90994-c9d5-43cf-9847-95ca56794817
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=150825442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.150825442
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.946528944
Short name T248
Test name
Test status
Simulation time 23788590 ps
CPU time 2.06 seconds
Started Jul 12 05:55:29 PM PDT 24
Finished Jul 12 05:55:32 PM PDT 24
Peak memory 203468 kb
Host smart-724fabf0-005d-48bb-b580-9a0d7ba3fdf6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=946528944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.946528944
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.96128301
Short name T669
Test name
Test status
Simulation time 4650543680 ps
CPU time 25.51 seconds
Started Jul 12 05:55:34 PM PDT 24
Finished Jul 12 05:56:02 PM PDT 24
Peak memory 203524 kb
Host smart-c29a4746-98a0-421b-bbf4-39bcba5c3f3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=96128301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.96128301
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.4083412852
Short name T239
Test name
Test status
Simulation time 6248474549 ps
CPU time 29.48 seconds
Started Jul 12 05:55:28 PM PDT 24
Finished Jul 12 05:55:59 PM PDT 24
Peak memory 203508 kb
Host smart-b73d1d1b-4434-48fe-862d-fda3b4b269eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4083412852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4083412852
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.512771258
Short name T579
Test name
Test status
Simulation time 127111496 ps
CPU time 2.1 seconds
Started Jul 12 05:55:26 PM PDT 24
Finished Jul 12 05:55:29 PM PDT 24
Peak memory 203484 kb
Host smart-13402534-7041-4397-823b-d1911958b4bc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512771258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.512771258
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.807699145
Short name T106
Test name
Test status
Simulation time 3950751502 ps
CPU time 109.02 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:57:22 PM PDT 24
Peak memory 206432 kb
Host smart-57bb7fc9-cff6-4674-89b1-bc9229172a96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=807699145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.807699145
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3182398470
Short name T327
Test name
Test status
Simulation time 9319258220 ps
CPU time 146.36 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:58:02 PM PDT 24
Peak memory 205772 kb
Host smart-c6f10b5c-5890-469a-97b3-ab20ef7322bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3182398470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3182398470
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3356317366
Short name T508
Test name
Test status
Simulation time 2246259202 ps
CPU time 404.43 seconds
Started Jul 12 05:55:27 PM PDT 24
Finished Jul 12 06:02:13 PM PDT 24
Peak memory 219940 kb
Host smart-9926aaa1-a778-47ab-8a39-20f8259dd027
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3356317366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.3356317366
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3638933880
Short name T828
Test name
Test status
Simulation time 2961484265 ps
CPU time 202.99 seconds
Started Jul 12 05:55:31 PM PDT 24
Finished Jul 12 05:58:57 PM PDT 24
Peak memory 211740 kb
Host smart-55614205-2a17-4f52-ace0-94c6cd6e6e87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3638933880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.3638933880
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.549787699
Short name T8
Test name
Test status
Simulation time 445316011 ps
CPU time 13.55 seconds
Started Jul 12 05:55:33 PM PDT 24
Finished Jul 12 05:55:49 PM PDT 24
Peak memory 211744 kb
Host smart-376e637b-a432-4e8c-aef8-5d68be6a2a0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=549787699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.549787699
Directory /workspace/9.xbar_unmapped_addr/latest
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