Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1831	1			T11	2		T30	9		T41	9
all_values[1]	1797	1			T11	1		T13	4		T30	7
all_values[2]	1865	1			T11	2		T13	1		T30	10
all_values[3]	1711	1			T11	5		T13	3		T30	9
all_values[4]	1764	1			T11	3		T13	4		T30	9
all_values[5]	1781	1			T11	2		T13	3		T30	9
all_values[6]	1859	1			T11	7		T13	1		T30	14
all_values[7]	1780	1			T11	5		T30	13		T41	11
all_values[8]	1785	1			T11	3		T13	1		T30	12
all_values[9]	1802	1			T11	3		T13	1		T30	11
all_values[10]	1764	1			T11	4		T13	1		T30	14
all_values[11]	1797	1			T11	1		T30	11		T41	12
all_values[12]	1846	1			T11	1		T13	1		T30	9
all_values[13]	1793	1			T11	3		T30	12		T41	14
all_values[14]	1882	1			T13	1		T30	17		T41	16
all_values[15]	1795	1			T11	5		T13	2		T30	7
all_values[16]	1746	1			T11	2		T13	2		T30	8
all_values[17]	1796	1			T11	2		T13	2		T30	12
all_values[18]	1739	1			T11	5		T13	2		T30	11
all_values[19]	1759	1			T11	1		T13	4		T30	6
all_values[20]	1817	1			T11	3		T13	3		T30	11
all_values[21]	1810	1			T13	2		T30	12		T41	9
all_values[22]	1767	1			T11	3		T13	2		T30	4
all_values[23]	1828	1			T11	1		T13	2		T30	12
all_values[24]	1761	1			T11	3		T30	5		T41	10
all_values[25]	1796	1			T11	5		T13	5		T30	11
all_values[26]	1791	1			T11	6		T30	7		T41	16
all_values[27]	1726	1			T11	2		T13	2		T30	8
all_values[28]	1786	1			T11	3		T13	4		T30	9
all_values[29]	1802	1			T11	4		T13	3		T30	6
all_values[30]	1719	1			T11	3		T30	11		T41	17
all_values[31]	1853	1			T11	4		T13	2		T30	17
all_values[32]	1734	1			T11	2		T30	13		T41	13
all_values[33]	1786	1			T11	4		T13	2		T30	8
all_values[34]	1773	1			T11	3		T30	10		T41	5
all_values[35]	1823	1			T11	2		T30	11		T41	13
all_values[36]	1760	1			T11	2		T30	10		T41	18
all_values[37]	1733	1			T11	2		T13	3		T30	8
all_values[38]	1699	1			T11	1		T30	11		T41	8
all_values[39]	1771	1			T11	3		T13	2		T30	15
all_values[40]	1822	1			T11	2		T13	5		T30	10
all_values[41]	1768	1			T11	3		T30	12		T41	12
all_values[42]	1787	1			T11	4		T13	3		T30	9
all_values[43]	1744	1			T11	2		T13	1		T30	12
all_values[44]	1814	1			T11	6		T13	3		T30	12
all_values[45]	1761	1			T11	1		T30	5		T41	14
all_values[46]	1806	1			T11	5		T13	4		T30	8
all_values[47]	1810	1			T11	3		T30	10		T41	12
all_values[48]	1801	1			T11	7		T13	2		T30	7
all_values[49]	1771	1			T11	2		T30	9		T41	12
all_values[50]	1769	1			T11	5		T13	3		T30	9
all_values[51]	1671	1			T11	2		T13	3		T30	8
all_values[52]	1841	1			T11	3		T13	2		T30	8
all_values[53]	1804	1			T11	4		T30	11		T41	16
all_values[54]	1795	1			T11	5		T30	9		T41	5
all_values[55]	1764	1			T11	7		T30	11		T41	5
all_values[56]	1780	1			T11	4		T13	1		T30	10
all_values[57]	1858	1			T11	4		T13	1		T30	5
all_values[58]	1802	1			T11	6		T13	1		T30	9
all_values[59]	1842	1			T11	3		T13	1		T30	15
all_values[60]	1774	1			T11	3		T13	2		T30	16
all_values[61]	1744	1			T11	1		T13	2		T30	11
all_values[62]	1769	1			T11	5		T13	1		T30	8
all_values[63]	1765	1			T11	2		T13	1		T30	8