Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 458 1 T2 1 T9 1 T12 12
all_values[1] 486 1 T2 1 T9 1 T12 6
all_values[2] 469 1 T2 1 T12 8 T15 3
all_values[3] 533 1 T2 2 T9 3 T12 13
all_values[4] 474 1 T9 1 T12 5 T15 5
all_values[5] 464 1 T12 6 T15 1 T17 3
all_values[6] 463 1 T9 1 T12 9 T17 1
all_values[7] 489 1 T2 2 T12 11 T15 4
all_values[8] 476 1 T12 10 T15 4 T17 5
all_values[9] 479 1 T9 2 T12 9 T15 1
all_values[10] 463 1 T12 7 T15 6 T17 5
all_values[11] 468 1 T9 1 T12 11 T15 3
all_values[12] 471 1 T12 5 T15 5 T17 2
all_values[13] 466 1 T2 2 T12 10 T15 6
all_values[14] 472 1 T9 1 T12 1 T15 3
all_values[15] 481 1 T2 1 T12 6 T15 5
all_values[16] 459 1 T2 1 T12 6 T15 4
all_values[17] 473 1 T2 1 T9 2 T12 6
all_values[18] 491 1 T2 2 T9 1 T12 4
all_values[19] 514 1 T2 1 T9 1 T10 1
all_values[20] 426 1 T12 4 T15 6 T17 3
all_values[21] 504 1 T9 1 T12 11 T15 4
all_values[22] 450 1 T9 1 T10 1 T12 7
all_values[23] 461 1 T12 9 T15 5 T17 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%