Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1647	1			T12	45		T15	8		T17	17
all_values[1]	1703	1			T10	5		T12	22		T15	8
all_values[2]	1688	1			T10	8		T12	27		T15	10
all_values[3]	1616	1			T10	4		T12	27		T15	14
all_values[4]	1736	1			T10	4		T12	25		T15	14
all_values[5]	1696	1			T10	7		T12	29		T15	15
all_values[6]	1718	1			T10	3		T12	32		T15	14
all_values[7]	1728	1			T10	4		T12	36		T15	19
all_values[8]	1659	1			T10	3		T12	34		T15	12
all_values[9]	1673	1			T10	10		T12	24		T15	18
all_values[10]	1661	1			T10	6		T12	34		T15	16
all_values[11]	1678	1			T10	4		T12	41		T15	16
all_values[12]	1703	1			T10	2		T12	34		T15	9
all_values[13]	1677	1			T10	4		T12	32		T15	14
all_values[14]	1620	1			T10	3		T12	35		T15	13
all_values[15]	1733	1			T10	6		T12	27		T15	25
all_values[16]	1708	1			T10	2		T12	37		T15	23
all_values[17]	1648	1			T10	4		T12	34		T15	13
all_values[18]	1666	1			T10	7		T12	31		T15	19
all_values[19]	1646	1			T10	3		T12	30		T15	9
all_values[20]	1699	1			T10	3		T12	41		T15	13
all_values[21]	1670	1			T10	1		T12	31		T15	16
all_values[22]	1630	1			T12	20		T15	15		T17	17
all_values[23]	1650	1			T10	4		T12	37		T15	10
all_values[24]	1644	1			T10	4		T12	32		T15	9
all_values[25]	1677	1			T10	2		T12	30		T15	12
all_values[26]	1736	1			T10	1		T12	34		T15	17
all_values[27]	1654	1			T10	4		T12	32		T15	9
all_values[28]	1729	1			T10	5		T12	35		T15	15
all_values[29]	1736	1			T10	5		T12	35		T15	14
all_values[30]	1705	1			T10	3		T12	40		T15	12
all_values[31]	1731	1			T10	5		T12	33		T15	12
all_values[32]	1706	1			T10	4		T12	38		T15	14
all_values[33]	1658	1			T10	6		T12	29		T15	16
all_values[34]	1647	1			T10	6		T12	33		T15	16
all_values[35]	1650	1			T10	6		T12	33		T15	8
all_values[36]	1688	1			T10	3		T12	30		T15	16
all_values[37]	1579	1			T10	6		T12	32		T15	15
all_values[38]	1647	1			T10	3		T12	26		T15	17
all_values[39]	1624	1			T10	6		T12	29		T15	19
all_values[40]	1671	1			T10	2		T12	26		T15	9
all_values[41]	1605	1			T10	3		T12	25		T15	9
all_values[42]	1714	1			T10	3		T12	41		T15	12
all_values[43]	1730	1			T12	33		T15	15		T17	17
all_values[44]	1622	1			T10	3		T12	29		T15	20
all_values[45]	1707	1			T10	3		T12	38		T15	11
all_values[46]	1685	1			T10	6		T12	33		T15	11
all_values[47]	1666	1			T10	3		T12	37		T15	12
all_values[48]	1697	1			T10	1		T12	25		T15	18
all_values[49]	1661	1			T10	3		T12	30		T15	12
all_values[50]	1674	1			T10	6		T12	31		T15	16
all_values[51]	1770	1			T10	5		T12	32		T15	18
all_values[52]	1623	1			T10	6		T12	29		T15	5
all_values[53]	1679	1			T10	5		T12	32		T15	16
all_values[54]	1752	1			T10	3		T12	18		T15	19
all_values[55]	1714	1			T10	1		T12	31		T15	14
all_values[56]	1657	1			T10	2		T12	28		T15	11
all_values[57]	1707	1			T10	8		T12	35		T15	15
all_values[58]	1714	1			T10	4		T12	23		T15	17
all_values[59]	1639	1			T10	5		T12	38		T15	16
all_values[60]	1673	1			T10	2		T12	34		T15	16
all_values[61]	1747	1			T10	2		T12	40		T15	19
all_values[62]	1681	1			T10	4		T12	22		T15	15
all_values[63]	1689	1			T10	5		T12	41		T15	14