Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1877	1			T9	2		T15	2		T157	24
all_values[1]	1928	1			T9	3		T15	4		T157	27
all_values[2]	1862	1			T9	4		T157	21		T32	12
all_values[3]	1862	1			T9	5		T15	3		T157	22
all_values[4]	1886	1			T9	1		T15	9		T157	27
all_values[5]	1943	1			T9	5		T15	1		T157	20
all_values[6]	1968	1			T9	4		T15	4		T157	10
all_values[7]	1847	1			T9	3		T15	6		T157	9
all_values[8]	1879	1			T9	2		T15	2		T157	32
all_values[9]	1891	1			T9	2		T15	2		T157	23
all_values[10]	1979	1			T15	3		T157	13		T32	13
all_values[11]	1835	1			T9	2		T15	3		T157	17
all_values[12]	1905	1			T15	8		T157	18		T32	11
all_values[13]	1911	1			T9	4		T15	4		T157	26
all_values[14]	1847	1			T9	4		T15	4		T157	19
all_values[15]	1820	1			T9	4		T15	2		T157	16
all_values[16]	1902	1			T9	5		T15	2		T157	23
all_values[17]	1880	1			T9	2		T15	5		T157	17
all_values[18]	1873	1			T9	4		T15	4		T157	20
all_values[19]	1926	1			T9	3		T15	6		T157	14
all_values[20]	1940	1			T9	5		T15	3		T157	13
all_values[21]	1905	1			T9	1		T15	3		T157	28
all_values[22]	1875	1			T9	2		T15	6		T157	13
all_values[23]	1841	1			T9	5		T15	2		T157	15
all_values[24]	1881	1			T9	1		T15	5		T157	15
all_values[25]	1869	1			T9	3		T15	1		T157	23
all_values[26]	1932	1			T9	2		T15	4		T157	27
all_values[27]	1869	1			T9	3		T157	14		T32	12
all_values[28]	1901	1			T9	4		T15	6		T157	23
all_values[29]	1963	1			T9	4		T15	1		T157	24
all_values[30]	1876	1			T9	3		T15	2		T157	23
all_values[31]	1939	1			T9	6		T15	3		T157	20
all_values[32]	1899	1			T9	1		T15	3		T157	15
all_values[33]	1895	1			T9	4		T15	5		T157	19
all_values[34]	1947	1			T9	1		T15	8		T157	16
all_values[35]	1933	1			T9	2		T15	7		T157	27
all_values[36]	1956	1			T9	2		T15	5		T157	21
all_values[37]	1917	1			T9	2		T15	3		T157	23
all_values[38]	1968	1			T9	1		T15	4		T157	31
all_values[39]	1885	1			T9	1		T15	6		T157	16
all_values[40]	1952	1			T9	3		T15	2		T157	20
all_values[41]	1841	1			T15	5		T157	17		T32	7
all_values[42]	1873	1			T9	3		T15	3		T157	14
all_values[43]	1964	1			T9	4		T15	2		T157	22
all_values[44]	1834	1			T9	3		T15	4		T157	24
all_values[45]	1889	1			T9	1		T15	6		T157	21
all_values[46]	1909	1			T9	1		T15	3		T157	17
all_values[47]	1876	1			T9	7		T15	4		T157	31
all_values[48]	1912	1			T9	1		T15	4		T157	20
all_values[49]	1883	1			T9	5		T15	5		T157	26
all_values[50]	1884	1			T9	2		T15	6		T157	20
all_values[51]	1878	1			T9	2		T15	3		T157	22
all_values[52]	1899	1			T9	4		T15	6		T157	13
all_values[53]	1843	1			T9	1		T15	3		T157	20
all_values[54]	1846	1			T9	2		T15	3		T157	18
all_values[55]	1829	1			T9	2		T15	6		T157	23
all_values[56]	1953	1			T9	3		T15	2		T157	23
all_values[57]	1852	1			T15	7		T157	20		T32	12
all_values[58]	1913	1			T9	1		T15	1		T157	18
all_values[59]	1906	1			T15	3		T157	28		T32	9
all_values[60]	1884	1			T9	1		T15	4		T157	10
all_values[61]	1853	1			T9	4		T15	5		T157	22
all_values[62]	1944	1			T9	2		T15	5		T157	25
all_values[63]	1938	1			T9	3		T15	1		T157	15