Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1668	1			T11	1		T13	1		T15	5
all_values[1]	1651	1			T7	1		T11	3		T13	3
all_values[2]	1711	1			T11	2		T13	3		T15	11
all_values[3]	1712	1			T11	6		T13	3		T15	8
all_values[4]	1579	1			T3	1		T11	3		T13	2
all_values[5]	1638	1			T7	4		T11	4		T13	6
all_values[6]	1618	1			T11	3		T13	2		T15	7
all_values[7]	1601	1			T3	1		T11	3		T13	2
all_values[8]	1629	1			T3	1		T11	3		T13	5
all_values[9]	1655	1			T3	1		T7	1		T11	2
all_values[10]	1679	1			T11	4		T13	3		T15	3
all_values[11]	1577	1			T7	2		T11	4		T13	3
all_values[12]	1749	1			T3	1		T7	1		T11	4
all_values[13]	1621	1			T7	1		T11	6		T15	4
all_values[14]	1689	1			T11	1		T13	4		T15	6
all_values[15]	1715	1			T7	1		T13	4		T15	7
all_values[16]	1742	1			T11	2		T13	1		T15	9
all_values[17]	1615	1			T11	8		T13	3		T15	5
all_values[18]	1639	1			T11	3		T13	2		T15	8
all_values[19]	1681	1			T7	1		T11	5		T13	5
all_values[20]	1627	1			T3	1		T7	1		T11	7
all_values[21]	1600	1			T11	5		T13	3		T15	5
all_values[22]	1626	1			T3	1		T11	2		T13	7
all_values[23]	1680	1			T11	2		T13	2		T15	4
all_values[24]	1670	1			T3	1		T11	1		T13	2
all_values[25]	1694	1			T11	3		T13	2		T15	12
all_values[26]	1629	1			T3	1		T7	1		T11	4
all_values[27]	1677	1			T3	1		T7	1		T11	4
all_values[28]	1614	1			T11	1		T13	3		T15	9
all_values[29]	1660	1			T11	5		T13	4		T15	7
all_values[30]	1690	1			T3	1		T11	7		T13	1
all_values[31]	1618	1			T11	5		T13	4		T15	4
all_values[32]	1674	1			T11	2		T13	1		T15	9
all_values[33]	1670	1			T3	1		T7	1		T11	2
all_values[34]	1623	1			T11	2		T13	4		T15	7
all_values[35]	1610	1			T11	3		T13	3		T15	4
all_values[36]	1641	1			T11	1		T13	1		T15	7
all_values[37]	1628	1			T3	1		T11	3		T13	1
all_values[38]	1582	1			T11	2		T13	3		T15	7
all_values[39]	1660	1			T11	3		T13	3		T15	7
all_values[40]	1617	1			T11	4		T13	4		T15	11
all_values[41]	1660	1			T11	5		T13	1		T15	2
all_values[42]	1620	1			T11	3		T13	2		T15	6
all_values[43]	1645	1			T3	1		T11	3		T13	2
all_values[44]	1621	1			T11	8		T13	3		T15	6
all_values[45]	1651	1			T11	3		T13	7		T15	7
all_values[46]	1640	1			T11	2		T13	1		T15	8
all_values[47]	1632	1			T11	2		T13	2		T15	8
all_values[48]	1738	1			T11	3		T13	2		T15	7
all_values[49]	1613	1			T11	1		T13	1		T15	12
all_values[50]	1639	1			T11	7		T15	6		T16	13
all_values[51]	1677	1			T11	3		T13	2		T15	7
all_values[52]	1577	1			T11	4		T13	3		T15	10
all_values[53]	1782	1			T11	2		T13	2		T15	8
all_values[54]	1645	1			T3	1		T7	1		T11	3
all_values[55]	1625	1			T3	1		T11	1		T13	2
all_values[56]	1663	1			T11	4		T13	5		T15	9
all_values[57]	1651	1			T11	5		T13	3		T15	10
all_values[58]	1593	1			T11	3		T13	5		T15	4
all_values[59]	1613	1			T7	1		T11	5		T13	3
all_values[60]	1641	1			T13	2		T15	9		T16	17
all_values[61]	1578	1			T11	7		T13	3		T15	6
all_values[62]	1641	1			T3	1		T7	2		T11	2
all_values[63]	1669	1			T3	1		T11	6		T13	3