Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	194955	1			T1	8		T2	7		T3	73
values[2]	6371	1			T3	14		T12	9		T13	11
values[3]	2194	1			T12	1		T16	1		T50	1
values[4]	1669	1			T168	50		T37	19		T27	33
values[5]	1413	1			T168	69		T37	6		T27	57
values[6]	1119	1			T168	71		T37	4		T27	41
values[7]	995	1			T168	27		T37	10		T27	55
values[8]	853	1			T168	22		T37	14		T27	49
values[9]	652	1			T168	13		T37	13		T27	17
values[10]	605	1			T168	8		T37	5		T27	4
values[11]	458	1			T168	17		T37	19		T27	5
values[12]	442	1			T168	15		T37	26		T27	4
values[13]	439	1			T168	10		T37	38		T27	7
values[14]	483	1			T168	4		T37	46		T27	1
values[15]	443	1			T37	64		T96	2		T225	73
values[16]	383	1			T37	50		T96	4		T225	72
values[17]	321	1			T37	24		T96	4		T225	60
values[18]	290	1			T37	14		T96	7		T225	45
values[19]	296	1			T37	8		T96	9		T225	44
values[20]	288	1			T37	17		T96	6		T225	31
values[21]	236	1			T37	12		T96	4		T225	15
values[22]	198	1			T37	2		T96	2		T225	17
values[23]	141	1			T96	2		T225	18		T170	1
values[24]	128	1			T96	1		T225	26		T170	1
values[25]	165	1			T96	8		T225	30		T170	1
values[26]	127	1			T96	4		T225	27		T170	1
values[27]	145	1			T96	3		T225	22		T170	1
values[28]	115	1			T96	2		T225	21		T170	1
values[29]	123	1			T96	4		T225	16		T170	1
values[30]	93	1			T96	3		T225	15		T170	1
values[31]	84	1			T96	2		T225	10		T170	1
values[32]	95	1			T96	1		T225	6		T170	1
values[33]	93	1			T96	1		T225	4		T170	1
values[34]	83	1			T96	1		T170	1		T232	1
values[35]	87	1			T96	1		T170	1		T232	1
values[36]	94	1			T96	3		T170	1		T232	1
values[37]	81	1			T96	1		T170	1		T232	1
values[38]	72	1			T96	1		T170	1		T232	1
values[39]	58	1			T96	3		T170	1		T232	2
values[40]	54	1			T96	1		T170	1		T232	1
values[41]	60	1			T96	1		T170	1		T232	1
values[42]	79	1			T96	3		T170	1		T232	1
values[43]	74	1			T96	1		T170	1		T232	1
values[44]	68	1			T96	3		T170	1		T232	1
values[45]	71	1			T96	5		T170	1		T232	1
values[46]	71	1			T96	3		T170	1		T232	1
values[47]	78	1			T96	1		T170	1		T232	1
values[48]	81	1			T96	1		T170	1		T232	1
values[49]	74	1			T96	1		T170	1		T232	1
values[50]	61	1			T96	3		T170	1		T232	1
values[51]	65	1			T96	2		T170	1		T232	2
values[52]	62	1			T96	2		T170	1		T232	1
values[53]	50	1			T96	2		T170	1		T232	1
values[54]	61	1			T96	2		T170	1		T232	1
values[55]	63	1			T96	2		T170	1		T232	1
values[56]	64	1			T96	8		T170	1		T232	1
values[57]	64	1			T96	1		T170	1		T232	1
values[58]	79	1			T96	4		T170	1		T232	1
values[59]	76	1			T96	6		T170	1		T232	1
values[60]	64	1			T96	8		T170	1		T232	1
values[61]	53	1			T96	4		T170	1		T232	1
values[62]	51	1			T96	2		T170	1		T232	1
values[63]	56	1			T96	3		T170	1		T232	1
values[64]	52	1			T96	2		T170	1		T232	1
values[65]	50	1			T96	3		T170	1		T232	1
values[66]	64	1			T96	4		T170	1		T232	1
values[67]	53	1			T96	1		T170	1		T232	1
values[68]	64	1			T96	1		T170	1		T232	1
values[69]	69	1			T96	3		T170	1		T232	1
values[70]	60	1			T96	6		T170	1		T232	1
values[71]	70	1			T96	6		T170	1		T232	1
values[72]	52	1			T96	5		T170	1		T232	1
values[73]	53	1			T96	2		T170	1		T232	1
values[74]	56	1			T96	1		T170	1		T232	1
values[75]	50	1			T96	1		T170	1		T232	1
values[76]	53	1			T96	2		T170	1		T232	1
values[77]	45	1			T96	2		T170	2		T232	1
values[78]	49	1			T96	1		T170	1		T232	1
values[79]	48	1			T96	2		T170	1		T232	1
values[80]	66	1			T96	3		T170	1		T232	1
values[81]	68	1			T96	4		T170	1		T232	1
values[82]	64	1			T96	2		T170	1		T232	1
values[83]	59	1			T96	3		T170	1		T232	1
values[84]	74	1			T96	7		T170	1		T232	1
values[85]	72	1			T96	4		T170	1		T232	1
values[86]	74	1			T96	10		T170	1		T232	1
values[87]	55	1			T96	3		T170	1		T232	1
values[88]	64	1			T96	3		T170	1		T232	1
values[89]	65	1			T96	1		T170	1		T232	1
values[90]	73	1			T96	2		T170	1		T232	1
values[91]	80	1			T96	3		T170	1		T232	1
values[92]	70	1			T96	3		T170	1		T232	1
values[93]	71	1			T96	10		T170	1		T232	1
values[94]	69	1			T96	5		T170	1		T232	1
values[95]	79	1			T96	3		T170	1		T232	1
values[96]	89	1			T96	4		T170	1		T232	1
values[97]	73	1			T96	5		T170	1		T232	1
values[98]	74	1			T96	4		T170	1		T232	1
values[99]	74	1			T96	1		T170	1		T232	1
values[100]	71	1			T96	6		T170	1		T232	1
values[101]	69	1			T96	5		T170	1		T232	3
values[102]	66	1			T96	2		T170	1		T232	3
values[103]	89	1			T96	4		T170	1		T232	2
values[104]	78	1			T96	2		T170	1		T232	2
values[105]	93	1			T96	3		T170	1		T232	8
values[106]	81	1			T96	9		T170	1		T232	5
values[107]	88	1			T96	7		T170	1		T232	4
values[108]	102	1			T96	1		T170	1		T232	1
values[109]	111	1			T96	8		T170	1		T232	2
values[110]	83	1			T96	2		T170	1		T232	3
values[111]	98	1			T96	3		T170	1		T232	3
values[112]	79	1			T96	5		T170	1		T232	2
values[113]	109	1			T96	10		T170	1		T232	2
values[114]	99	1			T96	9		T170	1		T232	4
values[115]	88	1			T96	4		T170	4		T232	1
values[116]	95	1			T96	5		T170	1		T232	1
values[117]	97	1			T96	5		T170	1		T232	2
values[118]	87	1			T96	7		T170	4		T232	2
values[119]	110	1			T96	6		T170	1		T232	3
values[120]	106	1			T96	3		T170	2		T232	2
values[121]	121	1			T96	13		T170	4		T232	2
values[122]	126	1			T96	19		T170	1		T232	1
values[123]	155	1			T96	20		T170	1		T232	5
values[124]	227	1			T96	15		T170	2		T232	1
values[125]	420	1			T96	4		T170	1		T232	2
values[126]	699	1			T96	16		T170	8		T232	14
values[127]	1977	1			T96	20		T170	108		T232	116
values[128]	3165	1			T96	2		T170	269		T232	220