Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	172411	1			T1	6		T2	3		T3	60
values[2]	10086	1			T3	1		T10	60		T11	2
values[3]	3858	1			T10	27		T14	3		T72	1
values[4]	2506	1			T10	14		T14	11		T233	1
values[5]	1830	1			T10	15		T14	3		T27	40
values[6]	1221	1			T10	25		T14	12		T27	6
values[7]	937	1			T10	7		T14	10		T83	37
values[8]	807	1			T10	2		T14	4		T83	32
values[9]	716	1			T14	4		T83	15		T43	42
values[10]	747	1			T14	12		T83	11		T43	50
values[11]	658	1			T14	4		T83	1		T43	26
values[12]	569	1			T14	8		T43	36		T96	4
values[13]	575	1			T14	2		T43	37		T96	5
values[14]	449	1			T14	12		T43	23		T96	2
values[15]	415	1			T14	7		T43	3		T96	3
values[16]	358	1			T14	3		T43	5		T96	17
values[17]	375	1			T14	7		T43	15		T96	7
values[18]	292	1			T14	4		T43	3		T96	2
values[19]	354	1			T14	7		T43	9		T96	3
values[20]	324	1			T14	9		T43	8		T96	3
values[21]	363	1			T14	7		T43	10		T96	1
values[22]	323	1			T14	9		T43	9		T96	6
values[23]	302	1			T14	8		T43	14		T96	6
values[24]	328	1			T14	3		T43	4		T96	6
values[25]	271	1			T14	11		T96	8		T236	10
values[26]	222	1			T14	4		T96	15		T236	7
values[27]	227	1			T14	10		T96	17		T236	33
values[28]	202	1			T14	9		T96	18		T236	3
values[29]	189	1			T14	11		T96	2		T110	10
values[30]	183	1			T14	9		T96	5		T110	5
values[31]	163	1			T14	8		T96	6		T110	8
values[32]	197	1			T14	11		T96	8		T110	28
values[33]	213	1			T14	4		T96	18		T110	7
values[34]	209	1			T14	14		T96	8		T110	12
values[35]	182	1			T14	3		T96	10		T110	13
values[36]	207	1			T14	5		T96	29		T110	16
values[37]	227	1			T14	8		T96	25		T110	8
values[38]	205	1			T14	9		T96	25		T110	6
values[39]	135	1			T14	5		T96	6		T110	14
values[40]	146	1			T14	4		T96	6		T110	2
values[41]	142	1			T14	3		T96	3		T110	5
values[42]	146	1			T14	4		T110	8		T111	17
values[43]	160	1			T14	4		T110	11		T111	26
values[44]	142	1			T14	5		T110	11		T111	15
values[45]	165	1			T14	12		T110	6		T111	10
values[46]	187	1			T14	4		T110	11		T111	25
values[47]	162	1			T14	8		T110	8		T111	15
values[48]	151	1			T14	5		T110	6		T111	15
values[49]	180	1			T14	10		T110	30		T111	26
values[50]	136	1			T14	5		T110	14		T111	15
values[51]	108	1			T14	3		T110	1		T111	11
values[52]	98	1			T14	7		T111	16		T97	1
values[53]	113	1			T14	6		T111	15		T97	1
values[54]	106	1			T14	4		T111	33		T97	1
values[55]	98	1			T14	11		T111	14		T97	1
values[56]	99	1			T14	4		T111	29		T97	1
values[57]	96	1			T14	12		T111	27		T97	1
values[58]	75	1			T14	7		T111	20		T97	1
values[59]	60	1			T14	4		T111	7		T97	1
values[60]	70	1			T14	12		T111	6		T97	1
values[61]	87	1			T14	8		T111	11		T97	1
values[62]	76	1			T14	6		T111	17		T97	1
values[63]	78	1			T14	2		T111	6		T97	1
values[64]	86	1			T14	8		T97	1		T102	1
values[65]	91	1			T14	10		T97	1		T102	1
values[66]	103	1			T14	5		T97	1		T102	1
values[67]	83	1			T14	7		T97	1		T102	1
values[68]	81	1			T14	10		T97	1		T102	2
values[69]	52	1			T14	7		T97	1		T102	1
values[70]	51	1			T14	5		T97	1		T102	1
values[71]	55	1			T14	6		T97	1		T102	1
values[72]	62	1			T14	4		T97	1		T102	1
values[73]	60	1			T14	4		T97	1		T102	1
values[74]	73	1			T14	11		T97	1		T102	1
values[75]	55	1			T14	5		T97	1		T102	1
values[76]	56	1			T97	1		T102	1		T232	1
values[77]	52	1			T97	1		T102	1		T232	1
values[78]	59	1			T97	1		T102	1		T232	1
values[79]	59	1			T97	1		T102	1		T232	2
values[80]	53	1			T97	1		T102	1		T232	1
values[81]	43	1			T97	1		T102	1		T232	1
values[82]	53	1			T97	1		T102	1		T232	1
values[83]	66	1			T97	1		T102	1		T232	1
values[84]	55	1			T97	2		T102	1		T232	1
values[85]	76	1			T97	1		T102	1		T232	1
values[86]	77	1			T97	1		T102	1		T232	1
values[87]	58	1			T97	1		T102	1		T232	1
values[88]	52	1			T97	1		T102	1		T232	1
values[89]	51	1			T97	1		T102	1		T232	1
values[90]	57	1			T97	1		T102	1		T232	1
values[91]	55	1			T97	1		T102	1		T232	1
values[92]	75	1			T97	1		T102	1		T232	1
values[93]	62	1			T97	1		T102	1		T232	1
values[94]	54	1			T97	1		T102	1		T232	1
values[95]	51	1			T97	1		T102	1		T232	1
values[96]	54	1			T97	1		T102	1		T232	1
values[97]	53	1			T97	1		T102	1		T232	1
values[98]	52	1			T97	1		T102	1		T232	1
values[99]	48	1			T97	1		T102	1		T232	1
values[100]	53	1			T97	1		T102	2		T232	1
values[101]	51	1			T97	1		T102	1		T232	1
values[102]	46	1			T97	1		T102	1		T232	1
values[103]	42	1			T97	1		T102	1		T232	1
values[104]	41	1			T97	1		T102	1		T232	1
values[105]	57	1			T97	1		T102	1		T232	1
values[106]	53	1			T97	1		T102	1		T232	1
values[107]	39	1			T97	1		T102	1		T232	1
values[108]	37	1			T97	1		T102	1		T232	1
values[109]	34	1			T97	2		T102	1		T232	1
values[110]	48	1			T97	1		T102	1		T232	1
values[111]	58	1			T97	3		T102	1		T232	1
values[112]	53	1			T97	3		T102	1		T232	1
values[113]	42	1			T97	1		T102	1		T232	1
values[114]	41	1			T97	2		T102	1		T232	1
values[115]	50	1			T97	3		T102	2		T232	1
values[116]	58	1			T97	2		T102	2		T232	1
values[117]	44	1			T97	2		T102	4		T232	1
values[118]	37	1			T97	1		T102	1		T232	1
values[119]	59	1			T97	1		T102	1		T232	1
values[120]	62	1			T97	4		T102	2		T232	5
values[121]	49	1			T97	3		T102	2		T232	1
values[122]	44	1			T97	2		T102	1		T232	1
values[123]	54	1			T97	4		T102	1		T232	1
values[124]	40	1			T97	2		T102	2		T232	1
values[125]	38	1			T97	1		T102	1		T232	1
values[126]	396	1			T97	38		T102	29		T232	3
values[127]	2408	1			T97	146		T102	144		T232	29
values[128]	4867	1			T97	154		T102	181		T232	250