Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	192	0	192	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	751366	1			T1	22		T2	17		T3	170
values[2]	49489	1			T1	1		T3	55		T7	7
values[3]	7188	1			T3	19		T9	31		T11	3
values[4]	1986	1			T3	3		T9	6		T11	1
values[5]	867	1			T3	1		T9	2		T11	1
values[6]	584	1			T9	1		T51	3		T168	14
values[7]	456	1			T168	10		T23	14		T233	2
values[8]	400	1			T168	6		T23	18		T27	3
values[9]	394	1			T168	11		T23	23		T27	5
values[10]	383	1			T168	8		T23	36		T27	3
values[11]	314	1			T168	9		T23	39		T27	1
values[12]	228	1			T168	8		T23	18		T27	2
values[13]	283	1			T168	8		T23	22		T27	2
values[14]	233	1			T168	4		T23	10		T27	5
values[15]	206	1			T168	11		T23	2		T27	5
values[16]	250	1			T168	12		T27	6		T88	17
values[17]	305	1			T168	21		T27	2		T88	12
values[18]	276	1			T168	18		T27	1		T88	11
values[19]	238	1			T168	16		T27	4		T88	4
values[20]	259	1			T168	17		T27	1		T88	8
values[21]	250	1			T168	13		T27	2		T88	9
values[22]	274	1			T168	4		T27	1		T88	6
values[23]	245	1			T168	8		T27	1		T88	6
values[24]	202	1			T168	9		T27	1		T88	9
values[25]	199	1			T168	9		T27	2		T88	16
values[26]	182	1			T168	5		T27	3		T88	10
values[27]	180	1			T168	5		T27	1		T88	9
values[28]	222	1			T168	8		T27	1		T88	3
values[29]	189	1			T168	9		T27	1		T88	3
values[30]	141	1			T168	8		T27	1		T88	5
values[31]	167	1			T168	8		T27	1		T88	11
values[32]	172	1			T168	10		T27	2		T88	3
values[33]	159	1			T168	9		T27	3		T88	2
values[34]	185	1			T168	7		T27	3		T88	1
values[35]	203	1			T168	5		T27	1		T88	3
values[36]	190	1			T168	5		T27	1		T88	2
values[37]	165	1			T168	6		T27	1		T88	3
values[38]	147	1			T168	6		T27	2		T88	2
values[39]	182	1			T168	5		T27	2		T88	7
values[40]	172	1			T168	5		T27	1		T88	4
values[41]	150	1			T168	11		T27	2		T88	9
values[42]	146	1			T168	12		T27	2		T88	10
values[43]	176	1			T168	8		T27	3		T88	9
values[44]	158	1			T168	5		T27	1		T88	10
values[45]	179	1			T168	12		T27	2		T88	15
values[46]	156	1			T168	8		T27	1		T88	13
values[47]	146	1			T168	6		T27	2		T88	6
values[48]	132	1			T168	14		T27	1		T88	3
values[49]	125	1			T168	9		T27	1		T88	10
values[50]	134	1			T168	9		T27	2		T88	9
values[51]	156	1			T168	4		T27	1		T88	18
values[52]	173	1			T168	2		T27	2		T88	8
values[53]	153	1			T168	6		T27	1		T88	5
values[54]	134	1			T168	6		T27	2		T88	2
values[55]	143	1			T168	4		T27	1		T88	2
values[56]	115	1			T168	2		T27	1		T88	2
values[57]	140	1			T168	1		T27	1		T88	14
values[58]	149	1			T168	1		T27	1		T88	20
values[59]	140	1			T168	4		T27	4		T88	6
values[60]	126	1			T168	1		T27	1		T88	3
values[61]	144	1			T168	3		T27	2		T88	3
values[62]	146	1			T168	1		T27	1		T88	3
values[63]	144	1			T168	1		T27	1		T88	2
values[64]	115	1			T168	1		T27	1		T88	7
values[65]	132	1			T168	3		T27	1		T88	1
values[66]	134	1			T168	1		T27	3		T88	1
values[67]	166	1			T168	1		T27	3		T88	2
values[68]	177	1			T168	1		T27	1		T88	6
values[69]	179	1			T168	1		T27	1		T88	31
values[70]	145	1			T168	2		T27	1		T88	19
values[71]	144	1			T168	2		T27	1		T88	17
values[72]	141	1			T168	1		T27	1		T88	11
values[73]	113	1			T168	3		T27	1		T88	2
values[74]	102	1			T168	2		T27	2		T88	4
values[75]	112	1			T168	1		T27	1		T88	5
values[76]	117	1			T168	2		T27	1		T88	2
values[77]	121	1			T168	1		T27	3		T88	1
values[78]	121	1			T168	1		T27	1		T88	1
values[79]	133	1			T168	2		T27	3		T88	4
values[80]	145	1			T168	2		T27	3		T88	7
values[81]	155	1			T168	2		T27	2		T88	1
values[82]	139	1			T168	2		T27	1		T88	5
values[83]	147	1			T168	2		T27	1		T88	13
values[84]	156	1			T168	4		T27	1		T88	14
values[85]	149	1			T168	5		T27	5		T88	7
values[86]	150	1			T168	2		T27	3		T88	8
values[87]	146	1			T168	3		T27	1		T88	6
values[88]	145	1			T168	1		T27	1		T88	12
values[89]	144	1			T168	1		T27	1		T88	11
values[90]	181	1			T168	1		T27	1		T88	10
values[91]	160	1			T168	2		T27	2		T88	9
values[92]	155	1			T168	1		T27	2		T88	13
values[93]	176	1			T168	3		T27	3		T88	28
values[94]	166	1			T168	1		T27	1		T88	18
values[95]	156	1			T168	2		T27	1		T88	10
values[96]	150	1			T168	1		T27	1		T88	4
values[97]	135	1			T168	1		T27	3		T88	7
values[98]	111	1			T168	1		T27	3		T88	4
values[99]	115	1			T168	2		T27	2		T34	4
values[100]	125	1			T168	3		T27	2		T34	6
values[101]	148	1			T168	2		T27	2		T34	5
values[102]	131	1			T168	1		T27	3		T34	5
values[103]	128	1			T168	1		T27	1		T34	3
values[104]	154	1			T168	2		T27	1		T34	5
values[105]	164	1			T168	1		T27	2		T34	6
values[106]	188	1			T168	2		T27	3		T34	3
values[107]	150	1			T168	1		T27	1		T34	4
values[108]	181	1			T168	3		T27	3		T34	4
values[109]	127	1			T168	2		T27	3		T34	3
values[110]	133	1			T168	2		T27	2		T34	2
values[111]	135	1			T168	2		T27	3		T34	3
values[112]	149	1			T168	1		T27	2		T34	3
values[113]	125	1			T168	2		T27	1		T34	2
values[114]	107	1			T168	1		T27	1		T34	4
values[115]	136	1			T168	1		T27	3		T34	6
values[116]	140	1			T168	1		T27	3		T34	5
values[117]	136	1			T168	1		T27	2		T34	3
values[118]	126	1			T168	1		T27	1		T34	1
values[119]	127	1			T168	3		T27	2		T34	1
values[120]	139	1			T168	1		T27	2		T34	4
values[121]	147	1			T168	1		T27	1		T34	7
values[122]	100	1			T168	2		T27	2		T34	6
values[123]	115	1			T168	5		T27	4		T34	7
values[124]	103	1			T168	2		T27	5		T34	2
values[125]	110	1			T168	1		T27	1		T34	2
values[126]	210	1			T168	1		T27	1		T34	9
values[127]	386	1			T168	2		T27	3		T34	16
values[128]	451	1			T168	1		T27	1		T34	44
values[129]	238	1			T168	3		T27	3		T34	21
values[130]	76	1			T168	5		T27	1		T228	4
values[131]	77	1			T168	1		T27	2		T90	1
values[132]	82	1			T168	2		T27	2		T90	1
values[133]	80	1			T168	1		T27	1		T90	1
values[134]	73	1			T168	2		T27	1		T90	1
values[135]	101	1			T168	1		T27	1		T90	1
values[136]	92	1			T168	1		T27	1		T90	1
values[137]	100	1			T168	3		T27	3		T90	1
values[138]	97	1			T168	1		T27	3		T90	1
values[139]	92	1			T168	3		T27	5		T90	1
values[140]	65	1			T168	3		T27	4		T90	1
values[141]	62	1			T168	1		T27	1		T90	1
values[142]	91	1			T168	1		T27	2		T90	1
values[143]	72	1			T168	1		T27	1		T90	1
values[144]	73	1			T168	1		T27	3		T90	1
values[145]	80	1			T168	2		T27	2		T90	1
values[146]	93	1			T168	4		T27	2		T90	1
values[147]	86	1			T168	1		T27	4		T90	1
values[148]	71	1			T168	1		T27	2		T90	1
values[149]	84	1			T168	3		T27	2		T90	1
values[150]	103	1			T168	2		T27	3		T90	1
values[151]	95	1			T168	3		T27	2		T90	1
values[152]	93	1			T168	3		T27	3		T90	1
values[153]	102	1			T168	7		T27	2		T90	1
values[154]	116	1			T168	2		T27	2		T90	1
values[155]	117	1			T168	4		T27	3		T90	1
values[156]	102	1			T168	3		T27	4		T90	1
values[157]	93	1			T168	4		T27	5		T90	1
values[158]	102	1			T168	2		T27	4		T90	1
values[159]	102	1			T168	6		T27	1		T90	1
values[160]	82	1			T168	3		T27	1		T90	1
values[161]	106	1			T168	4		T27	5		T90	1
values[162]	77	1			T168	2		T27	3		T90	1
values[163]	96	1			T168	1		T27	1		T90	1
values[164]	83	1			T168	4		T27	2		T90	1
values[165]	109	1			T168	8		T27	5		T90	1
values[166]	99	1			T168	3		T27	8		T90	1
values[167]	92	1			T168	3		T27	3		T90	1
values[168]	90	1			T168	6		T27	6		T90	1
values[169]	92	1			T168	5		T27	5		T90	1
values[170]	87	1			T168	5		T27	3		T90	1
values[171]	86	1			T168	3		T27	5		T90	1
values[172]	74	1			T168	6		T27	2		T90	1
values[173]	104	1			T168	5		T27	4		T90	1
values[174]	93	1			T168	3		T27	7		T90	1
values[175]	75	1			T168	1		T27	5		T90	1
values[176]	95	1			T168	1		T27	5		T90	1
values[177]	85	1			T168	5		T27	1		T90	1
values[178]	70	1			T168	6		T27	3		T90	4
values[179]	70	1			T168	3		T27	10		T90	1
values[180]	93	1			T168	3		T27	7		T90	2
values[181]	75	1			T168	2		T27	6		T90	2
values[182]	87	1			T168	2		T27	6		T90	1
values[183]	80	1			T168	3		T27	2		T90	3
values[184]	107	1			T168	5		T27	1		T90	1
values[185]	113	1			T168	3		T27	5		T90	9
values[186]	87	1			T168	2		T27	9		T90	1
values[187]	83	1			T168	3		T27	5		T90	2
values[188]	112	1			T168	5		T27	7		T90	7
values[189]	266	1			T168	44		T27	18		T90	6
values[190]	675	1			T168	77		T27	67		T90	2
values[191]	1685	1			T168	111		T27	117		T90	35
values[192]	7367	1			T168	45		T27	63		T90	435