Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 452 1 T8 6 T9 1 T10 1
all_values[1] 501 1 T8 3 T9 1 T13 1
all_values[2] 446 1 T8 5 T10 1 T13 1
all_values[3] 456 1 T8 5 T16 4 T20 2
all_values[4] 481 1 T8 1 T10 1 T16 2
all_values[5] 517 1 T8 8 T13 3 T14 1
all_values[6] 458 1 T8 3 T10 1 T20 3
all_values[7] 495 1 T8 5 T10 1 T14 1
all_values[8] 490 1 T8 3 T10 1 T14 1
all_values[9] 460 1 T8 3 T9 1 T16 1
all_values[10] 463 1 T8 3 T16 1 T20 3
all_values[11] 468 1 T8 4 T13 1 T16 1
all_values[12] 467 1 T8 8 T9 1 T10 1
all_values[13] 486 1 T8 4 T13 1 T20 6
all_values[14] 512 1 T8 2 T13 1 T16 2
all_values[15] 412 1 T8 1 T10 1 T16 1
all_values[16] 469 1 T8 3 T9 1 T16 2
all_values[17] 479 1 T8 5 T9 3 T13 1
all_values[18] 477 1 T8 5 T10 1 T16 3
all_values[19] 467 1 T8 1 T9 1 T10 3
all_values[20] 467 1 T8 2 T14 2 T16 1
all_values[21] 524 1 T8 7 T10 1 T13 1
all_values[22] 442 1 T8 1 T14 1 T16 2
all_values[23] 461 1 T8 3 T10 2 T16 5

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