Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1666	1			T8	11		T13	5		T16	15
all_values[1]	1664	1			T8	5		T13	6		T16	20
all_values[2]	1698	1			T8	6		T10	2		T13	1
all_values[3]	1663	1			T8	10		T13	4		T16	10
all_values[4]	1643	1			T8	9		T10	1		T13	3
all_values[5]	1622	1			T8	8		T13	1		T16	18
all_values[6]	1720	1			T8	5		T13	3		T16	18
all_values[7]	1679	1			T8	5		T13	3		T16	15
all_values[8]	1592	1			T8	4		T13	3		T16	11
all_values[9]	1649	1			T8	9		T13	2		T16	23
all_values[10]	1631	1			T8	10		T10	1		T13	3
all_values[11]	1640	1			T8	5		T13	2		T16	22
all_values[12]	1723	1			T8	10		T10	2		T13	1
all_values[13]	1669	1			T8	8		T13	5		T16	14
all_values[14]	1622	1			T8	9		T13	6		T16	16
all_values[15]	1664	1			T8	4		T13	2		T16	16
all_values[16]	1628	1			T8	4		T13	2		T16	8
all_values[17]	1641	1			T8	12		T13	2		T16	16
all_values[18]	1690	1			T8	11		T13	2		T16	15
all_values[19]	1601	1			T8	5		T10	1		T13	5
all_values[20]	1624	1			T8	6		T13	2		T16	15
all_values[21]	1702	1			T8	12		T13	2		T16	20
all_values[22]	1670	1			T8	8		T10	2		T13	5
all_values[23]	1753	1			T8	6		T13	1		T16	17
all_values[24]	1716	1			T8	14		T13	3		T16	19
all_values[25]	1734	1			T8	12		T10	1		T13	5
all_values[26]	1686	1			T8	10		T10	1		T13	4
all_values[27]	1724	1			T8	7		T13	2		T16	15
all_values[28]	1640	1			T8	4		T10	1		T13	4
all_values[29]	1706	1			T8	10		T13	1		T16	22
all_values[30]	1737	1			T8	6		T13	4		T16	10
all_values[31]	1643	1			T8	8		T13	1		T16	16
all_values[32]	1647	1			T8	7		T10	1		T13	3
all_values[33]	1629	1			T8	8		T13	4		T16	20
all_values[34]	1664	1			T8	8		T13	6		T16	23
all_values[35]	1596	1			T8	4		T13	2		T16	14
all_values[36]	1686	1			T8	10		T10	1		T13	3
all_values[37]	1593	1			T8	7		T13	3		T16	14
all_values[38]	1765	1			T8	9		T13	1		T16	21
all_values[39]	1691	1			T8	5		T13	5		T16	11
all_values[40]	1654	1			T8	4		T10	1		T13	3
all_values[41]	1693	1			T8	5		T13	5		T16	10
all_values[42]	1610	1			T8	8		T10	1		T13	1
all_values[43]	1665	1			T8	5		T10	1		T13	1
all_values[44]	1676	1			T8	6		T10	1		T13	3
all_values[45]	1668	1			T8	6		T13	5		T16	14
all_values[46]	1672	1			T8	9		T10	1		T13	1
all_values[47]	1652	1			T8	8		T13	5		T16	13
all_values[48]	1715	1			T8	14		T13	2		T16	17
all_values[49]	1719	1			T8	7		T13	5		T16	14
all_values[50]	1651	1			T8	12		T10	1		T13	6
all_values[51]	1578	1			T8	2		T13	5		T16	17
all_values[52]	1702	1			T8	7		T13	2		T16	20
all_values[53]	1635	1			T8	10		T13	2		T16	16
all_values[54]	1736	1			T8	9		T10	1		T13	2
all_values[55]	1673	1			T8	9		T13	6		T16	22
all_values[56]	1610	1			T8	12		T13	2		T16	13
all_values[57]	1731	1			T8	8		T10	1		T13	4
all_values[58]	1725	1			T8	9		T13	4		T16	17
all_values[59]	1595	1			T8	17		T10	1		T13	2
all_values[60]	1682	1			T8	7		T13	2		T16	14
all_values[61]	1612	1			T8	5		T13	2		T16	18
all_values[62]	1602	1			T8	11		T13	3		T16	17
all_values[63]	1620	1			T8	8		T13	3		T16	18