Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1798	1			T3	15		T9	11		T11	7
all_values[1]	1817	1			T3	9		T9	7		T11	7
all_values[2]	1757	1			T3	8		T9	9		T11	5
all_values[3]	1855	1			T3	6		T9	6		T11	7
all_values[4]	1900	1			T3	5		T9	8		T11	8
all_values[5]	1844	1			T3	10		T9	5		T11	13
all_values[6]	1776	1			T3	7		T9	6		T11	11
all_values[7]	1820	1			T3	12		T9	7		T11	14
all_values[8]	1839	1			T3	14		T9	9		T11	12
all_values[9]	1773	1			T3	14		T9	5		T11	3
all_values[10]	1772	1			T3	9		T9	6		T11	6
all_values[11]	1728	1			T3	7		T9	7		T11	8
all_values[12]	1742	1			T3	12		T9	14		T11	8
all_values[13]	1883	1			T3	17		T9	7		T11	18
all_values[14]	1719	1			T3	5		T9	11		T11	17
all_values[15]	1734	1			T3	5		T9	7		T11	8
all_values[16]	1826	1			T3	5		T9	8		T11	13
all_values[17]	1764	1			T3	7		T9	13		T11	5
all_values[18]	1852	1			T3	7		T9	10		T11	10
all_values[19]	1844	1			T3	8		T9	6		T11	5
all_values[20]	1765	1			T3	4		T9	6		T11	8
all_values[21]	1825	1			T3	5		T9	7		T11	10
all_values[22]	1813	1			T3	6		T9	12		T11	6
all_values[23]	1813	1			T3	5		T9	4		T11	5
all_values[24]	1826	1			T3	6		T9	9		T11	3
all_values[25]	1827	1			T3	4		T9	11		T11	9
all_values[26]	1837	1			T3	11		T9	8		T11	7
all_values[27]	1779	1			T3	3		T9	4		T11	7
all_values[28]	1874	1			T3	12		T9	12		T11	3
all_values[29]	1886	1			T3	13		T9	11		T11	3
all_values[30]	1809	1			T3	13		T9	12		T11	9
all_values[31]	1867	1			T3	9		T9	10		T11	5
all_values[32]	1872	1			T3	4		T9	12		T11	9
all_values[33]	1765	1			T3	8		T9	8		T11	8
all_values[34]	1785	1			T3	5		T9	5		T11	6
all_values[35]	1749	1			T3	10		T9	4		T11	7
all_values[36]	1760	1			T3	7		T9	6		T11	6
all_values[37]	1810	1			T3	4		T9	12		T11	11
all_values[38]	1797	1			T3	7		T9	5		T11	7
all_values[39]	1762	1			T3	5		T9	6		T11	6
all_values[40]	1817	1			T3	10		T9	8		T11	9
all_values[41]	1867	1			T3	9		T9	11		T11	6
all_values[42]	1852	1			T3	10		T9	8		T11	8
all_values[43]	1841	1			T3	7		T9	11		T11	3
all_values[44]	1781	1			T3	10		T9	4		T11	8
all_values[45]	1753	1			T3	7		T9	5		T11	8
all_values[46]	1723	1			T3	7		T9	12		T11	6
all_values[47]	1800	1			T3	13		T9	6		T11	6
all_values[48]	1854	1			T3	15		T9	3		T11	5
all_values[49]	1764	1			T3	7		T9	8		T11	5
all_values[50]	1851	1			T3	8		T9	10		T11	10
all_values[51]	1776	1			T3	13		T9	9		T11	6
all_values[52]	1803	1			T3	10		T9	8		T11	5
all_values[53]	1721	1			T3	12		T9	9		T11	5
all_values[54]	1900	1			T3	8		T9	9		T11	8
all_values[55]	1713	1			T3	9		T9	4		T11	5
all_values[56]	1848	1			T3	14		T9	8		T11	7
all_values[57]	1767	1			T3	11		T9	7		T11	8
all_values[58]	1871	1			T3	10		T9	6		T11	11
all_values[59]	1783	1			T3	5		T9	7		T11	8
all_values[60]	1790	1			T3	8		T9	8		T11	7
all_values[61]	1764	1			T3	12		T9	6		T11	6
all_values[62]	1793	1			T3	9		T9	8		T11	10
all_values[63]	1807	1			T3	6		T9	3		T11	6