Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 472 1 T1 1 T7 1 T9 1
all_values[1] 494 1 T1 1 T9 3 T34 2
all_values[2] 531 1 T7 1 T9 4 T17 4
all_values[3] 514 1 T1 1 T9 4 T17 1
all_values[4] 491 1 T1 1 T9 6 T34 2
all_values[5] 482 1 T1 1 T7 1 T9 3
all_values[6] 480 1 T1 1 T7 1 T9 3
all_values[7] 509 1 T7 1 T9 2 T34 1
all_values[8] 498 1 T7 1 T9 1 T34 1
all_values[9] 492 1 T1 1 T9 5 T34 3
all_values[10] 471 1 T1 1 T9 2 T34 2
all_values[11] 496 1 T9 5 T34 2 T46 2
all_values[12] 476 1 T1 2 T9 5 T34 1
all_values[13] 534 1 T1 2 T34 1 T46 1
all_values[14] 477 1 T9 1 T34 1 T46 1
all_values[15] 456 1 T9 5 T34 1 T17 7
all_values[16] 493 1 T1 1 T9 2 T34 2
all_values[17] 507 1 T1 1 T9 3 T34 3
all_values[18] 484 1 T1 1 T9 3 T34 3
all_values[19] 482 1 T9 5 T34 3 T46 1
all_values[20] 568 1 T1 1 T7 1 T9 3
all_values[21] 506 1 T1 2 T9 3 T34 3
all_values[22] 460 1 T1 2 T9 2 T34 3
all_values[23] 448 1 T1 2 T9 7 T17 2

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