Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1804	1			T1	5		T9	12		T10	1
all_values[1]	1686	1			T1	2		T9	10		T10	1
all_values[2]	1788	1			T1	4		T9	8		T10	1
all_values[3]	1727	1			T1	3		T9	8		T10	1
all_values[4]	1723	1			T1	3		T9	11		T10	1
all_values[5]	1756	1			T1	2		T9	14		T34	1
all_values[6]	1777	1			T1	2		T9	10		T10	3
all_values[7]	1847	1			T1	2		T9	11		T10	2
all_values[8]	1763	1			T9	12		T34	3		T17	25
all_values[9]	1762	1			T1	1		T9	10		T34	1
all_values[10]	1801	1			T1	2		T9	9		T10	2
all_values[11]	1675	1			T1	3		T9	5		T10	3
all_values[12]	1761	1			T1	4		T9	9		T34	4
all_values[13]	1792	1			T1	5		T9	11		T10	2
all_values[14]	1745	1			T9	12		T10	3		T17	23
all_values[15]	1793	1			T1	1		T9	9		T10	2
all_values[16]	1801	1			T1	2		T9	9		T34	1
all_values[17]	1781	1			T9	8		T10	4		T34	2
all_values[18]	1772	1			T1	5		T9	7		T10	2
all_values[19]	1766	1			T1	1		T9	5		T34	2
all_values[20]	1840	1			T1	6		T9	7		T10	1
all_values[21]	1759	1			T1	2		T9	8		T10	5
all_values[22]	1815	1			T1	1		T9	11		T10	1
all_values[23]	1776	1			T1	4		T9	6		T10	2
all_values[24]	1821	1			T1	3		T9	7		T10	5
all_values[25]	1788	1			T1	3		T9	11		T10	1
all_values[26]	1837	1			T1	2		T9	14		T10	3
all_values[27]	1851	1			T1	1		T9	7		T10	3
all_values[28]	1846	1			T1	1		T9	12		T17	28
all_values[29]	1767	1			T1	4		T9	13		T10	3
all_values[30]	1802	1			T1	1		T9	11		T10	1
all_values[31]	1706	1			T1	2		T9	10		T10	1
all_values[32]	1820	1			T1	3		T9	9		T10	1
all_values[33]	1837	1			T1	1		T9	10		T34	3
all_values[34]	1791	1			T1	2		T9	12		T10	2
all_values[35]	1860	1			T9	15		T34	1		T16	1
all_values[36]	1743	1			T1	3		T9	9		T34	1
all_values[37]	1748	1			T9	11		T10	2		T34	4
all_values[38]	1758	1			T1	1		T9	9		T10	5
all_values[39]	1831	1			T1	2		T9	13		T10	3
all_values[40]	1806	1			T1	2		T9	8		T10	2
all_values[41]	1838	1			T1	3		T9	10		T10	1
all_values[42]	1735	1			T1	1		T9	7		T10	1
all_values[43]	1798	1			T1	5		T9	13		T10	2
all_values[44]	1799	1			T1	1		T9	8		T10	1
all_values[45]	1859	1			T1	5		T9	13		T10	3
all_values[46]	1802	1			T1	4		T9	6		T10	2
all_values[47]	1808	1			T1	3		T9	10		T10	4
all_values[48]	1766	1			T1	4		T9	7		T34	2
all_values[49]	1798	1			T1	6		T9	10		T34	3
all_values[50]	1818	1			T1	3		T9	10		T10	2
all_values[51]	1789	1			T1	5		T9	10		T10	4
all_values[52]	1797	1			T1	4		T9	11		T10	2
all_values[53]	1833	1			T1	1		T9	15		T10	2
all_values[54]	1709	1			T1	1		T9	11		T10	2
all_values[55]	1743	1			T1	2		T9	7		T10	1
all_values[56]	1796	1			T9	14		T10	1		T34	1
all_values[57]	1854	1			T1	2		T9	11		T10	1
all_values[58]	1762	1			T1	4		T9	13		T10	2
all_values[59]	1734	1			T1	4		T9	13		T10	2
all_values[60]	1806	1			T1	1		T9	14		T10	3
all_values[61]	1798	1			T1	4		T9	6		T10	1
all_values[62]	1739	1			T1	4		T9	10		T34	3
all_values[63]	1785	1			T1	4		T9	4		T10	4