Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1804	1			T7	3		T9	1		T10	24
all_values[1]	1790	1			T7	5		T10	20		T11	1
all_values[2]	1766	1			T7	2		T10	26		T11	2
all_values[3]	1880	1			T7	4		T10	25		T11	2
all_values[4]	1849	1			T7	1		T10	24		T11	3
all_values[5]	1791	1			T7	1		T10	15		T11	5
all_values[6]	1792	1			T7	2		T10	21		T11	3
all_values[7]	1803	1			T7	2		T10	14		T11	4
all_values[8]	1914	1			T7	3		T10	23		T11	2
all_values[9]	1888	1			T7	2		T10	17		T11	2
all_values[10]	1845	1			T7	2		T10	15		T11	2
all_values[11]	1897	1			T10	23		T11	3		T169	2
all_values[12]	1852	1			T7	4		T10	25		T169	3
all_values[13]	1817	1			T7	5		T10	19		T11	1
all_values[14]	1779	1			T7	1		T10	19		T11	2
all_values[15]	1863	1			T7	2		T10	21		T11	3
all_values[16]	1847	1			T9	1		T10	18		T11	6
all_values[17]	1759	1			T10	18		T11	1		T169	2
all_values[18]	1843	1			T7	1		T10	20		T11	5
all_values[19]	1810	1			T7	2		T9	1		T10	20
all_values[20]	1822	1			T7	5		T10	23		T11	4
all_values[21]	1882	1			T7	3		T9	1		T10	26
all_values[22]	1816	1			T7	3		T9	2		T10	23
all_values[23]	1849	1			T7	2		T10	27		T11	2
all_values[24]	1844	1			T7	1		T9	1		T10	15
all_values[25]	1788	1			T7	1		T10	20		T11	2
all_values[26]	1856	1			T7	2		T9	2		T10	24
all_values[27]	1845	1			T7	1		T9	1		T10	15
all_values[28]	1874	1			T7	4		T10	20		T11	5
all_values[29]	1719	1			T7	3		T10	22		T11	3
all_values[30]	1840	1			T10	23		T11	2		T169	4
all_values[31]	1840	1			T7	2		T9	2		T10	22
all_values[32]	1770	1			T7	3		T10	23		T11	4
all_values[33]	1853	1			T9	3		T10	15		T11	6
all_values[34]	1856	1			T7	2		T10	21		T11	5
all_values[35]	1791	1			T10	16		T11	1		T169	1
all_values[36]	1817	1			T7	2		T10	26		T11	3
all_values[37]	1861	1			T7	4		T10	24		T11	3
all_values[38]	1822	1			T10	25		T11	2		T169	1
all_values[39]	1834	1			T7	2		T10	13		T11	4
all_values[40]	1818	1			T7	2		T9	2		T10	26
all_values[41]	1810	1			T7	4		T9	1		T10	20
all_values[42]	1929	1			T7	1		T10	21		T11	3
all_values[43]	1806	1			T7	1		T9	1		T10	27
all_values[44]	1842	1			T7	1		T10	21		T39	2
all_values[45]	1836	1			T7	4		T9	1		T10	14
all_values[46]	1799	1			T7	3		T10	17		T11	2
all_values[47]	1760	1			T7	3		T9	1		T10	16
all_values[48]	1852	1			T10	19		T11	1		T19	1
all_values[49]	1802	1			T7	3		T10	22		T11	1
all_values[50]	1826	1			T7	1		T9	1		T10	21
all_values[51]	1920	1			T7	1		T9	1		T10	23
all_values[52]	1817	1			T7	2		T9	1		T10	18
all_values[53]	1806	1			T7	1		T10	21		T68	1
all_values[54]	1814	1			T7	3		T10	21		T11	2
all_values[55]	1778	1			T7	1		T10	20		T11	3
all_values[56]	1763	1			T7	1		T9	1		T10	23
all_values[57]	1773	1			T7	4		T10	16		T169	3
all_values[58]	1901	1			T7	3		T10	26		T11	3
all_values[59]	1880	1			T9	1		T10	18		T11	2
all_values[60]	1791	1			T10	27		T11	2		T169	4
all_values[61]	1809	1			T7	2		T10	19		T11	1
all_values[62]	1798	1			T7	3		T10	29		T11	2
all_values[63]	1827	1			T7	2		T10	21		T169	3