Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	177708	1			T1	98		T2	7		T3	398
values[2]	7578	1			T3	3		T7	1		T8	8
values[3]	2847	1			T19	86		T68	1		T76	2
values[4]	1901	1			T19	47		T162	3		T125	96
values[5]	1454	1			T19	34		T125	51		T128	24
values[6]	1207	1			T19	32		T125	47		T128	22
values[7]	992	1			T19	28		T125	28		T128	7
values[8]	936	1			T19	24		T125	31		T86	1
values[9]	751	1			T19	34		T125	15		T86	1
values[10]	646	1			T19	17		T125	29		T86	1
values[11]	551	1			T19	10		T125	38		T86	1
values[12]	528	1			T19	5		T125	28		T86	1
values[13]	530	1			T19	4		T125	49		T86	1
values[14]	392	1			T19	3		T125	24		T86	1
values[15]	348	1			T19	3		T125	15		T86	1
values[16]	358	1			T19	1		T125	7		T86	1
values[17]	344	1			T19	2		T125	16		T86	1
values[18]	305	1			T19	1		T125	11		T86	1
values[19]	222	1			T19	2		T125	6		T86	1
values[20]	208	1			T19	2		T86	1		T87	6
values[21]	171	1			T19	4		T86	1		T87	15
values[22]	165	1			T19	4		T86	1		T87	15
values[23]	170	1			T19	6		T86	1		T87	6
values[24]	199	1			T19	1		T86	1		T87	3
values[25]	161	1			T19	5		T86	1		T87	4
values[26]	128	1			T19	1		T86	1		T87	23
values[27]	104	1			T86	1		T87	11		T241	1
values[28]	104	1			T86	1		T87	1		T241	1
values[29]	89	1			T86	1		T241	1		T243	1
values[30]	95	1			T86	1		T241	1		T243	1
values[31]	70	1			T86	1		T241	1		T243	1
values[32]	91	1			T86	1		T241	1		T243	1
values[33]	86	1			T86	1		T241	1		T243	1
values[34]	105	1			T86	1		T241	1		T243	1
values[35]	107	1			T86	1		T241	1		T243	1
values[36]	72	1			T86	1		T241	1		T243	1
values[37]	62	1			T86	1		T241	1		T243	1
values[38]	71	1			T86	1		T241	1		T243	1
values[39]	90	1			T86	1		T241	1		T243	1
values[40]	56	1			T86	1		T241	1		T243	1
values[41]	49	1			T86	1		T241	1		T243	1
values[42]	58	1			T86	1		T241	1		T243	1
values[43]	64	1			T86	1		T241	1		T243	1
values[44]	73	1			T86	1		T241	1		T243	1
values[45]	75	1			T86	1		T241	1		T243	1
values[46]	87	1			T86	1		T241	1		T243	1
values[47]	100	1			T86	1		T241	1		T243	1
values[48]	93	1			T86	1		T241	1		T243	1
values[49]	78	1			T86	1		T241	1		T243	1
values[50]	66	1			T86	1		T241	1		T243	1
values[51]	58	1			T86	1		T241	1		T243	1
values[52]	55	1			T86	1		T241	1		T243	1
values[53]	57	1			T86	1		T241	1		T243	1
values[54]	94	1			T86	1		T241	1		T243	1
values[55]	103	1			T86	1		T241	1		T243	1
values[56]	67	1			T86	1		T241	1		T243	1
values[57]	61	1			T86	1		T241	1		T243	1
values[58]	49	1			T86	1		T241	1		T243	1
values[59]	56	1			T86	1		T241	1		T243	1
values[60]	56	1			T86	1		T241	1		T243	1
values[61]	69	1			T86	1		T241	1		T243	1
values[62]	47	1			T86	1		T241	1		T243	1
values[63]	45	1			T86	1		T241	1		T243	1
values[64]	49	1			T86	1		T241	1		T243	1
values[65]	47	1			T86	1		T241	1		T243	1
values[66]	39	1			T86	1		T241	1		T243	1
values[67]	41	1			T86	1		T241	1		T243	1
values[68]	31	1			T86	1		T241	1		T243	2
values[69]	35	1			T86	1		T241	1		T243	1
values[70]	45	1			T86	1		T241	1		T243	1
values[71]	37	1			T86	1		T241	1		T243	1
values[72]	36	1			T86	1		T241	1		T243	1
values[73]	39	1			T86	1		T241	1		T243	1
values[74]	39	1			T86	1		T241	1		T243	1
values[75]	31	1			T86	1		T241	1		T243	1
values[76]	54	1			T86	1		T241	1		T243	1
values[77]	51	1			T86	1		T241	1		T243	1
values[78]	53	1			T86	1		T241	1		T243	1
values[79]	54	1			T86	1		T241	1		T243	1
values[80]	54	1			T86	1		T241	1		T243	1
values[81]	46	1			T86	1		T241	1		T243	1
values[82]	35	1			T86	1		T241	1		T243	1
values[83]	65	1			T86	1		T241	1		T243	1
values[84]	60	1			T86	1		T241	1		T243	1
values[85]	42	1			T86	1		T241	1		T243	1
values[86]	58	1			T86	1		T241	1		T243	1
values[87]	56	1			T86	1		T241	1		T243	1
values[88]	56	1			T86	1		T241	1		T243	1
values[89]	69	1			T86	1		T241	1		T243	1
values[90]	74	1			T86	1		T241	1		T243	1
values[91]	65	1			T86	1		T241	1		T243	1
values[92]	54	1			T86	1		T241	1		T243	1
values[93]	53	1			T86	1		T241	2		T243	1
values[94]	51	1			T86	1		T241	1		T243	1
values[95]	80	1			T86	1		T241	1		T243	1
values[96]	66	1			T86	1		T241	1		T243	1
values[97]	66	1			T86	1		T241	1		T243	1
values[98]	84	1			T86	1		T241	1		T243	1
values[99]	55	1			T86	1		T241	1		T243	1
values[100]	56	1			T86	1		T241	1		T243	1
values[101]	67	1			T86	3		T241	1		T243	1
values[102]	57	1			T86	3		T241	1		T243	1
values[103]	66	1			T86	1		T241	1		T243	1
values[104]	56	1			T86	3		T241	1		T243	1
values[105]	61	1			T86	4		T241	1		T243	1
values[106]	58	1			T86	4		T241	1		T243	1
values[107]	69	1			T86	7		T241	1		T243	1
values[108]	70	1			T86	1		T241	1		T243	1
values[109]	76	1			T86	2		T241	1		T243	1
values[110]	62	1			T86	1		T241	1		T243	1
values[111]	56	1			T86	1		T241	1		T243	1
values[112]	72	1			T86	1		T241	1		T243	1
values[113]	61	1			T86	3		T241	1		T243	1
values[114]	71	1			T86	4		T241	1		T243	1
values[115]	49	1			T86	2		T241	1		T243	1
values[116]	65	1			T86	1		T241	1		T243	1
values[117]	58	1			T86	1		T241	1		T243	1
values[118]	56	1			T86	1		T241	1		T243	1
values[119]	68	1			T86	1		T241	1		T243	1
values[120]	53	1			T86	1		T241	1		T243	1
values[121]	66	1			T86	1		T241	1		T243	1
values[122]	72	1			T86	2		T241	1		T243	4
values[123]	62	1			T86	2		T241	1		T243	2
values[124]	71	1			T86	2		T241	1		T243	2
values[125]	101	1			T86	4		T241	4		T243	3
values[126]	322	1			T86	18		T241	16		T243	15
values[127]	1568	1			T86	107		T241	104		T243	96
values[128]	2943	1			T86	176		T241	259		T243	177