Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	172274	1			T1	94		T2	7		T3	383
values[2]	5887	1			T3	12		T7	6		T8	5
values[3]	2037	1			T45	1		T17	37		T19	57
values[4]	1461	1			T17	34		T19	20		T156	1
values[5]	1112	1			T17	44		T19	2		T156	1
values[6]	941	1			T17	30		T19	2		T156	1
values[7]	865	1			T17	28		T156	1		T78	7
values[8]	812	1			T17	30		T156	1		T78	2
values[9]	696	1			T17	24		T156	1		T78	1
values[10]	713	1			T17	17		T156	1		T78	2
values[11]	591	1			T17	21		T156	1		T78	2
values[12]	465	1			T17	20		T156	1		T78	1
values[13]	451	1			T17	29		T156	1		T78	2
values[14]	330	1			T17	32		T156	1		T78	4
values[15]	275	1			T17	15		T156	1		T78	3
values[16]	255	1			T17	20		T156	1		T78	3
values[17]	286	1			T17	9		T156	1		T78	1
values[18]	303	1			T17	4		T156	1		T78	2
values[19]	261	1			T156	1		T78	2		T86	2
values[20]	249	1			T156	1		T78	1		T86	2
values[21]	202	1			T156	1		T78	2		T86	2
values[22]	170	1			T156	1		T78	2		T86	2
values[23]	161	1			T156	1		T78	2		T86	2
values[24]	195	1			T156	1		T78	2		T86	3
values[25]	143	1			T156	1		T78	2		T86	2
values[26]	141	1			T156	1		T78	2		T86	2
values[27]	141	1			T156	1		T78	1		T86	2
values[28]	109	1			T156	1		T78	3		T86	2
values[29]	117	1			T156	1		T78	1		T86	2
values[30]	151	1			T156	1		T78	1		T86	2
values[31]	139	1			T156	1		T78	4		T86	2
values[32]	101	1			T156	1		T78	2		T86	2
values[33]	90	1			T156	1		T78	7		T86	2
values[34]	85	1			T156	1		T78	5		T86	2
values[35]	83	1			T156	1		T78	4		T86	2
values[36]	68	1			T156	1		T78	2		T86	2
values[37]	55	1			T156	1		T78	4		T86	2
values[38]	58	1			T156	1		T78	2		T86	2
values[39]	55	1			T156	1		T78	1		T86	2
values[40]	59	1			T156	1		T78	2		T86	2
values[41]	53	1			T156	1		T78	3		T86	2
values[42]	44	1			T156	1		T78	1		T86	2
values[43]	59	1			T156	1		T78	5		T86	2
values[44]	58	1			T156	1		T78	3		T86	2
values[45]	48	1			T156	1		T78	1		T86	2
values[46]	41	1			T156	1		T78	5		T86	2
values[47]	35	1			T156	1		T78	4		T86	2
values[48]	37	1			T156	1		T78	2		T86	2
values[49]	37	1			T156	1		T78	5		T86	2
values[50]	35	1			T156	1		T78	1		T86	2
values[51]	34	1			T156	1		T78	1		T86	2
values[52]	33	1			T156	1		T78	2		T86	2
values[53]	39	1			T156	1		T78	5		T86	2
values[54]	33	1			T156	1		T78	1		T86	2
values[55]	34	1			T156	1		T78	3		T86	2
values[56]	30	1			T156	1		T78	5		T86	2
values[57]	35	1			T156	1		T78	3		T86	2
values[58]	32	1			T156	1		T78	1		T86	2
values[59]	33	1			T156	1		T78	2		T86	2
values[60]	39	1			T156	1		T78	4		T86	2
values[61]	44	1			T156	1		T78	6		T86	2
values[62]	47	1			T156	1		T78	9		T86	2
values[63]	39	1			T156	1		T78	4		T86	2
values[64]	28	1			T156	1		T78	2		T86	2
values[65]	37	1			T156	1		T78	2		T86	2
values[66]	37	1			T156	1		T78	2		T86	2
values[67]	36	1			T156	1		T78	2		T86	2
values[68]	35	1			T156	1		T78	4		T86	2
values[69]	47	1			T156	1		T78	3		T86	2
values[70]	39	1			T156	1		T78	3		T86	2
values[71]	44	1			T156	1		T78	3		T86	2
values[72]	29	1			T156	1		T78	1		T86	2
values[73]	32	1			T156	1		T78	2		T86	2
values[74]	35	1			T156	1		T78	2		T86	2
values[75]	30	1			T156	1		T78	1		T86	2
values[76]	28	1			T156	1		T78	1		T86	2
values[77]	30	1			T156	1		T78	2		T86	2
values[78]	32	1			T156	1		T78	1		T86	2
values[79]	32	1			T156	1		T78	2		T86	2
values[80]	42	1			T156	1		T78	3		T86	2
values[81]	51	1			T156	1		T78	3		T86	2
values[82]	56	1			T156	1		T78	5		T86	2
values[83]	41	1			T156	1		T78	1		T86	2
values[84]	39	1			T156	1		T78	3		T86	2
values[85]	43	1			T156	1		T78	1		T86	2
values[86]	47	1			T156	1		T78	1		T86	2
values[87]	55	1			T156	1		T78	4		T86	3
values[88]	50	1			T156	7		T78	2		T86	5
values[89]	41	1			T156	1		T78	1		T86	2
values[90]	58	1			T156	4		T78	2		T86	6
values[91]	52	1			T156	4		T78	1		T86	4
values[92]	50	1			T156	3		T78	2		T86	4
values[93]	66	1			T156	1		T78	5		T86	6
values[94]	51	1			T156	5		T78	4		T86	7
values[95]	60	1			T156	9		T78	2		T86	3
values[96]	62	1			T156	2		T78	6		T86	5
values[97]	53	1			T156	3		T78	2		T86	6
values[98]	54	1			T156	2		T78	2		T86	10
values[99]	48	1			T156	4		T78	3		T86	2
values[100]	42	1			T156	1		T78	3		T86	2
values[101]	52	1			T156	2		T78	3		T86	2
values[102]	52	1			T156	1		T78	1		T86	2
values[103]	54	1			T156	2		T78	2		T86	4
values[104]	52	1			T156	2		T78	2		T86	3
values[105]	56	1			T156	3		T78	4		T86	3
values[106]	54	1			T156	3		T78	3		T86	4
values[107]	71	1			T156	6		T78	6		T86	2
values[108]	75	1			T156	3		T78	6		T86	3
values[109]	62	1			T156	1		T78	3		T86	2
values[110]	54	1			T156	1		T78	1		T86	2
values[111]	62	1			T156	5		T78	3		T86	2
values[112]	46	1			T156	1		T78	5		T86	2
values[113]	53	1			T156	1		T78	4		T86	2
values[114]	47	1			T156	1		T78	3		T86	3
values[115]	61	1			T156	2		T78	5		T86	2
values[116]	60	1			T156	1		T78	2		T86	3
values[117]	63	1			T156	2		T78	1		T86	5
values[118]	61	1			T156	2		T78	2		T86	3
values[119]	62	1			T156	1		T78	4		T86	3
values[120]	53	1			T156	2		T78	5		T86	3
values[121]	44	1			T156	1		T78	2		T86	2
values[122]	60	1			T156	3		T78	4		T86	2
values[123]	71	1			T156	3		T78	13		T86	3
values[124]	113	1			T156	3		T78	19		T86	2
values[125]	155	1			T156	1		T78	48		T86	2
values[126]	481	1			T156	19		T78	69		T86	40
values[127]	2553	1			T156	95		T78	41		T86	208
values[128]	4915	1			T156	172		T78	3		T86	425