Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 484 1 T10 4 T67 2 T75 1
all_values[1] 479 1 T3 1 T10 1 T14 1
all_values[2] 540 1 T10 3 T17 1 T19 2
all_values[3] 474 1 T10 4 T19 3 T67 1
all_values[4] 514 1 T10 3 T14 1 T75 1
all_values[5] 487 1 T10 7 T17 4 T19 1
all_values[6] 492 1 T3 1 T10 5 T19 2
all_values[7] 494 1 T10 4 T14 1 T22 1
all_values[8] 506 1 T10 6 T17 1 T19 1
all_values[9] 470 1 T3 1 T10 6 T67 1
all_values[10] 487 1 T3 1 T10 4 T14 1
all_values[11] 491 1 T10 4 T17 1 T19 4
all_values[12] 516 1 T3 2 T10 3 T17 2
all_values[13] 460 1 T3 1 T10 7 T14 2
all_values[14] 482 1 T10 6 T17 2 T19 1
all_values[15] 489 1 T10 1 T19 2 T67 2
all_values[16] 490 1 T10 2 T19 1 T67 1
all_values[17] 466 1 T10 4 T14 1 T19 1
all_values[18] 501 1 T10 3 T14 1 T19 1
all_values[19] 479 1 T3 1 T10 5 T14 1
all_values[20] 472 1 T3 1 T10 7 T14 1
all_values[21] 507 1 T3 2 T10 7 T19 1
all_values[22] 502 1 T3 1 T10 6 T14 1
all_values[23] 499 1 T10 5 T14 2 T17 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%